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<header class="paper-header">
  <span class="paper-phase">Phase 2</span>
  <h1>Real-Time Control Loop Design for Software-Defined Power Tool Battery Adapters</h1>
  <div class="paper-meta">
    <p>Matthew Long &mdash; The YonedaAI Collaboration, YonedaAI Research Collective, Chicago, IL</p>
    <p>March 2026</p>
  </div>
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<main class="paper-content">

  <div class="paper-notice">
    This is the HTML summary version. <a href="../pdf/control-loop.pdf">Download the full PDF</a> for complete formatting, derivations, and simulation plots.
  </div>

  <h2>Abstract</h2>
  <p>
    This paper presents a comprehensive control systems design for the VoltForge adapter, covering classical PID control, state-space methods, and linear-quadratic regulator (LQR) optimal control applied to buck and boost converter plant models derived from Phase 1. We develop a cascaded current-inner/voltage-outer loop architecture, perform rigorous stability analysis via Bode, root locus, and Nyquist techniques, and characterize closed-loop performance against realistic power tool load profiles. Simulation results demonstrate sub-millisecond transient response, less than 2% overshoot, and robust disturbance rejection.
  </p>

  <h2>1. Introduction</h2>
  <p>
    The control loop is what makes VoltForge "software-defined" &mdash; it is not merely a connector, but a profile-driven, real-time power translation layer. Within the four-layer architecture, the control loop occupies Layer 2: the Real-Time Control Kernel, executing at 50 kHz with a hard deadline of $20\,\mu\text{s}$.
  </p>
  <p>
    The adapter operates through a deterministic state machine: Init &rarr; SelfTest &rarr; Detect Battery &rarr; Verify Chemistry/Voltage &rarr; Verify Tool Class &rarr; Precharge &rarr; Enable Output &rarr; Monitor Runtime &rarr; Derate &rarr; Shutdown on Fault.
  </p>

  <h2>2. Background: Control Theory Foundations</h2>

  <h3>Classical Control</h3>
  <p>A plant $G(s)$ with controller $C(s)$ forms a closed-loop system with characteristic equation:</p>
  $$1 + C(s)\,G(s) = 0$$
  <p>The closed-loop transfer function:</p>
  $$T(s) = \frac{C(s)\,G(s)}{1 + C(s)\,G(s)}$$

  <h3>Modern Control: State-Space Methods</h3>
  <p>State-space representation with state feedback $\mathbf{u} = -\mathbf{K}\mathbf{x} + \mathbf{N}r$:</p>
  $$\dot{\mathbf{x}} = \mathbf{A}\mathbf{x} + \mathbf{B}\mathbf{u}, \quad y = \mathbf{C}\mathbf{x}$$

  <h3>Frequency-Domain Analysis</h3>
  <p>Stability margins: gain margin (GM) and phase margin (PM) characterize robustness. Target: PM &gt; 45&deg;, GM &gt; 6 dB.</p>

  <h2>3. Plant Modeling</h2>

  <h3>Buck Converter State-Space Model</h3>
  <p>From Phase 1, the averaged state-space model with state vector $\mathbf{x} = [i_L, v_C]^T$:</p>
  $$\mathbf{A} = \begin{bmatrix} -\frac{R_L}{L} & -\frac{1}{L} \\ \frac{1}{C} & -\frac{1}{RC} \end{bmatrix}, \quad \mathbf{B} = \begin{bmatrix} \frac{V_{\text{in}}}{L} \\ 0 \end{bmatrix}$$

  <h3>Transfer Function Derivation</h3>
  <p>Control-to-inductor-current transfer function:</p>
  $$G_{id}(s) = \frac{\hat{i}_L(s)}{\hat{d}(s)} = V_{\text{in}} \cdot \frac{s + \frac{1}{RC}}{s^2 + s\left(\frac{1}{RC} + \frac{R_L}{L}\right) + \frac{1}{LC}}$$

  <h3>Numerical Plant Parameters</h3>
  <table>
    <thead><tr><th>Parameter</th><th>Value</th></tr></thead>
    <tbody>
      <tr><td>Input voltage $V_{\text{in}}$</td><td>20 V (DeWalt 20V MAX)</td></tr>
      <tr><td>Output voltage $V_{\text{out}}$</td><td>18 V</td></tr>
      <tr><td>Inductance $L$</td><td>$10\,\mu\text{H}$</td></tr>
      <tr><td>Output capacitance $C$</td><td>$200\,\mu\text{F}$</td></tr>
      <tr><td>Load resistance $R$</td><td>$1.2\,\Omega$ (15 A)</td></tr>
      <tr><td>Switching frequency $f_s$</td><td>100 kHz</td></tr>
    </tbody>
  </table>

  <h2>4. PID Controller Design</h2>

  <h3>Cascaded Control Architecture</h3>
  <p>
    The VoltForge adapter employs a cascaded (dual-loop) architecture: an inner current loop and an outer voltage loop. The inner loop directly controls inductor current for immediate overcurrent protection. The outer loop regulates output voltage.
  </p>

  <h3>Inner Current Loop: Type II Compensator</h3>
  $$C_i(s) = K_{ci}\,\frac{s + \omega_{zi}}{s\,(s + \omega_{pi})}$$
  <p>The zero $\omega_{zi}$ cancels the plant's dominant pole; the high-frequency pole $\omega_{pi}$ attenuates switching ripple.</p>

  <h3>Outer Voltage Loop</h3>
  <p>
    Type III compensator providing two zeros and two poles plus an integrator, achieving high bandwidth while maintaining adequate phase margin.
  </p>

  <h3>Anti-Windup Strategy</h3>
  <p>
    Clamping-based anti-windup limits the integrator accumulation when the controller output saturates (duty cycle hits 0 or 1), preventing large overshoot during recovery from saturation.
  </p>

  <h3>Gain Scheduling</h3>
  <p>
    Since the converter's small-signal model varies with operating point (input voltage, load current), the PID gains are scheduled across the operating envelope via interpolation tables stored in flash.
  </p>

  <h2>5. State-Space Control Design</h2>

  <h3>Full State Feedback</h3>
  <p>Control law $\mathbf{u} = -\mathbf{K}\mathbf{x}$ with gain matrix computed via pole placement, targeting a 5 kHz closed-loop bandwidth with $\zeta = 0.7$.</p>

  <h3>Observer Design</h3>
  <p>Luenberger observer estimates unmeasured states from ADC readings, enabling full state feedback even when only output voltage is directly measured.</p>

  <h3>LQR Optimal Control</h3>
  <p>The linear-quadratic regulator minimizes the cost function:</p>
  $$J = \int_0^\infty \left( \mathbf{x}^T \mathbf{Q} \mathbf{x} + \mathbf{u}^T \mathbf{R} \mathbf{u} \right) dt$$
  <p>LQR provides optimal trade-off between state regulation and control effort, with guaranteed stability margins (60&deg; phase margin, infinite gain margin).</p>

  <h2>6. Stability Analysis</h2>
  <ul>
    <li><strong>Bode Plot:</strong> Crossover frequency 5 kHz, phase margin 52&deg;, gain margin 12 dB</li>
    <li><strong>Root Locus:</strong> All closed-loop poles in left half plane across operating range</li>
    <li><strong>Nyquist:</strong> No encirclements of $-1 + 0j$, confirming stability</li>
    <li><strong>Robustness:</strong> Stability maintained with &plusmn;30% parameter variation in L and C</li>
  </ul>

  <h2>7. Load Profile Response</h2>
  <table>
    <thead><tr><th>Tool</th><th>Profile</th><th>Current Range</th></tr></thead>
    <tbody>
      <tr><td>Drill/Driver</td><td>Bursty, near-zero idle</td><td>2&ndash;8 A avg, 5&ndash;20 A spikes</td></tr>
      <tr><td>Circular Saw</td><td>Continuous high draw</td><td>10&ndash;15 A steady, 20&ndash;30 A spikes</td></tr>
      <tr><td>Impact Driver</td><td>Pulsed spikes</td><td>Repetitive 15&ndash;25 A pulses</td></tr>
      <tr><td>Angle Grinder</td><td>Sustained + spikes</td><td>6&ndash;16 A continuous</td></tr>
    </tbody>
  </table>

  <h2>8. Digital Implementation</h2>

  <h3>Discretization Methods</h3>
  <p>
    Zero-order hold (ZOH) and Tustin/bilinear transform for converting continuous-time controllers to discrete-time. The PID controller in discrete form using the Tustin transform:
  </p>
  $$u[n] = u[n-1] + K_p(e[n] - e[n-1]) + K_i \frac{T_s}{2}(e[n] + e[n-1]) + K_d \frac{2}{T_s}(e[n] - 2e[n-1] + e[n-2])$$

  <h3>Fixed-Point Arithmetic</h3>
  <p>
    Q16.16 fixed-point representation for the control loop on Cortex-M4F without FPU usage for maximum determinism. All gains and state variables scaled to prevent overflow at maximum operating conditions.
  </p>

  <h2>9. Simulation Results</h2>
  <ul>
    <li>Step response: 0.8 ms rise time, 1.5% overshoot</li>
    <li>Disturbance rejection: 0.3 V deviation for 10 A load step, recovery in 0.5 ms</li>
    <li>Drill profile: voltage within $\pm 0.4$ V throughout spike sequence</li>
    <li>Saw profile: voltage maintained within $\pm 0.5$ V during 25 A stall</li>
  </ul>

  <h2>10. Rust Implementation</h2>
  <p>
    The control loop is implemented in <code>no_std</code> Rust with separate modules for PID controller, state-space controller, load profile detection, and discretization. Integration with RTIC/Embassy provides interrupt-driven scheduling with hardware-enforced priority levels.
  </p>

  <h2>11. Interface to Phase 3: Thermal Management</h2>
  <p>
    The control loop produces real-time power dissipation data: MOSFET losses (function of duty cycle and current), inductor losses, and total converter efficiency. This thermal dissipation profile feeds directly into Phase 3 thermal modeling as the heat source input.
  </p>

  <div class="insight-box">
    <p><strong>Phase 3 Interface:</strong> $P_{\text{dissipated}}(t) = P_{\text{in}}(t) - P_{\text{out}}(t)$ computed in real-time by the control loop becomes the heat source input for the Phase 3 thermal model.</p>
  </div>

  <h2>12. Conclusion</h2>
  <p>
    The cascaded PID architecture with gain scheduling achieves robust voltage regulation across the full operating envelope, with sub-millisecond transient response and less than 2% overshoot. The state-space and LQR alternatives provide additional design flexibility. The discrete-time implementation fits within the $20\,\mu\text{s}$ control period budget on STM32G4.
  </p>

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