From ea7bf468f82519162b850a9ed3f34b220f1ac7b4 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 16:01:13 +0900 Subject: [PATCH 01/98] arm: mediatek: dts: Add support for Lenovo YOGA Tablet 10 Wi-Fi (B8000-F) --- arch/arm/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt6589-lenovo-blade-b8000-f.dts | 11 +++++ .../dts/mediatek/mt6589-lenovo-blade.dtsi | 40 +++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts create mode 100644 arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile index 1957947cb41ce8..11761b916ccfcf 100644 --- a/arch/arm/boot/dts/mediatek/Makefile +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6582-prestigio-pmt5008-3g.dtb \ mt6589-aquaris5.dtb \ mt6589-fairphone-fp1.dtb \ + mt6589-lenovo-blade-b8000-f.dtb \ mt6592-evb.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts new file mode 100644 index 00000000000000..e59c4c3ce2f9a4 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 akku + */ + +#include "mt6589-lenovo-blade.dtsi" + +/ { + model = "Lenovo YOGA Tablet 10 (Wi-Fi)"; + compatible = "lenovo,blade-b8000-f", "lenovo,blade", "mediatek,mt6589"; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi new file mode 100644 index 00000000000000..38dd673b6fe31c --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2025 akku + */ + +/dts-v1/; +#include + +/ { + compatible = "lenovo,blade", "mediatek,mt6589"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mtkfb_region: memory@bf600000{ + reg = <0xbf600000 (1280 * 800 * 2 * 2)>; + no-map; + }; + }; + + framebuffer0: framebuffer@bf600000 { + compatible = "simple-framebuffer"; + reg = <0xbf600000 (1280 * 800 * 2)>; + width = <1280>; + height = <800>; + stride = <(1280 * 2)>; + format = "r5g6b5"; + }; +}; + +&uart0 { + status = "okay"; +}; From 7545697ac012d8bfbe4bf05f529d5ff87baf0433 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 16:35:28 +0900 Subject: [PATCH 02/98] arm: dts: mt6589: lenovo-blade: Clarify #address-cells and #size-cells --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 38dd673b6fe31c..e1740b322b35c3 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -7,6 +7,8 @@ #include / { + #address-cells = <1>; + #size-cells = <1>; compatible = "lenovo,blade", "mediatek,mt6589"; memory { @@ -15,8 +17,6 @@ }; reserved-memory { - #address-cells = <1>; - #size-cells = <1>; ranges; mtkfb_region: memory@bf600000{ From d3fc96a7d68baab1d7207f2cedd58636afa74877 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 16:48:13 +0900 Subject: [PATCH 03/98] arm: defconfig: add defconfig for Lenovo YOGA Tablet 8/10 --- arch/arm/configs/lenovo-blade_defconfig | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 arch/arm/configs/lenovo-blade_defconfig diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig new file mode 100644 index 00000000000000..bd15c57ae35bd3 --- /dev/null +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -0,0 +1,9 @@ +# Add MediaTek MT8125/MT8389 Support +CONFIG_ARCH_MEDIATEK=y +CONFIG_MACH_MT2701=n +CONFIG_MACH_MT6589=y +CONFIG_MACH_MT6592=n +CONFIG_MACH_MT7623=n +CONFIG_MACH_MT7629=n +CONFIG_MACH_MT8127=n +CONFIG_MACH_MT8135=n From 82d2379664029b64d8aa606b5877896749c3240e Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 16:52:44 +0900 Subject: [PATCH 04/98] arm: defconfig: lenovo-blade: add some features --- arch/arm/configs/lenovo-blade_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index bd15c57ae35bd3..bfef0fe184e163 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -7,3 +7,10 @@ CONFIG_MACH_MT7623=n CONFIG_MACH_MT7629=n CONFIG_MACH_MT8127=n CONFIG_MACH_MT8135=n + +CONFIG_VMSPLIT_3G_OPT=y + +CONFIG_FB_SIMPLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y + +CONFIG_KERNEL_GZIP=y From b13128557fdaa0fdbe2fdf693e1a4efc5b147405 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 16:55:18 +0900 Subject: [PATCH 05/98] arm: dts: mt6589: lenovo-blade: fix wrong include --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index e1740b322b35c3..cae24fb6817e08 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -4,7 +4,7 @@ */ /dts-v1/; -#include +#include "mt6589.dtsi" / { #address-cells = <1>; From ebc0df8d8f7a022741378ea8638948ae9dc07fee Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 30 Aug 2025 17:02:59 +0900 Subject: [PATCH 06/98] arm: dts: mt6589: lenovo-blade: add #address-cells and #size-cells in reserved_memory node --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index cae24fb6817e08..4afddce051af7a 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -17,6 +17,9 @@ }; reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; mtkfb_region: memory@bf600000{ From 55d721c731a0fed1b1ceef4977c8d43291dab36b Mon Sep 17 00:00:00 2001 From: -akku- Date: Sun, 31 Aug 2025 17:29:54 +0900 Subject: [PATCH 07/98] arm: dts: mt6589: lenovo-blade: fix Device Tree --- arch/arm/configs/lenovo-blade_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index bfef0fe184e163..fc97a57d08def3 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -1,3 +1,4 @@ +### SoC # Add MediaTek MT8125/MT8389 Support CONFIG_ARCH_MEDIATEK=y CONFIG_MACH_MT2701=n @@ -10,7 +11,13 @@ CONFIG_MACH_MT8135=n CONFIG_VMSPLIT_3G_OPT=y +### Drivers +## Framebuffer +CONFIG_FB=y CONFIG_FB_SIMPLE=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_KERNEL_GZIP=y + +### Hacking +CONFIG_ARM_APPENDED_DTB=y From fd46a4873e09acbda9a9b2b44318a7e3bb0a56fd Mon Sep 17 00:00:00 2001 From: -akku- Date: Sun, 31 Aug 2025 20:46:38 +0900 Subject: [PATCH 08/98] arm: dts: mt6589: lenovo-blade: make initramfs recognized correctly --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 4afddce051af7a..3f558471e774b4 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -11,6 +11,10 @@ #size-cells = <1>; compatible = "lenovo,blade", "mediatek,mt6589"; + chosen { + linux,initrd-start = <0x82600000>; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; From d141503649df4e2bbe695d8e4854c6c2f841ad0c Mon Sep 17 00:00:00 2001 From: -akku- Date: Sun, 31 Aug 2025 20:48:07 +0900 Subject: [PATCH 09/98] arm: defconfig: lenovo-blade: setup drivers --- arch/arm/configs/lenovo-blade_defconfig | 26 +++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index fc97a57d08def3..20c6e3b69b103c 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -8,16 +8,38 @@ CONFIG_MACH_MT7623=n CONFIG_MACH_MT7629=n CONFIG_MACH_MT8127=n CONFIG_MACH_MT8135=n - -CONFIG_VMSPLIT_3G_OPT=y +CONFIG_SMP=y +CONFIG=PHYS_OFFSET=0x80000000 ### Drivers +CONFIG_OF=y ## Framebuffer CONFIG_FB=y CONFIG_FB_SIMPLE=y CONFIG_FRAMEBUFFER_CONSOLE=y +## Clock +CONFIG_HAVE_CLK=y +CONFIG_COMMON_CLK=y +## Timer +CONFIG_TIMER_OF=y +CONFIG_MTK_TIMER=y +## Watchdog +CONFIG_WATCHDOG=y +CONFIG_MEDIATEK_WATCHDOG=y +## UART +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_MT6577=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_8250_CONSOLE=y +### Initramfs +CONFIG_BLK_DEV_INITRD=y + +### Other CONFIG_KERNEL_GZIP=y +CONFIG_VMSPLIT_3G_OPT=y ### Hacking CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y From 638c6e00756fc9fffa5dd4ba47d2f8658bbdd11d Mon Sep 17 00:00:00 2001 From: -akku- Date: Sun, 31 Aug 2025 21:25:54 +0900 Subject: [PATCH 10/98] arm: defconfig: lenovo-blade: fix and add configs --- arch/arm/configs/lenovo-blade_defconfig | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 20c6e3b69b103c..a18ac24aeed3e2 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -9,7 +9,6 @@ CONFIG_MACH_MT7629=n CONFIG_MACH_MT8127=n CONFIG_MACH_MT8135=n CONFIG_SMP=y -CONFIG=PHYS_OFFSET=0x80000000 ### Drivers CONFIG_OF=y @@ -34,6 +33,7 @@ CONFIG_SERIAL_8250_CONSOLE=y ### Initramfs CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_RAM=y ### Other CONFIG_KERNEL_GZIP=y @@ -43,3 +43,7 @@ CONFIG_VMSPLIT_3G_OPT=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y + +### postmarketOS (must be removed!!!!!) +CONFIG_DEVTMPFS=y +CONFIG_SYSVIPC=y From 0533855dd58284e13006a2150ec2ef5b8eb085ca Mon Sep 17 00:00:00 2001 From: -akku- Date: Thu, 4 Sep 2025 23:03:13 +0900 Subject: [PATCH 11/98] arm: dts: mediatek: mt6589: add topckgen --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index c6babc8ad2ba6c..78d45c86e874ab 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -65,6 +65,14 @@ clock-frequency = <26000000>; #clock-cells = <0>; }; + + topckgen: syscon@f0000000 { + compatible = "mediatek,mt6589-topckgen", + "mediatek,mt2701-topckgen", + "syscon"; + reg = <0xf0000000 0x1000>; + #clock-cells = <1>; + }; }; soc { From 7e0b29af0ca269fcb48b94cbdfb0a7571862f6a1 Mon Sep 17 00:00:00 2001 From: -akku- Date: Thu, 4 Sep 2025 23:05:21 +0900 Subject: [PATCH 12/98] arm: defconfig: lenovo-blade: add mt2701 clock driver --- arch/arm/configs/lenovo-blade_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index a18ac24aeed3e2..cf02c09c404d52 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -19,6 +19,8 @@ CONFIG_FRAMEBUFFER_CONSOLE=y ## Clock CONFIG_HAVE_CLK=y CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MEDIATEK=y +CONFIG_COMMON_CLK_MT2701=y ## Timer CONFIG_TIMER_OF=y CONFIG_MTK_TIMER=y From a048c60fa8ff07d3af237aabda3c92cc4c42d130 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 6 Sep 2025 21:08:30 +0900 Subject: [PATCH 13/98] Revert "arm: defconfig: lenovo-blade: add mt2701 clock driver" This reverts commit 7e0b29af0ca269fcb48b94cbdfb0a7571862f6a1. --- arch/arm/configs/lenovo-blade_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index cf02c09c404d52..a18ac24aeed3e2 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -19,8 +19,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y ## Clock CONFIG_HAVE_CLK=y CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y ## Timer CONFIG_TIMER_OF=y CONFIG_MTK_TIMER=y From 575e110ce3f74271153687141c4f914f83e6f57f Mon Sep 17 00:00:00 2001 From: -akku- Date: Sat, 6 Sep 2025 21:08:37 +0900 Subject: [PATCH 14/98] Revert "arm: dts: mediatek: mt6589: add topckgen" This reverts commit 0533855dd58284e13006a2150ec2ef5b8eb085ca. --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 78d45c86e874ab..c6babc8ad2ba6c 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -65,14 +65,6 @@ clock-frequency = <26000000>; #clock-cells = <0>; }; - - topckgen: syscon@f0000000 { - compatible = "mediatek,mt6589-topckgen", - "mediatek,mt2701-topckgen", - "syscon"; - reg = <0xf0000000 0x1000>; - #clock-cells = <1>; - }; }; soc { From 32749c5e80a99cef9f2d94c64954e86b228c88f6 Mon Sep 17 00:00:00 2001 From: -akku- Date: Sun, 7 Sep 2025 16:15:11 +0900 Subject: [PATCH 15/98] arm: defconfig: lenovo-blade: add some drivers --- arch/arm/configs/lenovo-blade_defconfig | 117 ++++++++++++++++++++++-- 1 file changed, 110 insertions(+), 7 deletions(-) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index a18ac24aeed3e2..cbd0c4de178852 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -1,36 +1,139 @@ ### SoC -# Add MediaTek MT8125/MT8389 Support +## MediaTek MT8125/MT8389 basic support CONFIG_ARCH_MEDIATEK=y -CONFIG_MACH_MT2701=n CONFIG_MACH_MT6589=y -CONFIG_MACH_MT6592=n -CONFIG_MACH_MT7623=n -CONFIG_MACH_MT7629=n -CONFIG_MACH_MT8127=n -CONFIG_MACH_MT8135=n CONFIG_SMP=y +CONFIG_MODULES=y + ### Drivers CONFIG_OF=y +# Automatically enabled +CONFIG_MTK_INFRACFG=y + +# is needed? +#CONFIG_INTERCONNECT=y +#CONFIG_INTERCONNECT_MTK=y + +## CPU +CONFIG_CPU_IDLE=y +CONFIG_ARM_CPUIDLE=y +#CONFIG_CPUFREQ_DT=y +#CONFIG_CPU_FREQ=y +#CONFIG_ARM_MEDIATEK_CPUFREQ_HW=y # not ported + +## IOMMU +CONFIG_IOMMU_SUPPORT=y +# MediaTek M4U +#CONFIG_MTK_IOMMU=y + +## Display + ## Framebuffer CONFIG_FB=y CONFIG_FB_SIMPLE=y CONFIG_FRAMEBUFFER_CONSOLE=y + ## Clock CONFIG_HAVE_CLK=y CONFIG_COMMON_CLK=y + ## Timer CONFIG_TIMER_OF=y CONFIG_MTK_TIMER=y + ## Watchdog CONFIG_WATCHDOG=y CONFIG_MEDIATEK_WATCHDOG=y + ## UART CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_8250_CONSOLE=y +## I2C +CONFIG_I2C=y +CONFIG_I2C_MT65XX=y + +## SPI +CONFIG_SPI=y +CONFIG_SPI_MT65XX=y + +## Pinctrl +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MTK=y +CONFIG_EINT_MTK=y +#CONFIG_PINCTRL_MT6589=y # not ported + +## GPIO + +## DMA +#CONFIG_DMADEVICES=y + +## USB +CONFIG_USB_SUPPORT=y +CONFIG_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_MUSB_HDRC=y +CONFIG_USB_MUSB_MEDIATEK=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_SERIAL=y +#CONFIG_PHY_MTK_TPHY=y # is needed? + +## MMC (eMMC/SD) +CONFIG_MMC=y +CONFIG_MMC_MTK=y + +## Touchscreen +#CONFIG_INPUT_TOUCHSCREEN=y +#CONFIG_TOUCHSCREEN_S7300=y # not ported + +## PMIC +#CONFIG_MTK_PMIC_WRAP=y + +## Power ? +#CONFIG_POWER_RESET=y + +## Reset +#CONFIG_RESET_CONTROLLER + +## Battery + +## Audio + +## Video Accelerator + +## GPU +#CONFIG_SGX=y # not ported + +## Wi-Fi / Bluetooth + +## Thermal + +## Modem + +## GPS + +## Camera + +## PWM +#CONFIG_PWM=y +#CONFIG_PWM_MEDIATEK +#CONFIG_PWM_MTK_DISP=y + +## RTC +#CONFIG_RTC_CLASS=y +#CONFIG_RTC_DRV_MT7622=y + +## Android +#CONFIG_ANDROID_BINDER_IPC=y + +### FS +CONFIG_UNICODE=y +CONFIG_EXT4_FS=y +CONFIG_VFAT_FS=y + ### Initramfs CONFIG_BLK_DEV_INITRD=y CONFIG_BLK_DEV_RAM=y From 8f5bed3a98d4c6e1041d35c50b15ac835163b8e0 Mon Sep 17 00:00:00 2001 From: -akku- Date: Mon, 15 Sep 2025 13:42:32 +0900 Subject: [PATCH 16/98] arm: defconfig: lenovo-blade: enable FPU --- arch/arm/configs/lenovo-blade_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index cbd0c4de178852..1024989f272095 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -3,6 +3,10 @@ CONFIG_ARCH_MEDIATEK=y CONFIG_MACH_MT6589=y CONFIG_SMP=y +CONFIG_VFP=y +CONFIG_NEON=y +# auto select +CONFIG_VFPv3=y CONFIG_MODULES=y From 4ec9bf60020cfce06c99fa498cfd2779ed706f30 Mon Sep 17 00:00:00 2001 From: -akku- Date: Mon, 15 Sep 2025 15:59:26 +0900 Subject: [PATCH 17/98] arm: defconfig: lenovo-blade: add some configs --- arch/arm/configs/lenovo-blade_defconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 1024989f272095..e82b0cd1cbb809 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -1,5 +1,6 @@ ### SoC ## MediaTek MT8125/MT8389 basic support +CONFIG_ARM=y CONFIG_ARCH_MEDIATEK=y CONFIG_MACH_MT6589=y CONFIG_SMP=y @@ -7,6 +8,8 @@ CONFIG_VFP=y CONFIG_NEON=y # auto select CONFIG_VFPv3=y +CONFIG_ARM_THUMBEE=y +CONFIG_SCHED_MC=y CONFIG_MODULES=y @@ -133,10 +136,21 @@ CONFIG_MMC_MTK=y ## Android #CONFIG_ANDROID_BINDER_IPC=y +## Block Device +CONFIG_BLK_DEV_LOOP=y + ### FS CONFIG_UNICODE=y CONFIG_EXT4_FS=y CONFIG_VFAT_FS=y +# VFAT +CONFIG_NLS_CODEPAGE_437=y +# VFAT +CONFIG_NLS_ISO8859_1=y +CONFIG_TMPFS=y +# pmOS +CONFIG_DEVTMPFS_MOUNT=n +CONFIG_CONFIGFS_FS=y ### Initramfs CONFIG_BLK_DEV_INITRD=y @@ -145,6 +159,7 @@ CONFIG_BLK_DEV_RAM=y ### Other CONFIG_KERNEL_GZIP=y CONFIG_VMSPLIT_3G_OPT=y +CONFIG_THUMB2_KERNEL=y ### Hacking CONFIG_ARM_APPENDED_DTB=y @@ -154,3 +169,5 @@ CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y ### postmarketOS (must be removed!!!!!) CONFIG_DEVTMPFS=y CONFIG_SYSVIPC=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CGROUPS=y From 8eb30a10091130139a3a33cf693c84a87610eb72 Mon Sep 17 00:00:00 2001 From: "Akari Tsuyukusa (-akku-)" Date: Mon, 10 Nov 2025 19:33:10 +0900 Subject: [PATCH 18/98] dt-bindings: arm: mediatek: add Lenovo YOGA Tablet 8/10 family --- Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index a7e0a72f6e4cb8..4a24b68f6dcbb8 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -39,6 +39,11 @@ properties: - enum: - fairphone,fp1 - mundoreader,bq-aquaris5 + - lenovo,blade + - lenovo,blade-b8000-f + - lenovo,blade-b8000-h + - lenovo,blade-b6000-f + - lenovo,blade-b8000-h - const: mediatek,mt6589 - items: - enum: From a0e4d6afc304535eeaf3e4e497fec834c29c5fb9 Mon Sep 17 00:00:00 2001 From: "Tsuyukusa Akari (-akku-)" Date: Fri, 2 Jan 2026 16:23:50 +0900 Subject: [PATCH 19/98] clk: mediatek: add MT6589 clock drivers --- .../arm/mediatek/mediatek,audsys.yaml | 1 + .../bindings/clock/mediatek,apmixedsys.yaml | 1 + .../bindings/clock/mediatek,infracfg.yaml | 1 + .../bindings/clock/mediatek,pericfg.yaml | 1 + .../bindings/clock/mediatek,syscon.yaml | 5 + .../bindings/clock/mediatek,topckgen.yaml | 1 + .../dts/mediatek/mt6589-lenovo-blade.dtsi | 2 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 71 +++ arch/arm/configs/lenovo-blade_defconfig | 7 + drivers/clk/mediatek/Kconfig | 50 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 152 ++++++ drivers/clk/mediatek/clk-mt6589-aud.c | 53 ++ drivers/clk/mediatek/clk-mt6589-disp.c | 104 ++++ drivers/clk/mediatek/clk-mt6589-img.c | 67 +++ drivers/clk/mediatek/clk-mt6589-infracfg.c | 94 ++++ drivers/clk/mediatek/clk-mt6589-mfg.c | 59 +++ drivers/clk/mediatek/clk-mt6589-pericfg.c | 129 +++++ drivers/clk/mediatek/clk-mt6589-topckgen.c | 456 ++++++++++++++++++ drivers/clk/mediatek/clk-mt6589-vdec.c | 86 ++++ drivers/clk/mediatek/clk-mt6589-venc.c | 62 +++ drivers/clk/mediatek/clk-mtk.c | 18 +- drivers/clk/mediatek/clk-mtk.h | 2 + drivers/clk/mediatek/clk-pll.c | 31 +- include/dt-bindings/clock/mt6589-clk.h | 308 ++++++++++++ include/dt-bindings/reset/mt6589-resets.h | 71 +++ 26 files changed, 1825 insertions(+), 14 deletions(-) create mode 100644 drivers/clk/mediatek/clk-mt6589-apmixedsys.c create mode 100644 drivers/clk/mediatek/clk-mt6589-aud.c create mode 100644 drivers/clk/mediatek/clk-mt6589-disp.c create mode 100644 drivers/clk/mediatek/clk-mt6589-img.c create mode 100644 drivers/clk/mediatek/clk-mt6589-infracfg.c create mode 100644 drivers/clk/mediatek/clk-mt6589-mfg.c create mode 100644 drivers/clk/mediatek/clk-mt6589-pericfg.c create mode 100644 drivers/clk/mediatek/clk-mt6589-topckgen.c create mode 100644 drivers/clk/mediatek/clk-mt6589-vdec.c create mode 100644 drivers/clk/mediatek/clk-mt6589-venc.c create mode 100644 include/dt-bindings/clock/mt6589-clk.h create mode 100644 include/dt-bindings/reset/mt6589-resets.h diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index 45d4a6620041b1..1a6fd42f43a5a5 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -18,6 +18,7 @@ properties: - items: - enum: - mediatek,mt2701-audsys + - mediatek,mt6589-audsys - mediatek,mt6765-audsys - mediatek,mt6779-audsys - mediatek,mt7622-audsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml index 591a9e862c7d46..dfa3b2840c9af7 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml @@ -35,6 +35,7 @@ properties: - enum: - mediatek,mt2701-apmixedsys - mediatek,mt2712-apmixedsys + - mediatek,mt6589-apmixedsys - mediatek,mt6735-apmixedsys - mediatek,mt6765-apmixedsys - mediatek,mt6779-apmixed diff --git a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml index d1d30700d9b0e4..9b54493393ce96 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,infracfg.yaml @@ -23,6 +23,7 @@ properties: - enum: - mediatek,mt2701-infracfg - mediatek,mt2712-infracfg + - mediatek,mt6589-infracfg - mediatek,mt6735-infracfg - mediatek,mt6765-infracfg - mediatek,mt6795-infracfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml index b98cf45efe2f63..63c80a4ac2e8c2 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml @@ -20,6 +20,7 @@ properties: - enum: - mediatek,mt2701-pericfg - mediatek,mt2712-pericfg + - mediatek,mt6589-pericfg - mediatek,mt6735-pericfg - mediatek,mt6765-pericfg - mediatek,mt6795-pericfg diff --git a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml index a86a64893c675a..38c107ca301c6b 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,syscon.yaml @@ -28,6 +28,11 @@ properties: - mediatek,mt2712-mfgcfg - mediatek,mt2712-vdecsys - mediatek,mt2712-vencsys + - mediatek,mt6589-dispsys + - mediatek,mt6589-imgsys + - mediatek,mt6589-mfgsys + - mediatek,mt6589-vdecsys + - mediatek,mt6589-vencsys - mediatek,mt6735-imgsys - mediatek,mt6735-mfgcfg - mediatek,mt6735-vdecsys diff --git a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml index c080fb0a161819..82e1e602e62991 100644 --- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml +++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml @@ -32,6 +32,7 @@ properties: - enum: - mediatek,mt2701-topckgen - mediatek,mt2712-topckgen + - mediatek,mt6589-topckgen - mediatek,mt6735-topckgen - mediatek,mt6765-topckgen - mediatek,mt6779-topckgen diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 3f558471e774b4..af86a0f261488d 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -13,6 +13,8 @@ chosen { linux,initrd-start = <0x82600000>; + /* DEBUG: testing clock drivers */ + bootargs = "clk_ignore_unused"; }; memory { diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index c6babc8ad2ba6c..8603a2e9069aed 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -48,6 +48,13 @@ compatible = "simple-bus"; ranges; + clk26m: oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + system_clk: dummy13m { compatible = "fixed-clock"; clock-frequency = <13000000>; @@ -57,6 +64,7 @@ rtc_clk: dummy32k { compatible = "fixed-clock"; clock-frequency = <32000>; + clock-output-names = "rtc_clk"; #clock-cells = <0>; }; @@ -73,6 +81,68 @@ compatible = "simple-bus"; ranges; + topckgen: syscon@10000100 { + compatible = "mediatek,mt6589-topckgen", "syscon"; + reg = <0x10000100 0x7c>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt6589-infracfg", "syscon"; + reg = <0x10001000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt6589-pericfg", "syscon"; + reg = <0x10003000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mfgsys: syscon@10206000 { + compatible = "mediatek,mt6589-mfgsys", "syscon"; + reg = <0x10206000 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: syscon@10209000 { + compatible = "mediatek,mt6589-apmixedsys", "syscon"; + reg = <0x10209000 0x1000>; + #clock-cells = <1>; + }; + + audsys: syscon@12070000 { + compatible = "mediatek,mt6589-audsys", "syscon"; + reg = <0x12070000 0x1000>; + #clock-cells = <1>; + }; + + dispsys: syscon@14000000 { + compatible = "mediatek,mt6589-dispsys", "syscon"; + reg = <0x14000000 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@15000000 { + compatible = "mediatek,mt6589-imgsys", "syscon"; + reg = <0x15000000 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt6589-vdecsys", "syscon"; + reg = <0x16000000 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt6589-vencsys", "syscon"; + reg = <0x17000000 0x1000>; + #clock-cells = <1>; + }; + timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; @@ -133,6 +203,7 @@ status = "disabled"; }; + /* FIXME: Register area that overlaps with topckgen */ wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x44>; diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index e82b0cd1cbb809..9f1c2f63af3b51 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -44,6 +44,13 @@ CONFIG_FRAMEBUFFER_CONSOLE=y ## Clock CONFIG_HAVE_CLK=y CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_MT6589=y +CONFIG_COMMON_CLK_MT6589_AUDSYS=y +CONFIG_COMMON_CLK_MT6589_DISPSYS=y +CONFIG_COMMON_CLK_MT6589_IMGSYS=y +CONFIG_COMMON_CLK_MT6589_MFGSYS=y +CONFIG_COMMON_CLK_MT6589_VDECSYS=y +CONFIG_COMMON_CLK_MT6589_VENCSYS=y ## Timer CONFIG_TIMER_OF=y diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 5f8e6d68fa148d..948ef64beebba3 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -124,6 +124,56 @@ config COMMON_CLK_MT2712_VENCSYS help This driver supports MediaTek MT2712 vencsys clocks. +config COMMON_CLK_MT6589 + tristate "Main clock drivers for MediaTek MT6589" + depends on ARCH_MEDIATEK || COMPILE_TEST + select COMMON_CLK_MEDIATEK + help + This enables drivers for main clocks (topckgen, pericfg, + infracfg) on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_AUDSYS + tristate "Clock driver for MediaTek MT6589 audsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by audsys + on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_DISPSYS + tristate "Clock driver for MediaTek MT6589 dispsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by dispsys + on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_IMGSYS + tristate "Clock driver for MediaTek MT6589 imgsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by imgsys + on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_MFGSYS + tristate "Clock driver for MediaTek MT6589 mfgsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by mfgsys + on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_VDECSYS + tristate "Clock driver for MediaTek MT6589 vdecsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by vdecsys + on the MediaTek MT6589 SoC. + +config COMMON_CLK_MT6589_VENCSYS + tristate "Clock driver for MediaTek MT6589 vencsys" + depends on COMMON_CLK_MT6589 + help + This enables a driver for clocks provided by vencsys + on the MediaTek MT6589 SoC. + config COMMON_CLK_MT6735 tristate "Main clock drivers for MediaTek MT6735" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 6efec95406bd5c..0aecb18211e69d 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -2,6 +2,13 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o +obj-$(CONFIG_COMMON_CLK_MT6589) += clk-mt6589-apmixedsys.o clk-mt6589-infracfg.o clk-mt6589-pericfg.o clk-mt6589-topckgen.o +obj-$(CONFIG_COMMON_CLK_MT6589_AUDSYS) += clk-mt6589-aud.o +obj-$(CONFIG_COMMON_CLK_MT6589_DISPSYS) += clk-mt6589-disp.o +obj-$(CONFIG_COMMON_CLK_MT6589_IMGSYS) += clk-mt6589-img.o +obj-$(CONFIG_COMMON_CLK_MT6589_MFGSYS) += clk-mt6589-mfg.o +obj-$(CONFIG_COMMON_CLK_MT6589_VDECSYS) += clk-mt6589-vdec.o +obj-$(CONFIG_COMMON_CLK_MT6589_VENCSYS) += clk-mt6589-venc.o obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c new file mode 100644 index 00000000000000..0b436b7d3934a3 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include +#include + +#include "clk-pll.h" +#include "clk-mtk.h" + +#include + +#define AP_PLL_CON0 0x0000 +#define AP_PLL_CON1 0x0004 +#define AP_PLL_CON2 0x0008 +#define AP_PLL_CON3 0x000c + +#define PLL_HP_CON0 0x0014 + +#define ARMPLL_CON0 0x0200 +#define ARMPLL_CON1 0x0204 +#define ARMPLL_CON2 0x0208 +#define ARMPLL_PWR_CON0 0x0218 + +#define MAINPLL_CON0 0x021c +#define MAINPLL_CON1 0x0220 +#define MAINPLL_CON2 0x0224 +#define MAINPLL_PWR_CON0 0x0234 + +#define UNIVPLL_CON0 0x0238 +#define MMPLL_CON0 0x0240 +#define ISPPLL_CON0 0x0248 + +#define MSDCPLL_CON0 0x0250 +#define MSDCPLL_CON1 0x0254 +#define MSDCPLL_CON2 0x0258 +#define MSDCPLL_PWR_CON0 0x0268 + +#define TVDPLL_CON0 0x026c +#define TVDPLL_CON1 0x0270 +#define TVDPLL_CON2 0x0274 +#define TVDPLL_CON3 0x0278 +#define TVDPLL_PWR_CON0 0x0284 + +#define LVDSPLL_CON0 0x0288 +#define LVDSPLL_CON1 0x028c +#define LVDSPLL_CON2 0x0290 +#define LVDSPLL_CON3 0x0294 +#define LVDSPLL_PWR_CON0 0x02a0 + +#define VOID_REG 0x0 + +#define CON0_MT6589_RST_BAR BIT(27) + +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ + _pd_reg, _pd_shift, _pcw_reg, _pcw_shift, \ + _fmax) { \ + .id = _id, \ + .name = _name, \ + .reg = _reg, \ + .pwr_reg = _pwr_reg, \ + .en_mask = _en_mask, \ + .flags = _flags, \ + .rst_bar_mask = CON0_MT6589_RST_BAR, \ + .fmax = _fmax, \ + .pcwbits = _pcwbits, \ + .pd_reg = _pd_reg, \ + .pd_shift = _pd_shift, \ + .tuner_reg = VOID_REG, \ + .pcw_reg = _pcw_reg, \ + .pcw_shift = _pcw_shift, \ + } + +static const struct mtk_pll_data plls[] = { + PLL(CLK_APMIXED_ARMPLL, "armpll", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x80000001, + PLL_AO, 21, ARMPLL_CON1, 24, ARMPLL_CON1, 0, 1300000000), + PLL(CLK_APMIXED_MAINPLL, "mainpll", MAINPLL_CON0, MAINPLL_PWR_CON0, 0xf0000001, + HAVE_RST_BAR, 21, MAINPLL_CON0, 6, MAINPLL_CON1, 0, 1612000000), + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", MSDCPLL_CON0, MSDCPLL_PWR_CON0, 0x80000001, + 0, 21, MSDCPLL_CON0, 6, MSDCPLL_CON1, 0, 1664000000), + PLL(CLK_APMIXED_TVDPLL, "tvdpll", TVDPLL_CON0, TVDPLL_PWR_CON0, 0x80000001, + 0, 21, TVDPLL_CON0, 6, TVDPLL_CON1, 0, 2376000000), + PLL(CLK_APMIXED_LVDSPLL, "lvdspll", LVDSPLL_CON0, LVDSPLL_PWR_CON0, 0x80000001, + 0, 21, LVDSPLL_CON0, 6, LVDSPLL_CON1, 0, 1300000000), + PLL(CLK_APMIXED_UNIVPLL, "univpll", UNIVPLL_CON0, VOID_REG, 0xf3000001, + HAVE_RST_BAR, 7, UNIVPLL_CON0, 6, UNIVPLL_CON0, 8, 1248000000), + PLL(CLK_APMIXED_MMPLL, "mmpll", MMPLL_CON0, VOID_REG, 0xf0000001, + HAVE_RST_BAR, 7, MMPLL_CON0, 6, MMPLL_CON0, 8, 1430000000), + PLL(CLK_APMIXED_ISPPLL, "isppll", ISPPLL_CON0, VOID_REG, 0x80000001, + 0, 7, ISPPLL_CON0, 7, ISPPLL_CON0, 8, 1664000000), +}; + +/* init logic from MT2712 */ + +static int clk_mt6589_apmixed_probe(struct platform_device *pdev) +{ + struct clk_hw_onecell_data *clk_data; + int r; + struct device_node *node = pdev->dev.of_node; + + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); + if (!clk_data) + return -ENOMEM; + + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; + + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + if (r) { + dev_err(&pdev->dev, "Cannot register clock provider: %d\n", r); + goto unregister_plls; + } + + return 0; + +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; +} + +static void clk_mt6589_apmixed_remove(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); + + of_clk_del_provider(node); + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); + mtk_free_clk_data(clk_data); +} + +static const struct of_device_id of_match_clk_mt6589_apmixed[] = { + { .compatible = "mediatek,mt6589-apmixedsys" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_apmixed); + +static struct platform_driver clk_mt6589_apmixed_drv = { + .probe = clk_mt6589_apmixed_probe, + .remove = clk_mt6589_apmixed_remove, + .driver = { + .name = "clk-mt6589-apmixed", + .of_match_table = of_match_clk_mt6589_apmixed, + }, +}; +module_platform_driver(clk_mt6589_apmixed_drv) + +MODULE_DESCRIPTION("MediaTek MT6589 apmixedsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-aud.c b/drivers/clk/mediatek/clk-mt6589-aud.c new file mode 100644 index 00000000000000..3d322475f1961d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-aud.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define AUDIO_TOP_CON0 0x0000 + +static const struct mtk_gate_regs aud_cg_regs = { + .sta_ofs = AUDIO_TOP_CON0, +}; + +#define GATE_AUDIO(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &aud_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate aud_clks[] = { + GATE_AUDIO(CLK_AUDIO_AFE, "audio_afe", "infra_audio", 2), + GATE_AUDIO(CLK_AUDIO_I2S, "audio_i2s", "infra_audio", 6), +}; + +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_aud[] = { + { + .compatible = "mediatek,mt6589-audsys", + .data = &aud_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_aud); + +static struct platform_driver clk_mt6589_aud_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-aud", + .of_match_table = of_match_clk_mt6589_aud, + }, +}; +module_platform_driver(clk_mt6589_aud_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 audio clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-disp.c b/drivers/clk/mediatek/clk-mt6589-disp.c new file mode 100644 index 00000000000000..cc01fb141194c1 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-disp.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define DISP_CG_CON0 0x0100 +#define DISP_CG_SET0 0x0104 +#define DISP_CG_CLR0 0x0108 + +#define DISP_CG_CON1 0x0110 +#define DISP_CG_SET1 0x0114 +#define DISP_CG_CLR1 0x0118 + +static const struct mtk_gate_regs disp0_cg_regs = { + .set_ofs = DISP_CG_SET0, + .clr_ofs = DISP_CG_CLR0, + .sta_ofs = DISP_CG_CON0, +}; + +static const struct mtk_gate_regs disp1_cg_regs = { + .set_ofs = DISP_CG_SET1, + .clr_ofs = DISP_CG_CLR1, + .sta_ofs = DISP_CG_CON1, +}; + +#define GATE_DISP0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_DISP1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate disp_clks[] = { + GATE_DISP0(CLK_DISP0_LARB2_SMI, "disp0_larb2_smi", "smi_sel", 0), /* mt8135 */ + GATE_DISP0(CLK_DISP0_ROT_ENGINE, "disp0_rot_engine", "disp_sel", 1), + GATE_DISP0(CLK_DISP0_ROT_SMI, "disp0_rot_smi", "smi_sel", 2), /* mt8135 */ + GATE_DISP0(CLK_DISP0_SCL, "disp0_scl", "disp_sel", 3), + GATE_DISP0(CLK_DISP0_OVL_ENGINE, "disp0_ovl_engine", "disp_sel", 4), + GATE_DISP0(CLK_DISP0_OVL_SMI, "disp0_ovl_smi", "smi_sel", 5), /* mt8135 */ + GATE_DISP0(CLK_DISP0_COLOR, "disp0_color", "disp_sel", 6), + GATE_DISP0(CLK_DISP0_2DSHP, "disp0_2dshp", "disp_sel", 7), + GATE_DISP0(CLK_DISP0_BLS, "disp0_bls", "disp_sel", 8), + GATE_DISP0(CLK_DISP0_WDMA0_ENGINE, "disp0_wdma0_engine", "disp_sel", 9), + GATE_DISP0(CLK_DISP0_WDMA0_SMI, "disp0_wdma0_smi", "smi_sel", 10), /* mt8135 */ + GATE_DISP0(CLK_DISP0_WDMA1_ENGINE, "disp0_wdma1_engine", "disp_sel", 11), + GATE_DISP0(CLK_DISP0_WDMA1_SMI, "disp0_wdma1_smi", "smi_sel", 12), /* mt8135 */ + GATE_DISP0(CLK_DISP0_RDMA0_ENGINE, "disp0_rdma0_engine", "disp_sel", 13), + GATE_DISP0(CLK_DISP0_RDMA0_SMI, "disp0_rdma0_smi", "clk_null", 14), /* mt8135 */ + GATE_DISP0(CLK_DISP0_RDMA0_OUTPUT, "disp0_rdma0_output", "clk_null", 15), /* mt8135 */ + GATE_DISP0(CLK_DISP0_RDMA1_ENGINE, "disp0_rdma1_engine", "disp_sel", 16), + GATE_DISP0(CLK_DISP0_RDMA1_SMI, "disp0_rdma1_smi", "clk_null", 17), /* mt8135 */ + GATE_DISP0(CLK_DISP0_RDMA1_OUTPUT, "disp0_rdma1_output", "clk_null", 18), /* mt8135 */ + GATE_DISP0(CLK_DISP0_GAMMA_ENGINE, "disp0_gamma_engine", "disp_sel", 19), + GATE_DISP0(CLK_DISP0_GAMMA_PIXEL, "disp0_gamma_pixel", "clk_null", 20), /* mt8135 */ + GATE_DISP0(CLK_DISP0_CMDQ_ENGINE, "disp0_cmdq_engine", "disp_sel", 21), + GATE_DISP0(CLK_DISP0_CMDQ_SMI, "disp0_cmdq_smi", "smi_sel", 22), /* mt8135 */ + GATE_DISP0(CLK_DISP0_G2D_ENGINE, "disp0_g2d_engine", "disp_sel", 23), + GATE_DISP0(CLK_DISP0_G2D_SMI, "disp0_g2d_smi", "smi_sel", 24), /* mt8135 */ + + GATE_DISP1(CLK_DISP1_DBI_ENGINE, "disp1_dbi_engine", "disp_sel", 0), + GATE_DISP1(CLK_DISP1_DBI_SMI, "disp1_dbi_smi", "smi_sel", 1), /* maybe */ + GATE_DISP1(CLK_DISP1_DBI_OUTPUT, "disp1_dbi_output", "disp_sel", 2), + GATE_DISP1(CLK_DISP1_DSI_ENGINE, "disp1_dsi_engine", "disp_sel", 3), + GATE_DISP1(CLK_DISP1_DSI_DIGITAL, "disp1_dsi_digital", "disp_sel", 4), + GATE_DISP1(CLK_DISP1_DSI_DIGITAL_LANE, "disp1_dsi_digital_lane", "disp_sel", 5), + GATE_DISP1(CLK_DISP1_DPI0, "disp1_dpi0", "disp_sel", 6), + GATE_DISP1(CLK_DISP1_DPI1, "disp1_dpi1", "disp_sel", 7), + GATE_DISP1(CLK_DISP1_LCD, "disp1_lcd", "disp_sel", 8), + GATE_DISP1(CLK_DISP1_SLCD, "disp1_slcd", "disp_sel", 9), +}; + +static const struct mtk_clk_desc disp_desc = { + .clks = disp_clks, + .num_clks = ARRAY_SIZE(disp_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_disp[] = { + { + .compatible = "mediatek,mt6589-dispsys", + .data = &disp_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_disp); + +static struct platform_driver clk_mt6589_disp_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-disp", + .of_match_table = of_match_clk_mt6589_disp, + }, +}; +module_platform_driver(clk_mt6589_disp_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 display clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-img.c b/drivers/clk/mediatek/clk-mt6589-img.c new file mode 100644 index 00000000000000..77e21fd1dbda97 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-img.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define IMG_CG_CON 0x0000 +#define IMG_CG_SET 0x0004 +#define IMG_CG_CLR 0x0008 + +static const struct mtk_gate_regs img_cg_regs = { + .set_ofs = IMG_CG_SET, + .clr_ofs = IMG_CG_CLR, + .sta_ofs = IMG_CG_CON, +}; + +#define GATE_IMG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate img_clks[] = { + GATE_IMG(CLK_IMAGE_LARB3_SMI, "image_larb3_smi", "smi_sel", 0), /* maybe */ + GATE_IMG(CLK_IMAGE_LARB4_SMI, "image_larb4_smi", "smi_sel", 2), /* maybe */ + GATE_IMG(CLK_IMAGE_COMMN_SMI, "image_commn_smi", "smi_sel", 4), /* maybe */ + GATE_IMG(CLK_IMAGE_CAM_SMI, "image_cam_smi", "smi_sel", 5), /* maybe */ + GATE_IMG(CLK_IMAGE_CAM_CAM, "image_cam_cam", "cam_sel", 6), + GATE_IMG(CLK_IMAGE_SEN_TG, "image_sen_tg", "camtg_sel", 7), + GATE_IMG(CLK_IMAGE_SEN_CAM, "image_sen_cam", "cam_sel", 8), + GATE_IMG(CLK_IMAGE_JPGD_SMI, "image_jpgd_smi", "smi_sel", 9), /* maybe, mt8135 */ + GATE_IMG(CLK_IMAGE_JPGD_JPG, "image_jpgd_jpg", "jpg_sel", 10), + GATE_IMG(CLK_IMAGE_JPGE_SMI, "image_jpge_smi", "smi_sel", 11), /* maybe, mt8135 */ + GATE_IMG(CLK_IMAGE_JPGE_JPG, "image_jpge_jpg", "jpg_sel", 12), + GATE_IMG(CLK_IMAGE_FPC, "image_fpc", "smi_sel", 13), /* maybe, mt8135 */ +}; + +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_img[] = { + { + .compatible = "mediatek,mt6589-imgsys", + .data = &img_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_img); + +static struct platform_driver clk_mt6589_img_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-img", + .of_match_table = of_match_clk_mt6589_img, + }, +}; +module_platform_driver(clk_mt6589_img_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 imgsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-infracfg.c b/drivers/clk/mediatek/clk-mt6589-infracfg.c new file mode 100644 index 00000000000000..dea3488a4116ac --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-infracfg.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define TOP_CKMUXSEL 0x10001000 + +static const char * const infra_mux1_parents[] = { + "clk26m", + "armpll", + "mainpll", + "mmpll", /* MMPLL/2 */ +}; + +static const struct mtk_composite cpu_muxes[] = { + MUX(CLK_INFRA_MUX1, "infra_mux1_sel", infra_mux1_parents, TOP_CKMUXSEL, 2, 2), +}; + +#define INFRA_PDN_SET 0x0040 +#define INFRA_PDN_CLR 0x0044 +#define INFRA_PDN_STA 0x0048 + +static const struct mtk_gate_regs infra_cg_regs = { + .set_ofs = INFRA_PDN_SET, + .clr_ofs = INFRA_PDN_CLR, + .sta_ofs = INFRA_PDN_STA, +}; + +#define GATE_INFRA(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate infra_clks[] = { + GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), /* maybe */ + GATE_INFRA(CLK_INFRA_SMI, "infra_smi", "smi_sel", 1), /* maybe */ + GATE_INFRA(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 2), /* maybe, is it infra_mfg_bus? */ + GATE_INFRA(CLK_INFRA_AUDIO, "infra_audio", "audintbus_sel", 5), + GATE_INFRA(CLK_INFRA_DEVAPC, "infra_devapc", "axi_sel", 6), /* is it infra cec (setclr_inv)? maybe correct parent */ + GATE_INFRA(CLK_INFRA_MFGAXI, "infra_mfgaxi", "axi_sel", 7), /* maybe */ + GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), /* or axi_sel, maybe */ + GATE_INFRA(CLK_INFRA_MD1MCUAXI, "infra_md1mcuaxi", "axi_sel", 9), /* maybe */ + GATE_INFRA(CLK_INFRA_MD1HWMIXAXI, "infra_md1hwmixaxi", "axi_sel", 10), /* maybe */ + GATE_INFRA(CLK_INFRA_MD1AHB, "infra_md1ahb", "axi_sel", 11), /* maybe */ + GATE_INFRA(CLK_INFRA_MD2MCUAXI, "infra_md2mcuaxi", "axi_sel", 12), /* maybe */ + GATE_INFRA(CLK_INFRA_MD2HWMIXAXI, "infra_md2hwmixaxi", "axi_sel", 13), /* maybe */ + GATE_INFRA(CLK_INFRA_MD2AHB, "infra_md2ahb", "axi_sel", 14), /* maybe */ + GATE_INFRA(CLK_INFRA_CPUM, "infra_cpum", "cpum_tck_in", 15), /* from MT8135 */ + GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), /* maybe */ + GATE_INFRA(CLK_INFRA_CCIF0, "infra_ccif0", "axi_sel", 20), /* maybe */ + GATE_INFRA(CLK_INFRA_CCIF1, "infra_ccif1", "axi_sel", 21), /* maybe */ + GATE_INFRA(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), /* maybe */ + GATE_INFRA(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), /* maybe */ +}; + +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; + +static const struct mtk_clk_rst_desc infra_clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = infrasys_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), +}; + +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .cpumuxes = cpu_muxes, + .num_cpumuxes = ARRAY_SIZE(cpu_muxes), + .rst_desc = &infra_clk_rst_desc, +}; + +static const struct of_device_id of_match_clk_mt6589_infracfg[] = { + { .compatible = "mediatek,mt6589-infracfg", .data = &infra_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_infracfg); + +static struct platform_driver clk_mt6589_infracfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-infracfg", + .of_match_table = of_match_clk_mt6589_infracfg, + }, +}; +module_platform_driver(clk_mt6589_infracfg_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 infracfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-mfg.c b/drivers/clk/mediatek/clk-mt6589-mfg.c new file mode 100644 index 00000000000000..27ce3deac0637d --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-mfg.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define MFG_CG_CON 0x0000 +#define MFG_CG_SET 0x0004 +#define MFG_CG_CLR 0x0008 + +static const struct mtk_gate_regs mfg_cg_regs = { + .set_ofs = MFG_CG_SET, + .clr_ofs = MFG_CG_CLR, + .sta_ofs = MFG_CG_CON, +}; + +#define GATE_MFG(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mfg_clks[] = { + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "infra_mfgaxi", 0), /* or axi_sel, maybe */ + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "smi_mfg_as_sel", 1), + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2), + GATE_MFG(CLK_MFG_HYD, "mfg_hyd", "hyd_sel", 3), +}; + +static const struct mtk_clk_desc mfg_desc = { + .clks = mfg_clks, + .num_clks = ARRAY_SIZE(mfg_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_mfg[] = { + { + .compatible = "mediatek,mt6589-mfgsys", + .data = &mfg_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_mfg); + +static struct platform_driver clk_mt6589_mfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-mfg", + .of_match_table = of_match_clk_mt6589_mfg, + }, +}; +module_platform_driver(clk_mt6589_mfg_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 mfgsys clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-pericfg.c b/drivers/clk/mediatek/clk-mt6589-pericfg.c new file mode 100644 index 00000000000000..1aaeef1b33c74a --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-pericfg.c @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define PERI_PDN0_SET 0x0008 +#define PERI_PDN0_CLR 0x0010 +#define PERI_PDN0_STA 0x0018 +#define PERI_PDN1_SET 0x000c +#define PERI_PDN1_CLR 0x0014 +#define PERI_PDN1_STA 0x001c + +static const struct mtk_gate_regs peri0_cg_regs = { + .set_ofs = PERI_PDN0_SET, + .clr_ofs = PERI_PDN0_CLR, + .sta_ofs = PERI_PDN0_STA, +}; + +static const struct mtk_gate_regs peri1_cg_regs = { + .set_ofs = PERI_PDN1_SET, + .clr_ofs = PERI_PDN1_CLR, + .sta_ofs = PERI_PDN1_STA, +}; + +#define GATE_PERI0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_PERI1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate peri_clks[] = { + GATE_PERI0(CLK_PERI0_NFI, "peri_nfi", "axi_sel", 0), /* auxadc, maybe */ + GATE_PERI0(CLK_PERI0_THERM, "peri_therm", "axi_sel", 1), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM1, "peri_pwm1", "axi_sel", 2), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM2, "peri_pwm2", "axi_sel", 3), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM3, "peri_pwm3", "axi_sel", 4), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM4, "peri_pwm4", "axi_sel", 5), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM5, "pwri_pwm5", "axi_sel", 6), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM6, "pwri_pwm6", "axi_sel", 7), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM7, "peri_pwm7", "axi_sel", 8), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM, "peri_pwm", "axi_sel", 9), /* maybe */ + GATE_PERI0(CLK_PERI0_USB0, "peri_usb0", "usb20_sel", 10), + GATE_PERI0(CLK_PERI0_USB1, "peri_usb1", "usb20_sel", 11), + GATE_PERI0(CLK_PERI0_APDMA, "peri_apdma", "axi_sel", 12), /* maybe */ + GATE_PERI0(CLK_PERI0_MSDC0, "peri_msdc0", "msdc0_sel", 13), + GATE_PERI0(CLK_PERI0_MSDC1, "peri_msdc1", "msdc1_sel", 14), + GATE_PERI0(CLK_PERI0_MSDC2, "peri_msdc2", "msdc2_sel", 15), + GATE_PERI0(CLK_PERI0_MSDC3, "peri_msdc3", "msdc3_sel", 16), + GATE_PERI0(CLK_PERI0_MSDC4, "peri_msdc4", "msdc4_sel", 17), + GATE_PERI0(CLK_PERI0_APHIF, "peri_aphif", "axi_sel", 18), /* maybe */ + GATE_PERI0(CLK_PERI0_MDHIF, "peri_mdhif", "axi_sel", 19), /* maybe */ + GATE_PERI0(CLK_PERI0_NLI, "peri_nli", "axi_sel", 20), /* maybe */ + GATE_PERI0(CLK_PERI0_IRDA, "peri_irda", "irda_sel", 21), + GATE_PERI0(CLK_PERI0_UART0, "peri_uart0", "peri_uart0_sel", 22), + GATE_PERI0(CLK_PERI0_UART1, "peri_uart1", "peri_uart1_sel", 23), + GATE_PERI0(CLK_PERI0_UART2, "peri_uart2", "peri_uart2_sel", 24), + GATE_PERI0(CLK_PERI0_UART3, "peri_uart3", "peri_uart3_sel", 25), + GATE_PERI0(CLK_PERI0_I2C0, "peri_i2c0", "axi_sel", 26), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C1, "peri_i2c1", "axi_sel", 27), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C2, "peri_i2c2", "axi_sel", 28), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C3, "peri_i2c3", "axi_sel", 29), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C4, "peri_i2c4", "axi_sel", 30), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C5, "peri_i2c5", "axi_sel", 31), /* maybe */ + + GATE_PERI1(CLK_PERI1_I2C6, "peri_i2c6", "axi_sel", 0), /* maybe */ + GATE_PERI1(CLK_PERI1_PWRAP, "peri_pwrap", "axi_sel", 1), /* maybe */ + GATE_PERI1(CLK_PERI1_AUXADC, "peri_auxadc", "axi_sel", 2), /* maybe */ + GATE_PERI1(CLK_PERI1_SPI1, "peri_spi1", "spi_sel", 3), + GATE_PERI1(CLK_PERI1_FHCTL, "peri_fhctl", "clk26m", 4), /* maybe */ +}; + +static const char * const uart_mux_parents[] = { + "clk26m", /* 26 MHz */ + "uart_sel", /* or univpll2_d8, 52 MHz */ +}; + +static const struct mtk_composite peri_muxes[] = { + MUX(CLK_PERI_MUX_UART0, "peri_uart0_sel", uart_mux_parents, + 0x040c, 0, 1), + MUX(CLK_PERI_MUX_UART1, "peri_uart1_sel", uart_mux_parents, + 0x040c, 1, 1), + MUX(CLK_PERI_MUX_UART2, "peri_uart2_sel", uart_mux_parents, + 0x040c, 2, 1), + MUX(CLK_PERI_MUX_UART3, "peri_uart3_sel", uart_mux_parents, + 0x040c, 3, 1), +}; + +static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; + +static const struct mtk_clk_rst_desc peri_clk_rst_desc = { + .version = MTK_RST_SIMPLE, + .rst_bank_ofs = pericfg_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), + .composite_clks = peri_muxes, + .num_composite_clks = ARRAY_SIZE(peri_muxes), + .rst_desc = &peri_clk_rst_desc, +}; + + +static const struct of_device_id of_match_clk_mt6589_pericfg[] = { + { .compatible = "mediatek,mt6589-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_pericfg); + +static struct platform_driver clk_mt6589_pericfg_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-pericfg", + .of_match_table = of_match_clk_mt6589_pericfg, + }, +}; +module_platform_driver(clk_mt6589_pericfg_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 pericfg clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-topckgen.c b/drivers/clk/mediatek/clk-mt6589-topckgen.c new file mode 100644 index 00000000000000..1e8e5756ae4ccc --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-topckgen.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +/* HACK: reg starts from 0x10000100 to avoid overlap with the watchdog register area */ +#define BASE_SHIFT 0x0100 + +static DEFINE_SPINLOCK(mt6589_clk_lock); + +static const struct mtk_fixed_clk top_fixed_clks[] = { + FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0), +}; + +static const struct mtk_fixed_factor top_divs[] = { + FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1), + FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1), + + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 2), // mainpll_806m + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3), // mainpll_537p3m + FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5), // mainpll_322p4m + FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7), // mainpll_230p3m + + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), + FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "syspll_ck", 2, 7), + FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "syspll_ck", 1, 4), + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), + FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "syspll_ck", 1, 6), + FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "syspll_ck", 1, 8), + FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "syspll_ck", 1, 10), + FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "syspll_ck", 1, 16), + FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "syspll_ck", 1, 24), + + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2), // univpll_624m + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3), // univpll_416m + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5), // univpll_249p6m + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7), // univpll_178p3m + FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll", 1, 10), + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26), // univpll_48m + + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), + FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_d2", 1, 6), + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), + FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_d10", 1, 10), + + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), + FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_d3", 1, 6), + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), // unconfirmed + + FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3), + FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), + FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), + FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6), + FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), + + FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), + FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2), // lvdspll_180m + FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4), + FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8), + + FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1), + + FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1), + + FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2), + FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3), + + FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2), + FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4), + + FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4), + + FACTOR(CLK_TOP_AD_ISP_208M_CK, "ad_isp_208m_ck", "isppll", 1, 8), // ? + + FACTOR(CLK_TOP_AD_MSDC_H208M_CK, "ad_msdc_h208m_ck", "msdcpll", 1, 8), // ? +}; + +static const char * axi_parents[] = { + "clk26m", + "syspll_d3", + "syspll_d4", + "syspll_d6", + "univpll_d5", + "univpll2_d2", + "syspll_d3p5", +}; + +static const char * smi_parents[] = { + "clk26m", + "syspll_d3", + "syspll_d8", + "univpll_d5", + "univpll1_d6", + "mmpll_d4", + "mmpll_d5", + "mmpll_d6", +}; + +static const char * const mfg_parents[] = { + "univpll1_d4", + "mmpll_d6", + "syspll_d2", + "syspll_d3", + "univpll1_d2", + "mmpll_d3", + "mmpll_d4", + "mmpll_d5", +}; + +static const char * const irda_parents[] = { + "clk26m", + "univpll2_d8", + "univpll1_d6", +}; + +static const char * const cam_parents[] = { + "clk26m", + "syspll_d3", + "syspll_d3p5", + "syspll_d4", + "syspll_d6", + "syspll_d8", + "ad_isp_208m_ck", + "univpll_d5", + "univpll2_d2", + "univpll_d7", + "univpll1_d4", +}; + +static const char * const audintbus_parents[] = { + "clk26m", + "syspll_d6", + "univpll_d10", +}; + +static const char * const jpg_parents[] = { + "clk26m", + "syspll_d5", + "syspll_d4", + "univpll2_d2", + "univpll_d7", +}; + +static const char * const disp_parents[] = { + "clk26m", + "syspll_d3p5", + "syspll_d3", + "univpll2_d2", + "univpll_d5", +}; + +static const char * const msdc1_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d5", + "univpll1_d4", + "unicpll2_d4", + "ad_msdc_h208m_ck", +}; + +static const char * const msdc2_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d5", + "univpll1_d4", + "unicpll2_d4", + "ad_msdc_h208m_ck", +}; + +static const char * const msdc3_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d5", + "univpll1_d4", + "unicpll2_d4", + "ad_msdc_h208m_ck", +}; + +static const char * const msdc4_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d5", + "univpll1_d4", + "unicpll2_d4", + "ad_msdc_h208m_ck", +}; + +static const char * const usb20_parents[] = { + "clk26m", + "univpll2_d6", + "univpll1_d10", +}; + +static const char * const hyd_parents[] = { + "univpll1_d4", + "mmpll_d6", + "syspll_d2", + "syspll_d3", + "univpll1_d2", + "mmpll_d3", + "mmpll_d4", + "mmpll_d5", +}; + +static const char * const venc_parents[] = { + "clk26m", + "syspll_d3", + "syspll_d8", + "univpll_d5", + "univpll1_d6", + "mmpll_d4", + "mmpll_d5", + "mmpll_d6", +}; + +static const char * const spi_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d8", + "syspll_d10", + "univpll1_d6", + "univpll1_d8", +}; + +static const char * const uart_parents[] = { + "clk26m", + "univpll2_d8", +}; + +static const char * const mem_parents[] = { + "clk26m", + "clkph_mck", + "clk_null", + "clk_null", +}; + +static const char * const camtg_parents[] = { + "clk26m", + "univpll_d26", + "univpll1_d6", + "syspll_d16", + "syspll_d8", + "ad_isp_208m_ck", +}; + +static const char * const fd_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d8", + "univpll_d10", + "univpll2_d4", +}; + +static const char * const audio_parents[] = { + "clk26m", + "syspll_d24", +}; + +static const char * const fix_parents[] = { + "rtc_clk", + "clk26m", /* f_f26m_ck" */ + "univpll_d5", + "univpll_d7", + "univpll1_d2", + "univpll1_d4", + "univpll1_d6", + "univpll1_d8", +}; + +static const char * const vdec_parents[] = { + "clk26m", + "syspll_d3p5", + "syspll_d4", + "syspll_d5", + "syspll_d6", + "syspll_d8", + "univpll2_d2", + "univpll_d7", + "univpll_d10", + "univpll2_d4", +}; + +static const char * const dpilvds_parents[] = { + "clk26m", + "lvdspll_ck", + "lvdspll_d2", + "lvdspll_d4", + "lvdspll_d8", +}; + +static const char * const pmicspi_parents[] = { + "clk26m", + "univpll2_d6", + "syspll_d8", + "syspll_d10", + "univpll1_d10", + "mempll_mck_d4", + "univpll_d26", + "syspll_d24", +}; + +static const char * const msdc0_parents[] = { + "clk26m", + "syspll_d6", + "syspll_d5", + "univpll1_d4", + "unicpll2_d4", + "ad_msdc_h208m_ck", +}; + +static const char * const smi_mfg_as_parents[] = { + "clk26m", + "smi_sel", + "mfg_sel", + "hyd_sel", +}; + +#define CLK_CFG_0 (0x0140 - BASE_SHIFT) +#define CLK_CFG_1 (0x0144 - BASE_SHIFT) +#define CLK_CFG_2 (0x0148 - BASE_SHIFT) +#define CLK_CFG_3 (0x014c - BASE_SHIFT) +#define CLK_CFG_4 (0x0150 - BASE_SHIFT) +#define CLK_CFG_5 (0x0154 - BASE_SHIFT) +#define CLK_CFG_6 (0x0158 - BASE_SHIFT) +#define CLK_CFG_7 (0x015c - BASE_SHIFT) +#define CLK_CFG_8 (0x0164 - BASE_SHIFT) + +static struct mtk_composite top_muxes[] = { + /* CLK_CFG_0 */ + MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents, + CLK_CFG_0, 0, 3), + MUX_GATE(CLK_TOP_MUX_SMI, "smi_sel", smi_parents, + CLK_CFG_0, 8, 3, 15), + MUX_GATE(CLK_TOP_MUX_MFG, "mfg_sel", mfg_parents, + CLK_CFG_0, 16, 3, 23), + MUX_GATE(CLK_TOP_MUX_IRDA, "irda_sel", irda_parents, + CLK_CFG_0, 24, 2, 31), + + /* CLK_CFG_1 */ + MUX_GATE(CLK_TOP_MUX_CAM, "cam_sel", cam_parents, + CLK_CFG_1, 0, 4, 7), + MUX_GATE(CLK_TOP_MUX_AUDINTBUS, "audintbus_sel", audintbus_parents, + CLK_CFG_1, 8, 2, 15), + MUX_GATE(CLK_TOP_MUX_JPG, "jpg_sel", jpg_parents, + CLK_CFG_1, 16, 3, 23), + MUX_GATE(CLK_TOP_MUX_DISP, "disp_sel", disp_parents, + CLK_CFG_1, 24, 3, 31), + + /* CLK_CFG_2 */ + MUX_GATE(CLK_TOP_MUX_MSDC1, "msdc1_sel", msdc1_parents, + CLK_CFG_2, 0, 3, 7), + MUX_GATE(CLK_TOP_MUX_MSDC2, "msdc2_sel", msdc2_parents, + CLK_CFG_2, 8, 3, 15), + MUX_GATE(CLK_TOP_MUX_MSDC3, "msdc3_sel", msdc3_parents, + CLK_CFG_2, 16, 3, 23), + MUX_GATE(CLK_TOP_MUX_MSDC4, "msdc4_sel", msdc4_parents, + CLK_CFG_2, 24, 3, 31), + + /* CLK_CFG_3 */ + MUX_GATE(CLK_TOP_MUX_USB20, "usb20_sel", usb20_parents, + CLK_CFG_3, 0, 2, 7), + + /* CLK_CFG_4 */ + MUX_GATE(CLK_TOP_MUX_HYD, "hyd_sel", hyd_parents, + CLK_CFG_4, 0, 3, 7), + MUX_GATE(CLK_TOP_MUX_VENC, "venc_sel", venc_parents, + CLK_CFG_4, 8, 3, 15), + MUX_GATE(CLK_TOP_MUX_SPI, "spi_sel", spi_parents, + CLK_CFG_4, 16, 3, 23), + MUX_GATE(CLK_TOP_MUX_UART, "uart_sel", uart_parents, + CLK_CFG_4, 24, 2, 31), + + /* CLK_CFG_6 */ + MUX_GATE(CLK_TOP_MUX_MEM, "mem_sel", mem_parents, + CLK_CFG_6, 0, 2, 7), + MUX_GATE(CLK_TOP_MUX_CAMTG, "camtg_sel", camtg_parents, + CLK_CFG_6, 8, 3, 15), + MUX_GATE(CLK_TOP_MUX_FD, "fd_sel", fd_parents, + CLK_CFG_6, 16, 3, 23), + MUX_GATE(CLK_TOP_MUX_AUDIO, "audio_sel", audio_parents, + CLK_CFG_6, 24, 2, 31), + + /* CLK_CFG_7 */ + MUX_GATE(CLK_TOP_MUX_FIX, "fix_sel", fix_parents, + CLK_CFG_7, 0, 3, 7), + MUX_GATE(CLK_TOP_MUX_VDEC, "vdec_sel", vdec_parents, + CLK_CFG_7, 8, 4, 15), + MUX_GATE(CLK_TOP_MUX_DPILVDS, "dpilvds_sel", dpilvds_parents, + CLK_CFG_7, 24, 3, 31), + + /* CLK_CFG_8 */ + MUX_GATE(CLK_TOP_MUX_PMICSPI, "pmicspi_sel", pmicspi_parents, + CLK_CFG_8, 0, 3, 7), + MUX_GATE(CLK_TOP_MUX_MSDC0, "msdc0_sel", msdc0_parents, + CLK_CFG_8, 8, 3, 15), + MUX_GATE(CLK_TOP_MUX_SMI_MFG_AS, "smi_mfg_as_sel", smi_mfg_as_parents, + CLK_CFG_8, 16, 2, 23), +}; + +#define TOPCK_PDN_SET (0x0170 - BASE_SHIFT) +#define TOPCK_PDN_CLR (0x0174 - BASE_SHIFT) +#define TOPCK_PDN_STA (0x0178 - BASE_SHIFT) + +static const struct mtk_gate_regs topck_cg_regs = { + .set_ofs = TOPCK_PDN_SET, + .clr_ofs = TOPCK_PDN_CLR, + .sta_ofs = TOPCK_PDN_STA, +}; + +#define GATE_TOPCK(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &topck_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate top_clks[] = { + GATE_TOPCK(CLK_TOPCK_PMICSPI, "topck_pmicspi", "pmicspi_sel", 0), +}; + +static const struct mtk_clk_desc topck_desc = { + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .clk_lock = &mt6589_clk_lock, +}; + +static const struct of_device_id of_match_clk_mt6589_topckgen[] = { + { .compatible = "mediatek,mt6589-topckgen", .data = &topck_desc }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_topckgen); + +static struct platform_driver clk_mt6589_topckgen_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-topckgen", + .of_match_table = of_match_clk_mt6589_topckgen, + }, +}; +module_platform_driver(clk_mt6589_topckgen_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 topckgen driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-vdec.c b/drivers/clk/mediatek/clk-mt6589-vdec.c new file mode 100644 index 00000000000000..7b7c9c999b0a83 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-vdec.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define VDEC_CKEN_SET 0x0000 +#define VDEC_CKEN_CLR 0x0004 +#define LARB_CKEN_SET 0x0008 +#define LARB_CKEN_CLR 0x000c + +/* + * downstream + { + .name = __stringify(CG_VDEC0), + .set_addr = VDEC_CKEN_CLR, + .clr_addr = VDEC_CKEN_SET, + .mask = 0x00000001, + .ops = &vdec_cg_grp_ops, + .sys = &syss[SYS_VDE], + }, { + .name = __stringify(CG_VDEC1), + .set_addr = LARB_CKEN_CLR, + .clr_addr = LARB_CKEN_SET, + .mask = 0x00000001, + .ops = &vdec_cg_grp_ops, + .sys = &syss[SYS_VDE], + } + */ + +static const struct mtk_gate_regs vdec_cg_regs = { + .set_ofs = VDEC_CKEN_SET, + .clr_ofs = VDEC_CKEN_CLR, + .sta_ofs = VDEC_CKEN_SET, /* many SoCs use set reg as sta reg */ +}; + +static const struct mtk_gate_regs larb_cg_regs = { + .set_ofs = LARB_CKEN_SET, + .clr_ofs = LARB_CKEN_CLR, + .sta_ofs = LARB_CKEN_SET, +}; + +#define GATE_VDEC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &vdec_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +#define GATE_LARB(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &larb_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate vdec_clks[] = { + GATE_VDEC(CLK_VDEC0_VDE, "vdec0_vde", "vdec_sel", 0), + GATE_LARB(CLK_VDEC1_SMI, "vdec0_smi", "vdec_sel", 0), +}; + +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_vdec[] = { + { + .compatible = "mediatek,mt6589-vdecsys", + .data = &vdec_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_vdec); + +static struct platform_driver clk_mt6589_vdec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-vdec", + .of_match_table = of_match_clk_mt6589_vdec, + }, +}; +module_platform_driver(clk_mt6589_vdec_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 video decoder clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-venc.c b/drivers/clk/mediatek/clk-mt6589-venc.c new file mode 100644 index 00000000000000..57192e593377e8 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt6589-venc.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +#define VENCSYS_CG_CON 0x0000 +#define VENCSYS_CG_SET 0x0004 +#define VENCSYS_CG_CLR 0x0008 + +/* + * NOTE: downstream: + * .set_addr = VENCSYS_CG_CLR, + * .clr_addr = VENCSYS_CG_SET, + * .sta_addr = VENCSYS_CG_CON, + */ +static const struct mtk_gate_regs venc_cg_regs = { + .set_ofs = VENCSYS_CG_SET, + .clr_ofs = VENCSYS_CG_CLR, + .sta_ofs = VENCSYS_CG_CON, +}; + +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + +static const struct mtk_gate venc_clks[] = { + GATE_VENC(CLK_VENC_VEN, "venc_ven", "venc_sel", 0), +}; + +static const struct mtk_clk_desc venc_desc = { + .clks = venc_clks, + .num_clks = ARRAY_SIZE(venc_clks), +}; + +static const struct of_device_id of_match_clk_mt6589_venc[] = { + { + .compatible = "mediatek,mt6589-vencsys", + .data = &venc_desc, + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt6589_venc); + +static struct platform_driver clk_mt6589_venc_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6589-venc", + .of_match_table = of_match_clk_mt6589_venc, + }, +}; +module_platform_driver(clk_mt6589_venc_drv); + +MODULE_DESCRIPTION("MediaTek MT6589 video encoder clocks driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index ba1d1c495bc2bf..7f14ddf20a0fa7 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -19,6 +19,7 @@ #include "clk-mtk.h" #include "clk-gate.h" #include "clk-mux.h" +#include "clk-cpumux.h" const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; EXPORT_SYMBOL_GPL(cg_regs_dummy); @@ -511,6 +512,7 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, num_clks = mcd->num_clks + mcd->num_composite_clks; num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; num_clks += mcd->num_mux_clks + mcd->num_divider_clks; + num_clks += mcd->num_cpumuxes; clk_data = mtk_alloc_clk_data(num_clks); if (!clk_data) { @@ -540,6 +542,13 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, goto unregister_factors; } + if (mcd->cpumuxes) { + r = mtk_clk_register_cpumuxes(&pdev->dev, node, mcd->cpumuxes, + mcd->num_cpumuxes, clk_data); + if (r) + goto unregister_muxes; + } + if (mcd->composite_clks) { /* We don't check composite_lock because it's optional */ r = mtk_clk_register_composites(&pdev->dev, @@ -547,9 +556,10 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, mcd->num_composite_clks, base, mcd->clk_lock, clk_data); if (r) - goto unregister_muxes; + goto unregister_cpumuxes; } + if (mcd->divider_clks) { r = mtk_clk_register_dividers(&pdev->dev, mcd->divider_clks, @@ -603,6 +613,9 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev, if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); +unregister_cpumuxes: + if (mcd->cpumuxes) + mtk_clk_unregister_cpumuxes(mcd->cpumuxes, mcd->num_cpumuxes, clk_data); unregister_muxes: if (mcd->mux_clks) mtk_clk_unregister_muxes(mcd->mux_clks, @@ -641,6 +654,9 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev, if (mcd->composite_clks) mtk_clk_unregister_composites(mcd->composite_clks, mcd->num_composite_clks, clk_data); + if (mcd->cpumuxes) + mtk_clk_unregister_cpumuxes(mcd->cpumuxes, + mcd->num_cpumuxes, clk_data); if (mcd->mux_clks) mtk_clk_unregister_muxes(mcd->mux_clks, mcd->num_mux_clks, clk_data); diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c17fe1c2d732da..6f0e9e8660c22e 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -234,6 +234,8 @@ struct mtk_clk_desc { const struct mtk_clk_rst_desc *rst_desc; spinlock_t *clk_lock; bool shared_io; + const struct mtk_composite *cpumuxes; + size_t num_cpumuxes; int (*clk_notifier_func)(struct device *dev, struct clk *clk); unsigned int mfg_clk_idx; diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index ce453e1718e535..a987deffa7857f 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -217,13 +217,15 @@ int mtk_pll_prepare(struct clk_hw *hw) struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; - r = readl(pll->pwr_addr) | CON0_PWR_ON; - writel(r, pll->pwr_addr); - udelay(1); - - r = readl(pll->pwr_addr) & ~CON0_ISO_EN; - writel(r, pll->pwr_addr); - udelay(1); + if (pll->pwr_addr) { + r = readl(pll->pwr_addr) | CON0_PWR_ON; + writel(r, pll->pwr_addr); + udelay(1); + + r = readl(pll->pwr_addr) & ~CON0_ISO_EN; + writel(r, pll->pwr_addr); + udelay(1); + } r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit); writel(r, pll->en_addr); @@ -267,11 +269,13 @@ void mtk_pll_unprepare(struct clk_hw *hw) r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit); writel(r, pll->en_addr); - r = readl(pll->pwr_addr) | CON0_ISO_EN; - writel(r, pll->pwr_addr); - - r = readl(pll->pwr_addr) & ~CON0_PWR_ON; - writel(r, pll->pwr_addr); + if (pll->pwr_addr) { + r = readl(pll->pwr_addr) | CON0_ISO_EN; + writel(r, pll->pwr_addr); + + r = readl(pll->pwr_addr) & ~CON0_PWR_ON; + writel(r, pll->pwr_addr); + } } const struct clk_ops mtk_pll_ops = { @@ -293,7 +297,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll, const char *parent_name = "clk26m"; pll->base_addr = base + data->reg; - pll->pwr_addr = base + data->pwr_reg; + if (data->pwr_reg) + pll->pwr_addr = base + data->pwr_reg; pll->pd_addr = base + data->pd_reg; pll->pcw_addr = base + data->pcw_reg; if (data->pcw_chg_reg) diff --git a/include/dt-bindings/clock/mt6589-clk.h b/include/dt-bindings/clock/mt6589-clk.h new file mode 100644 index 00000000000000..67e6b75118522c --- /dev/null +++ b/include/dt-bindings/clock/mt6589-clk.h @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ + +/* clock IDs from mt_clkmgr.h */ + + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL 0 +#define CLK_APMIXED_MAINPLL 1 +#define CLK_APMIXED_MSDCPLL 2 +#define CLK_APMIXED_TVDPLL 3 +#define CLK_APMIXED_LVDSPLL 4 +#define CLK_APMIXED_UNIVPLL 5 +#define CLK_APMIXED_MMPLL 6 +#define CLK_APMIXED_ISPPLL 7 +#define CLK_APMIXED_NR_CLK 8 + + +/* TOPCKGEN */ +#define CLK_TOP_CLK_NULL 1 + +#define CLK_TOP_CLKPH_MCK 11 +#define CLK_TOP_CPUM_TCK_IN 12 + +#define CLK_TOP_SYSPLL 21 +#define CLK_TOP_MAINPLL_D3 22 +#define CLK_TOP_MAINPLL_D5 23 +#define CLK_TOP_MAINPLL_D7 24 + +/* GPU: 403MHz */ +#define CLK_TOP_SYSPLL_D2 31 +#define CLK_TOP_SYSPLL_D2P5 32 +/* MAINPLL / 3 / 2 = GPU: 268MHz */ +#define CLK_TOP_SYSPLL_D3 33 +#define CLK_TOP_SYSPLL_D3P5 34 +/* MAINPLL / 2 / 4 */ +#define CLK_TOP_SYSPLL_D4 35 +#define CLK_TOP_SYSPLL_D5 36 +/* MAINPLL /2 / 6 */ +#define CLK_TOP_SYSPLL_D6 37 +#define CLK_TOP_SYSPLL_D8 38 +#define CLK_TOP_SYSPLL_D10 39 +#define CLK_TOP_SYSPLL_D12 40 +#define CLK_TOP_SYSPLL_D16 41 +#define CLK_TOP_SYSPLL_D24 42 + +/* may be univpll1 parent */ +#define CLK_TOP_UNIVPLL_D2 51 +/* must be univpll2 parent */ +#define CLK_TOP_UNIVPLL_D3 52 +/* UNIVPLL / 5 */ +#define CLK_TOP_UNIVPLL_D5 53 +#define CLK_TOP_UNIVPLL_D7 54 +#define CLK_TOP_UNIVPLL_D10 55 +#define CLK_TOP_UNIVPLL_D26 56 + +/* GPU: 312MHz */ +#define CLK_TOP_UNIVPLL1_D2 61 +/* GPU: 156MHz */ +#define CLK_TOP_UNIVPLL1_D4 62 +#define CLK_TOP_UNIVPLL1_D6 63 +#define CLK_TOP_UNIVPLL1_D8 64 +#define CLK_TOP_UNIVPLL1_D10 65 + +/* UNIVPLL / 3 / 2 */ +#define CLK_TOP_UNIVPLL2_D2 71 +/* unknown */ +#define CLK_TOP_UNIVPLL2_D4 72 +#define CLK_TOP_UNIVPLL2_D6 73 +#define CLK_TOP_UNIVPLL2_D8 74 + +#define CLK_TOP_MMPLL_D2 81 +/* GPU: 476MHz */ +#define CLK_TOP_MMPLL_D3 82 +/* GPU: 357MHz */ +#define CLK_TOP_MMPLL_D4 83 +/* GPU: 286MHz */ +#define CLK_TOP_MMPLL_D5 84 +/* GPU: 238MHz */ +#define CLK_TOP_MMPLL_D6 85 +#define CLK_TOP_MMPLL_D7 86 + +#define CLK_TOP_LVDSPLL 91 +#define CLK_TOP_LVDSPLL_D2 92 +#define CLK_TOP_LVDSPLL_D4 93 +#define CLK_TOP_LVDSPLL_D8 94 + +#define CLK_TOP_LVDSTX_CLKDIG_CT 101 + +#define CLK_TOP_TVHDMI_H 111 + +#define CLK_TOP_HDMITX_CLKDIG_D2 121 +#define CLK_TOP_HDMITX_CLKDIG_D3 122 + +#define CLK_TOP_TVHDMI_D2 131 +#define CLK_TOP_TVHDMI_D4 132 + +#define CLK_TOP_MEMPLL_MCK_D4 141 + +#define CLK_TOP_APLL 151 +#define CLK_TOP_APLL_D4 152 +#define CLK_TOP_APLL_D8 153 +#define CLK_TOP_APLL_D16 154 +#define CLK_TOP_APLL_D24 155 + +#define CLK_TOP_VPLL_DPIX 161 + +#define CLK_TOP_AD_ISP_208M_CK 171 + +#define CLK_TOP_AD_MSDC_H208M_CK 181 + + +/* MUXs */ +/* CLK_CFG_0 */ +#define CLK_TOP_MUX_AXI 201 +#define CLK_TOP_MUX_SMI 202 +#define CLK_TOP_MUX_MFG 203 +#define CLK_TOP_MUX_IRDA 204 + +/* CLK_CFG_1 */ +#define CLK_TOP_MUX_CAM 205 +#define CLK_TOP_MUX_AUDINTBUS 206 +#define CLK_TOP_MUX_JPG 207 +#define CLK_TOP_MUX_DISP 208 + +/* CLK_CFG_2 */ +#define CLK_TOP_MUX_MSDC1 209 +#define CLK_TOP_MUX_MSDC2 210 +#define CLK_TOP_MUX_MSDC3 211 +#define CLK_TOP_MUX_MSDC4 212 + +/* CLK_CFG_3 */ +#define CLK_TOP_MUX_USB20 213 +// 214 +// 215 +// 216 + +/* CLK_CFG_4 */ +#define CLK_TOP_MUX_HYD 217 +#define CLK_TOP_MUX_VENC 218 +#define CLK_TOP_MUX_SPI 219 +#define CLK_TOP_MUX_UART 220 + +/* CLK_CFG_6 */ +#define CLK_TOP_MUX_MEM 221 +#define CLK_TOP_MUX_CAMTG 222 +#define CLK_TOP_MUX_FD 223 +#define CLK_TOP_MUX_AUDIO 224 + +/* CLK_CFG_7 */ +#define CLK_TOP_MUX_FIX 225 +#define CLK_TOP_MUX_VDEC 226 +#define CLK_TOP_MUX_DPILVDS 227 + +/* CLK_CFG_8 */ +#define CLK_TOP_MUX_PMICSPI 228 +#define CLK_TOP_MUX_MSDC0 229 +#define CLK_TOP_MUX_SMI_MFG_AS 230 + +#define CLK_TOPCK_PMICSPI 301 + + +/* INFRACFG */ +#define CLK_INFRA_MUX1 1 + +#define CLK_INFRA_DBGCLK 64 +#define CLK_INFRA_SMI 65 +#define CLK_INFRA_SPI0 66 +#define CLK_INFRA_AUDIO 69 +#define CLK_INFRA_DEVAPC 70 +#define CLK_INFRA_MFGAXI 71 +#define CLK_INFRA_M4U 72 +#define CLK_INFRA_MD1MCUAXI 73 +#define CLK_INFRA_MD1HWMIXAXI 74 +#define CLK_INFRA_MD1AHB 75 +#define CLK_INFRA_MD2MCUAXI 76 +#define CLK_INFRA_MD2HWMIXAXI 77 +#define CLK_INFRA_MD2AHB 78 +#define CLK_INFRA_CPUM 79 +#define CLK_INFRA_KP 80 +#define CLK_INFRA_CCIF0 84 +#define CLK_INFRA_CCIF1 85 +#define CLK_INFRA_PMICSPI 86 +#define CLK_INFRA_PMICWRAP 87 + + +/* PERICFG */ +#define CLK_PERI0_NFI 0 +#define CLK_PERI0_THERM 1 +#define CLK_PERI0_PWM1 2 +#define CLK_PERI0_PWM2 3 +#define CLK_PERI0_PWM3 4 +#define CLK_PERI0_PWM4 5 +#define CLK_PERI0_PWM5 6 +#define CLK_PERI0_PWM6 7 +#define CLK_PERI0_PWM7 8 +#define CLK_PERI0_PWM 9 +#define CLK_PERI0_USB0 10 +#define CLK_PERI0_USB1 11 +#define CLK_PERI0_APDMA 12 +#define CLK_PERI0_MSDC0 13 +#define CLK_PERI0_MSDC1 14 +#define CLK_PERI0_MSDC2 15 +#define CLK_PERI0_MSDC3 16 +#define CLK_PERI0_MSDC4 17 +#define CLK_PERI0_APHIF 18 +#define CLK_PERI0_MDHIF 19 +#define CLK_PERI0_NLI 20 +#define CLK_PERI0_IRDA 21 +#define CLK_PERI0_UART0 22 +#define CLK_PERI0_UART1 23 +#define CLK_PERI0_UART2 24 +#define CLK_PERI0_UART3 25 +#define CLK_PERI0_I2C0 26 +#define CLK_PERI0_I2C1 27 +#define CLK_PERI0_I2C2 28 +#define CLK_PERI0_I2C3 29 +#define CLK_PERI0_I2C4 30 +#define CLK_PERI0_I2C5 31 + +#define CLK_PERI1_I2C6 32 +#define CLK_PERI1_PWRAP 33 +#define CLK_PERI1_AUXADC 34 +#define CLK_PERI1_SPI1 35 +#define CLK_PERI1_FHCTL 36 + +#define CLK_PERI_MUX_UART0 37 +#define CLK_PERI_MUX_UART1 38 +#define CLK_PERI_MUX_UART2 39 +#define CLK_PERI_MUX_UART3 40 + + +/* DISP */ +#define CLK_DISP0_LARB2_SMI 128 +#define CLK_DISP0_ROT_ENGINE 129 +#define CLK_DISP0_ROT_SMI 130 +#define CLK_DISP0_SCL 131 +#define CLK_DISP0_OVL_ENGINE 132 +#define CLK_DISP0_OVL_SMI 133 +#define CLK_DISP0_COLOR 134 +#define CLK_DISP0_2DSHP 135 +#define CLK_DISP0_BLS 136 +#define CLK_DISP0_WDMA0_ENGINE 137 +#define CLK_DISP0_WDMA0_SMI 138 +#define CLK_DISP0_WDMA1_ENGINE 139 +#define CLK_DISP0_WDMA1_SMI 140 +#define CLK_DISP0_RDMA0_ENGINE 141 +#define CLK_DISP0_RDMA0_SMI 142 +#define CLK_DISP0_RDMA0_OUTPUT 143 +#define CLK_DISP0_RDMA1_ENGINE 144 +#define CLK_DISP0_RDMA1_SMI 145 +#define CLK_DISP0_RDMA1_OUTPUT 146 +#define CLK_DISP0_GAMMA_ENGINE 147 +#define CLK_DISP0_GAMMA_PIXEL 148 +#define CLK_DISP0_CMDQ_ENGINE 149 +#define CLK_DISP0_CMDQ_SMI 150 +#define CLK_DISP0_G2D_ENGINE 151 +#define CLK_DISP0_G2D_SMI 152 + +#define CLK_DISP1_DBI_ENGINE 160 +#define CLK_DISP1_DBI_SMI 161 +#define CLK_DISP1_DBI_OUTPUT 162 +#define CLK_DISP1_DSI_ENGINE 163 +#define CLK_DISP1_DSI_DIGITAL 164 +#define CLK_DISP1_DSI_DIGITAL_LANE 165 +#define CLK_DISP1_DPI0 166 +#define CLK_DISP1_DPI1 167 +#define CLK_DISP1_LCD 168 +#define CLK_DISP1_SLCD 169 + + +/* IMG */ +#define CLK_IMAGE_LARB3_SMI 192 +#define CLK_IMAGE_LARB4_SMI 194 +#define CLK_IMAGE_COMMN_SMI 196 +#define CLK_IMAGE_CAM_SMI 197 +#define CLK_IMAGE_CAM_CAM 198 +#define CLK_IMAGE_SEN_TG 199 +#define CLK_IMAGE_SEN_CAM 200 +#define CLK_IMAGE_JPGD_SMI 201 +#define CLK_IMAGE_JPGD_JPG 202 +#define CLK_IMAGE_JPGE_SMI 203 +#define CLK_IMAGE_JPGE_JPG 204 +#define CLK_IMAGE_FPC 205 + + +/* MFG */ +#define CLK_MFG_AXI 224 +#define CLK_MFG_MEM 225 +#define CLK_MFG_G3D 226 +#define CLK_MFG_HYD 227 + + +/* AUD */ +#define CLK_AUDIO_AFE 258 +#define CLK_AUDIO_I2S 262 + + +/* VDEC */ +#define CLK_VDEC0_VDE 288 + +#define CLK_VDEC1_SMI 320 + + +/* VENC */ +#define CLK_VENC_VEN 352 diff --git a/include/dt-bindings/reset/mt6589-resets.h b/include/dt-bindings/reset/mt6589-resets.h new file mode 100644 index 00000000000000..12f2c784aecd4f --- /dev/null +++ b/include/dt-bindings/reset/mt6589-resets.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 akku + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6589 +#define _DT_BINDINGS_RESET_CONTROLLER_MT6589 + +/* PERI */ +#define MT6589_PERI_UART0_SW_RST 0 +#define MT6589_PERI_UART1_SW_RST 1 +#define MT6589_PERI_UART2_SW_RST 2 +#define MT6589_PERI_UART3_SW_RST 3 +#define MT6589_PERI_IRDA_SW_RST 4 +#define MT6589_PERI_PTP_RST 5 +#define MT6589_PERI_AP_HIF_SW_RST 6 +#define MT6589_PERI_MD_HIF_SW_RST 8 +#define MT6589_PERI_NLI_SW_RST 9 +#define MT6589_PERI_AUXADC_SW_RST 10 +#define MT6589_PERI_DMA_SW_RS_RST 11 +#define MT6589_PERI_NFI_SW_RST_RST 14 +#define MT6589_PERI_PWM_SW_RST 15 +#define MT6589_PERI_THERM_SW_RST 16 +#define MT6589_PERI_MSDC0_SW_RST 17 +#define MT6589_PERI_MSDC1_SW_RST 18 +#define MT6589_PERI_MSDC2_SW_RST 19 +#define MT6589_PERI_MSDC3_SW_RST 20 +#define MT6589_PERI_I2C0_SW_RST 22 +#define MT6589_PERI_I2C1_SW_RST 23 +#define MT6589_PERI_I2C2_SW_RST 24 +#define MT6589_PERI_I2C3_SW_RST 25 +#define MT6589_PERI_I2C4_SW_RST 26 +#define MT6589_PERI_I2C5_SW_RST 27 +#define MT6589_PERI_I2C6_SW_RST 28 +#define MT6589_PERI_USB_SW_RST 29 +#define MT6589_PERI_SPI0_SW_RST 33 + +/* INFRA */ +#define MT6589_INFRA_EMI_REG_RST 0 +#define MT6589_INFRA_DRAMC0_AO_RST 1 +#define MT6589_INFRA_CCIF0_RST 2 +#define MT6589_INFRA_AP_CIRP_EINT_RST 3 +#define MT6589_INFRA_APXGPT_RST 4 +#define MT6589_INFRA_SCPSYS_RST 5 +#define MT6589_INFRA_CCIF1_RST 6 +#define MT6589_INFRA_PMIC_WRAP_RST 7 +#define MT6589_INFRA_KP_RST 8 +#define MT6589_INFRA_EMI_RST 32 +#define MT6589_INFRA_DRAMC0_RST 34 +#define MT6589_INFRA_SMI_RST 35 +#define MT6589_INFRA_M4U_RST 36 + +/* TOPRGU */ +#define MT6589_TOPRGU_INFRA_RST 0 +#define MT6589_TOPRGU_DISP_RST 1 +#define MT6589_TOPRGU_MFG_RST 2 +#define MT6589_TOPRGU_VENC_RST 3 +#define MT6589_TOPRGU_VDEC_RST 4 +#define MT6589_TOPRGU_IMG_RST 5 +#define MT6589_TOPRGU_DDRPHY_RST 6 +#define MT6589_TOPRGU_MD_RST 7 +#define MT6589_TOPRGU_INFRA_AO_RST 8 +#define MT6589_TOPRGU_MD_LITE_RST 9 +#define MT6589_TOPRGU_APMIXED_RST 10 +#define MT6589_TOPRGU_PWRAP_SPICTL_RST 11 + +/* MFG */ +#define MT6589_MFG_AXI_RESET 0 +#define MT6589_MFG_G3D_RESET 1 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6589 */ From 222807091b547003b9f892989c4b60a1bcb4352d Mon Sep 17 00:00:00 2001 From: akku Date: Fri, 2 Jan 2026 16:34:46 +0900 Subject: [PATCH 20/98] arm: dts: mt6589: move watchdog node in order of address --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 8603a2e9069aed..5b9161c2155a13 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -81,6 +81,11 @@ compatible = "simple-bus"; ranges; + wdt: watchdog@10000000 { + compatible = "mediatek,mt6589-wdt"; + reg = <0x10000000 0x44>; + }; + topckgen: syscon@10000100 { compatible = "mediatek,mt6589-topckgen", "syscon"; reg = <0x10000100 0x7c>; @@ -202,11 +207,5 @@ clocks = <&uart_clk>; status = "disabled"; }; - - /* FIXME: Register area that overlaps with topckgen */ - wdt: watchdog@10000000 { - compatible = "mediatek,mt6589-wdt"; - reg = <0x10000000 0x44>; - }; }; }; From ce0713ddf3a01bcfa80bedf4cc3ca574e092496d Mon Sep 17 00:00:00 2001 From: akku Date: Fri, 2 Jan 2026 17:08:10 +0900 Subject: [PATCH 21/98] arm: dts: mediatek: mt6589: enable UART clock controls --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 5b9161c2155a13..7b265fa25f2166 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -7,6 +7,7 @@ #include #include +#include / { #address-cells = <1>; @@ -67,12 +68,6 @@ clock-output-names = "rtc_clk"; #clock-cells = <0>; }; - - uart_clk: dummy26m { - compatible = "fixed-clock"; - clock-frequency = <26000000>; - #clock-cells = <0>; - }; }; soc { @@ -180,7 +175,8 @@ compatible = "mediatek,mt6577-uart"; reg = <0x11006000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_MUX_UART0>, <&pericfg CLK_PERI0_UART0>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -188,7 +184,8 @@ compatible = "mediatek,mt6577-uart"; reg = <0x11007000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_MUX_UART1>, <&pericfg CLK_PERI0_UART1>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -196,7 +193,8 @@ compatible = "mediatek,mt6577-uart"; reg = <0x11008000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_MUX_UART2>, <&pericfg CLK_PERI0_UART2>; + clock-names = "baud", "bus"; status = "disabled"; }; @@ -204,7 +202,8 @@ compatible = "mediatek,mt6577-uart"; reg = <0x11009000 0x400>; interrupts = ; - clocks = <&uart_clk>; + clocks = <&pericfg CLK_PERI_MUX_UART3>, <&pericfg CLK_PERI0_UART3>; + clock-names = "baud", "bus"; status = "disabled"; }; }; From 7c0fc2d6222ef7195190cba13db980d2a05a3afa Mon Sep 17 00:00:00 2001 From: akku Date: Fri, 2 Jan 2026 17:27:08 +0900 Subject: [PATCH 22/98] dt-bindings: dma: add mediatek,mt6589-uart-dma --- Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml | 1 + arch/arm/configs/lenovo-blade_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index dab468a88942d6..c80f8f43c55581 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - mediatek,mt2712-uart-dma + - mediatek,mt6589-uart-dma - mediatek,mt6795-uart-dma - mediatek,mt8365-uart-dma - mediatek,mt8516-uart-dma diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 9f1c2f63af3b51..a563b5de9b32fb 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -65,6 +65,7 @@ CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_MT6577=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_MTK_UART_APDMA=y ## I2C CONFIG_I2C=y From de943c895e17a3e7975173069603fed34be5eb5e Mon Sep 17 00:00:00 2001 From: akku Date: Fri, 2 Jan 2026 18:43:31 +0900 Subject: [PATCH 23/98] arm: dts: mt6589: setup uart apdma --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 28 ++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 7b265fa25f2166..deeb1494f15a3a 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -171,12 +171,35 @@ <0x10216000 0x2000>; }; + apdma: dma-controller@11000680 { + compatible = "mediatek,mt6589-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0x11000680 0x54>, + <0x11000700 0x54>, + <0x11000780 0x54>, + <0x11000800 0x54>, + <0x11000880 0x54>, + <0x11000900 0x54>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&pericfg CLK_PERI0_APDMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + uart0: serial@11006000 { compatible = "mediatek,mt6577-uart"; reg = <0x11006000 0x400>; interrupts = ; clocks = <&pericfg CLK_PERI_MUX_UART0>, <&pericfg CLK_PERI0_UART0>; clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -186,6 +209,8 @@ interrupts = ; clocks = <&pericfg CLK_PERI_MUX_UART1>, <&pericfg CLK_PERI0_UART1>; clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -195,10 +220,13 @@ interrupts = ; clocks = <&pericfg CLK_PERI_MUX_UART2>, <&pericfg CLK_PERI0_UART2>; clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; status = "disabled"; }; uart3: serial@11009000 { + /* NOTE: MT6589 does not have DMA for UART3 */ compatible = "mediatek,mt6577-uart"; reg = <0x11009000 0x400>; interrupts = ; From 294b4d2280a5d0dc2e6a2ff6590a087ef3261aa2 Mon Sep 17 00:00:00 2001 From: "Tsuyukusa Akari (-akku-)" Date: Sat, 3 Jan 2026 00:21:51 +0900 Subject: [PATCH 24/98] clk: mediatek: mt6589-apmixedsys: add original copyright (mt2712) --- drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c index 0b436b7d3934a3..8b4dd5bdaf5876 100644 --- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2017 MediaTek Inc. + * Weiyi Lu + * Copyright (c) 2023 Collabora Ltd. + * AngeloGioacchino Del Regno * Author: akku */ #include From 20e1ae316d76e3f8351d880defc5a9690bbe11cc Mon Sep 17 00:00:00 2001 From: "Tsuyukusa Akari (-akku-)" Date: Mon, 5 Jan 2026 23:34:20 +0900 Subject: [PATCH 25/98] clk: mediatek: mt6589-apmixedsys: fix copyright --- drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c index 8b4dd5bdaf5876..714670194270b7 100644 --- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -1,10 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Author: akku + * + * Based on clk-mt2712-apmixedsys.c * Copyright (c) 2017 MediaTek Inc. * Weiyi Lu * Copyright (c) 2023 Collabora Ltd. * AngeloGioacchino Del Regno - * Author: akku */ #include #include @@ -95,8 +97,6 @@ static const struct mtk_pll_data plls[] = { 0, 7, ISPPLL_CON0, 7, ISPPLL_CON0, 8, 1664000000), }; -/* init logic from MT2712 */ - static int clk_mt6589_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; From 7b7bf7a6645b3e4580fb19acc77c5f1d71b0c9fa Mon Sep 17 00:00:00 2001 From: Tsuyukusa Akari Date: Sun, 11 Jan 2026 22:11:24 +0900 Subject: [PATCH 26/98] pinctrl: mediatek: introduce MT6589 pinctrl driver --- .../devicetree/bindings/mfd/syscon.yaml | 4 + .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 27 + arch/arm/configs/lenovo-blade_defconfig | 2 +- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt2701.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt2712.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt6397.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt6589.c | 465 ++++ drivers/pinctrl/mediatek/pinctrl-mt8127.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8135.c | 8 + drivers/pinctrl/mediatek/pinctrl-mt8167.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8173.c | 2 - drivers/pinctrl/mediatek/pinctrl-mt8365.c | 3 - drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 64 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 10 +- drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h | 2336 +++++++++++++++++ 19 files changed, 2900 insertions(+), 42 deletions(-) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6589.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fedb..7fc84cdeaa1185 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -84,6 +84,8 @@ select: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt6589-pctl-a-syscfg + - mediatek,mt6589-pctl-b-syscfg - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg @@ -190,6 +192,8 @@ properties: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg + - mediatek,mt6589-pctl-a-syscfg + - mediatek,mt6589-pctl-b-syscfg - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index b9680b896f12f8..19270dd0fec1bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -18,6 +18,7 @@ properties: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl - mediatek,mt6397-pinctrl + - mediatek,mt6589-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl - mediatek,mt8135-pinctrl diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index deeb1494f15a3a..ee7d8d5cc55862 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -143,6 +143,33 @@ #clock-cells = <1>; }; + /* + * EINT registers: 0x1000b000 + * GPIO base: 0x10005000, GPIO1 base 0x1020c000 + */ + pio: pinctrl@10005000 { + compatible = "mediatek,mt6589-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + ; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt6589-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + syscfg_pctl_b: syscfg_pctl_b@1020c000 { + compatible = "mediatek,mt6589-pctl-b-syscfg", "syscon"; + reg = <0 0x1020c000 0 0x1000>; + }; + timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index a563b5de9b32fb..13cbcc326d43cf 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -79,7 +79,7 @@ CONFIG_SPI_MT65XX=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MTK=y CONFIG_EINT_MTK=y -#CONFIG_PINCTRL_MT6589=y # not ported +CONFIG_PINCTRL_MT6589=y ## GPIO diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 2d15af6be27628..8d9f84701793ac 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -97,6 +97,13 @@ config PINCTRL_MT2701 default MACH_MT2701 select PINCTRL_MTK +config PINCTRL_MT6589 + bool "MediaTek MT6589 pin control" + depends on MACH_MT6589 || COMPILE_TEST + depends on OF + default MACH_MT6589 + select PINCTRL_MTK + config PINCTRL_MT7623 bool "MediaTek MT7623 pin control with generic binding" depends on MACH_MT7623 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 7518980fba5960..249920adc36e00 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o obj-$(CONFIG_PINCTRL_MT2712) += pinctrl-mt2712.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o +obj-$(CONFIG_PINCTRL_MT6589) += pinctrl-mt6589.o obj-$(CONFIG_PINCTRL_MT6765) += pinctrl-mt6765.o obj-$(CONFIG_PINCTRL_MT6779) += pinctrl-mt6779.o obj-$(CONFIG_PINCTRL_MT6795) += pinctrl-mt6795.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 6b1c7122b0fb99..30bec29de9bdc0 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -504,8 +504,6 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { .dout_offset = 0x0500, .din_offset = 0x0630, .pinmux_offset = 0x0760, - .type1_start = 280, - .type1_end = 280, .port_shf = 4, .port_mask = 0x1f, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index bb7394ae252b48..eb6ecaa726793a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -553,8 +553,6 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { .dout_offset = 0x0300, .din_offset = 0x0400, .pinmux_offset = 0x0500, - .type1_start = 210, - .type1_end = 210, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index 03d0f65d7bcc1f..af5f48039895e6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -27,8 +27,6 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { .dout_offset = (MT6397_PIN_REG_BASE + 0x080), .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), - .type1_start = 41, - .type1_end = 41, .port_shf = 3, .port_mask = 0x3, .port_align = 2, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6589.c b/drivers/pinctrl/mediatek/pinctrl-mt6589.c new file mode 100644 index 00000000000000..45d04d4559892d --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6589.c @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + * + * Based on pinctrl-mt2701.c + * Copyright (c) 2015 MediaTek Inc. + * Author: Biao Huang + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6589.h" + +/* + * E2, E4, E8, E16: Drive + * SR: ??? + * DM: Dummy + * MSB <-> LSB + */ +static const struct mtk_drv_group_desc mt6589_drv_grp[] = { + /* grp 0: SR E8 E4 E2: 2/4/6/8/10/12/14/16mA */ + MTK_DRV_GRP(2, 16, 0, 2, 2), + /* grp 1: SR E8 E4 DM: 4/8/12/16mA */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* grp 2: SR E4 E2 DM: 2/4/6/8mA */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* grp 3: SR E16 E8 E4 4/8/12/16/20/24/28/32mA */ + MTK_DRV_GRP(4, 32, 0, 2, 4), +}; + + +/* GPIO0 */ +#define DRV_CON0 0x0500 +#define DRV_CON1 0x0510 +#define DRV_CON2 0x0520 +#define DRV_CON3 0x0530 +#define DRV_CON4 0x0540 +#define DRV_CON5 0x0550 + +/* GPIO1 */ +#define DRV_CON6 0x0560 +#define DRV_CON7 0x0570 +#define DRV_CON8 0x0580 +#define DRV_CON9 0x0590 + +/* GPIO0 */ +#define DRV_CON10 0x05a0 +#define DRV_CON11 0x05b0 +#define DRV_CON12 0x05c0 + +static const struct mtk_pin_drv_grp mt6589_pin_drv[] = { + /* MSDC0_DAT 7 to 4 */ + MTK_PIN_DRV_GRP(0, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(1, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(2, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(3, DRV_CON0, 0, 0), + + /* MSDC0_RSTB */ + MTK_PIN_DRV_GRP(4, DRV_CON0, 8, 1), + + /* MSDC0_CMD */ + MTK_PIN_DRV_GRP(5, DRV_CON0, 4, 0), + + /* MSDC0_CLK */ + MTK_PIN_DRV_GRP(6, DRV_CON12, 12, 0), + + /* MSDC0_DAT 3 to 0 */ + MTK_PIN_DRV_GRP(7, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(8, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(9, DRV_CON0, 0, 0), + MTK_PIN_DRV_GRP(10, DRV_CON0, 0, 0), + + /* NFI */ + MTK_PIN_DRV_GRP(11, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(12, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(13, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(14, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(15, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(16, DRV_CON0, 12, 1), + MTK_PIN_DRV_GRP(17, DRV_CON0, 12, 1), + + /* NLD 0 to 15 */ + MTK_PIN_DRV_GRP(18, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(19, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(20, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(21, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(22, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(23, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(24, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(25, DRV_CON0, 16, 1), + MTK_PIN_DRV_GRP(26, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(27, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(28, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(29, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(30, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(31, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(32, DRV_CON0, 20, 1), + MTK_PIN_DRV_GRP(33, DRV_CON0, 20, 1), + + /* EINT 0 to 4 */ + MTK_PIN_DRV_GRP(34, DRV_CON0, 24, 2), + MTK_PIN_DRV_GRP(35, DRV_CON0, 28, 2), + MTK_PIN_DRV_GRP(36, DRV_CON1, 0, 2), + MTK_PIN_DRV_GRP(37, DRV_CON1, 4, 2), + MTK_PIN_DRV_GRP(38, DRV_CON1, 8, 2), + + /* SPI0 */ + MTK_PIN_DRV_GRP(39, DRV_CON1, 12, 1), + MTK_PIN_DRV_GRP(40, DRV_CON1, 12, 1), + MTK_PIN_DRV_GRP(41, DRV_CON1, 12, 1), + MTK_PIN_DRV_GRP(42, DRV_CON1, 12, 1), + MTK_PIN_DRV_GRP(43, DRV_CON1, 12, 1), + + /* SIM */ + MTK_PIN_DRV_GRP(44, DRV_CON1, 16, 1), + MTK_PIN_DRV_GRP(45, DRV_CON1, 16, 1), + MTK_PIN_DRV_GRP(46, DRV_CON1, 16, 1), + MTK_PIN_DRV_GRP(47, DRV_CON1, 16, 1), + MTK_PIN_DRV_GRP(48, DRV_CON1, 16, 1), + MTK_PIN_DRV_GRP(49, DRV_CON1, 16, 1), + + /* ADC */ + MTK_PIN_DRV_GRP(50, DRV_CON1, 20, 1), + MTK_PIN_DRV_GRP(51, DRV_CON1, 20, 1), + MTK_PIN_DRV_GRP(52, DRV_CON1, 20, 1), + + /* DAC */ + MTK_PIN_DRV_GRP(53, DRV_CON1, 24, 1), + MTK_PIN_DRV_GRP(54, DRV_CON1, 24, 1), + MTK_PIN_DRV_GRP(55, DRV_CON1, 24, 1), + + /* RTC32K_CK */ + /* + MTK_PIN_DRV_GRP(56, , , 1), // no drive? + */ + + /* IDDIG */ + MTK_PIN_DRV_GRP(57, DRV_CON1, 28, 2), + + /* WATCHDOG */ + MTK_PIN_DRV_GRP(58, DRV_CON2, 0, 1), + + /* SRCLKENA */ + MTK_PIN_DRV_GRP(59, DRV_CON2, 4, 1), + + /* SRCVOLTEN */ + MTK_PIN_DRV_GRP(60, DRV_CON2, 8, 1), + + /* JTAG */ + MTK_PIN_DRV_GRP(61, DRV_CON3, 0, 1), + MTK_PIN_DRV_GRP(62, DRV_CON3, 0, 1), + MTK_PIN_DRV_GRP(63, DRV_CON3, 0, 1), + MTK_PIN_DRV_GRP(64, DRV_CON3, 0, 1), + MTK_PIN_DRV_GRP(65, DRV_CON3, 0, 1), + MTK_PIN_DRV_GRP(66, DRV_CON3, 0, 1), + + /* UR2 */ + MTK_PIN_DRV_GRP(69, DRV_CON3, 4, 1), + MTK_PIN_DRV_GRP(70, DRV_CON3, 8, 1), + MTK_PIN_DRV_GRP(71, DRV_CON3, 12, 1), + MTK_PIN_DRV_GRP(72, DRV_CON3, 16, 1), + + /* PWM 1 to 4 */ + MTK_PIN_DRV_GRP(73, DRV_CON3, 20, 1), + MTK_PIN_DRV_GRP(74, DRV_CON3, 24, 1), + MTK_PIN_DRV_GRP(75, DRV_CON3, 28, 1), + MTK_PIN_DRV_GRP(76, DRV_CON4, 0, 1), + + /* UR1 */ + MTK_PIN_DRV_GRP(77, DRV_CON4, 4, 1), + MTK_PIN_DRV_GRP(78, DRV_CON4, 8, 1), + MTK_PIN_DRV_GRP(79, DRV_CON4, 12, 1), + MTK_PIN_DRV_GRP(80, DRV_CON4, 16, 1), + + /* UR4 */ + MTK_PIN_DRV_GRP(81, DRV_CON4, 20, 1), + MTK_PIN_DRV_GRP(82, DRV_CON4, 24, 1), + + /* BPI1B */ + MTK_PIN_DRV_GRP(83, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(84, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(85, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(86, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(87, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(88, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(89, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(90, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(91, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(92, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(93, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(94, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(95, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(96, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(97, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(98, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(99, DRV_CON5, 12, 1), + + /* VM 1, 0 */ + MTK_PIN_DRV_GRP(100, DRV_CON5, 12, 1), + MTK_PIN_DRV_GRP(101, DRV_CON5, 12, 1), + + /* BSI 1 */ + MTK_PIN_DRV_GRP(102, DRV_CON5, 16, 1), + MTK_PIN_DRV_GRP(103, DRV_CON5, 16, 1), + MTK_PIN_DRV_GRP(104, DRV_CON5, 16, 1), + + /* TXBPI1 */ + MTK_PIN_DRV_GRP(105, DRV_CON5, 20, 1), + + /* EXT_CLK_EN */ + MTK_PIN_DRV_GRP(106, DRV_CON4, 28, 1), + + /* SRCLKENA2 */ + MTK_PIN_DRV_GRP(107, DRV_CON5, 0, 1), + + /* BSI1A */ + MTK_PIN_DRV_GRP(108, DRV_CON5, 4, 1), + MTK_PIN_DRV_GRP(109, DRV_CON5, 4, 1), + MTK_PIN_DRV_GRP(110, DRV_CON5, 4, 1), + MTK_PIN_DRV_GRP(111, DRV_CON5, 4, 1), + MTK_PIN_DRV_GRP(112, DRV_CON5, 4, 1), + + /* BSI1C */ + MTK_PIN_DRV_GRP(113, DRV_CON5, 8, 1), + MTK_PIN_DRV_GRP(114, DRV_CON5, 8, 1), + + /* EINT10_AUXIN2, EINT11_AUXIN3, EINT16_AUXIN3 */ + MTK_PIN_DRV_GRP(115, DRV_CON6, 0, 1), + MTK_PIN_DRV_GRP(116, DRV_CON6, 4, 1), + MTK_PIN_DRV_GRP(117, DRV_CON6, 8, 1), + + /* I2S */ + MTK_PIN_DRV_GRP(120, DRV_CON6, 12, 1), + MTK_PIN_DRV_GRP(121, DRV_CON6, 12, 1), + MTK_PIN_DRV_GRP(122, DRV_CON6, 12, 1), + MTK_PIN_DRV_GRP(123, DRV_CON6, 12, 1), + + /* EINT 5 to 9 */ + MTK_PIN_DRV_GRP(124, DRV_CON6, 16, 2), + MTK_PIN_DRV_GRP(125, DRV_CON6, 20, 2), + MTK_PIN_DRV_GRP(126, DRV_CON6, 24, 2), + MTK_PIN_DRV_GRP(127, DRV_CON6, 28, 2), + MTK_PIN_DRV_GRP(128, DRV_CON7, 0, 2), + + /* DISP_PWM */ + MTK_PIN_DRV_GRP(129, DRV_CON7, 28, 1), + + /* LPTE/MSDC4_DAT0, LRSTB/MSDC4_DAT1 */ + MTK_PIN_DRV_GRP(130, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(131, DRV_CON8, 20, 0), + + /* LPCE1B, LPCE0B */ + MTK_PIN_DRV_GRP(132, DRV_CON8, 28, 1), + MTK_PIN_DRV_GRP(133, DRV_CON9, 0, 1), + + /* SPI1 / MSDC4 */ + MTK_PIN_DRV_GRP(134, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(135, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(136, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(137, DRV_CON8, 20, 0), + + /* LCD / MSDC4 */ + MTK_PIN_DRV_GRP(138, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(139, DRV_CON8, 0, 0), + MTK_PIN_DRV_GRP(140, DRV_CON8, 20, 0), + MTK_PIN_DRV_GRP(141, DRV_CON7, 16, 0), + MTK_PIN_DRV_GRP(142, DRV_CON7, 20, 1), + + /* DPI */ + MTK_PIN_DRV_GRP(143, DRV_CON9, 8, 1), + MTK_PIN_DRV_GRP(144, DRV_CON9, 8, 1), + MTK_PIN_DRV_GRP(145, DRV_CON9, 8, 1), + MTK_PIN_DRV_GRP(146, DRV_CON9, 8, 1), + MTK_PIN_DRV_GRP(147, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(148, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(149, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(150, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(151, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(152, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(153, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(154, DRV_CON9, 12, 1), + MTK_PIN_DRV_GRP(155, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(156, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(157, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(158, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(159, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(160, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(161, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(162, DRV_CON9, 16, 1), + MTK_PIN_DRV_GRP(163, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(164, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(165, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(166, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(167, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(168, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(169, DRV_CON9, 20, 1), + MTK_PIN_DRV_GRP(170, DRV_CON9, 20, 1), + + /* MSDC1_INSI, MSDC2_INSI */ + MTK_PIN_DRV_GRP(171, DRV_CON9, 24, 1), + MTK_PIN_DRV_GRP(172, DRV_CON10, 0, 1), + + /* MSDC2 */ + MTK_PIN_DRV_GRP(173, DRV_CON10, 4, 1), + MTK_PIN_DRV_GRP(174, DRV_CON10, 8, 3), + MTK_PIN_DRV_GRP(175, DRV_CON10, 8, 3), + MTK_PIN_DRV_GRP(176, DRV_CON10, 12, 3), + MTK_PIN_DRV_GRP(177, DRV_CON12, 20, 3), + MTK_PIN_DRV_GRP(178, DRV_CON10, 8, 3), + MTK_PIN_DRV_GRP(179, DRV_CON10, 8, 3), + + /* MSDC1 */ + MTK_PIN_DRV_GRP(180, DRV_CON10, 20, 3), + MTK_PIN_DRV_GRP(181, DRV_CON10, 20, 3), + MTK_PIN_DRV_GRP(182, DRV_CON10, 16, 1), + MTK_PIN_DRV_GRP(183, DRV_CON10, 24, 3), + MTK_PIN_DRV_GRP(184, DRV_CON12, 16, 3), + MTK_PIN_DRV_GRP(185, DRV_CON10, 20, 3), + MTK_PIN_DRV_GRP(186, DRV_CON10, 20, 3), + + /* CMPCLK, CMMCLK, CMRST, CMPDN, CMFLASH */ + MTK_PIN_DRV_GRP(209, DRV_CON11, 0, 1), + MTK_PIN_DRV_GRP(210, DRV_CON11, 4, 1), + MTK_PIN_DRV_GRP(211, DRV_CON11, 8, 1), + MTK_PIN_DRV_GRP(212, DRV_CON11, 12, 1), + MTK_PIN_DRV_GRP(213, DRV_CON11, 16, 1), + + /* SRCLKENAI */ + MTK_PIN_DRV_GRP(218, DRV_CON11, 20, 1), + + /* UR3 */ + MTK_PIN_DRV_GRP(219, DRV_CON11, 24, 1), + MTK_PIN_DRV_GRP(220, DRV_CON11, 28, 1), + + /* PCM0 */ + MTK_PIN_DRV_GRP(221, DRV_CON12, 0, 2), + MTK_PIN_DRV_GRP(222, DRV_CON12, 0, 2), + MTK_PIN_DRV_GRP(223, DRV_CON12, 0, 2), + MTK_PIN_DRV_GRP(224, DRV_CON12, 0, 2), + MTK_PIN_DRV_GRP(225, DRV_CON12, 0, 2), + + /* MSDC3 */ + MTK_PIN_DRV_GRP(226, DRV_CON12, 4, 0), + MTK_PIN_DRV_GRP(227, DRV_CON12, 4, 0), + MTK_PIN_DRV_GRP(228, DRV_CON12, 8, 0), + MTK_PIN_DRV_GRP(229, DRV_CON12, 24, 0), + MTK_PIN_DRV_GRP(230, DRV_CON12, 4, 0), + MTK_PIN_DRV_GRP(231, DRV_CON12, 4, 0), +}; + +#define MT6589_SIM_MODE_PER_REG 3 +#define MT6589_SIM_MODE_BITS 4 + +/* based on mtk_pmx_set_mode (pinctrl-mtk-common.c)*/ +static void mt6589_pinmux_set(struct regmap *reg, unsigned int pin, unsigned int mode) +{ + unsigned int pin2, reg_addr, val; + unsigned char bit; + unsigned int mask = (1L << MT6589_SIM_MODE_BITS) - 1; + if (pin < 44 || pin > 49) return; + + pin2 = pin - 44; + if (pin2 <= 2) reg_addr = 0x0980; + else reg_addr = 0x09a0; + + mode &= mask; + bit = pin2 % MT6589_SIM_MODE_PER_REG; + mask <<= (MT6589_SIM_MODE_BITS * bit); + val = (mode << (MT6589_SIM_MODE_BITS * bit)); + regmap_update_bits(reg, reg_addr, mask, val); +} + +static int mt6589_pull_set(struct regmap *regmap, + const struct mtk_pinctrl_devdata *devdata, + unsigned int pin, bool isup, unsigned int arg) +{ + unsigned int pin2, reg_addr, bit_en, bit_sel; + unsigned int mask, val; + bool enable = (arg != MTK_PUPD_SET_R1R0_00); + + if (pin < 44 || pin > 49) + return -EINVAL; + + pin2 = pin - 44; + if (pin2 <= 2) + reg_addr = 0x0990; + else + reg_addr = 0x09b0; + + bit_en = (pin2 % 3) + 4; + bit_sel = (pin2 % 3) + 8; + + mask = BIT(bit_en) | BIT(bit_sel); + val = (enable ? BIT(bit_en) : 0) | (isup ? BIT(bit_sel) : 0); + + regmap_update_bits(regmap, reg_addr, mask, val); + + return 0; +} + +/* TODO: MSDC_R0, BIAS */ +static const struct mtk_pinctrl_devdata mt6589_pinctrl_data = { + .pins = mtk_pins_mt6589, + .npins = ARRAY_SIZE(mtk_pins_mt6589), + .grp_desc = mt6589_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt6589_drv_grp), + .pin_drv_grp = mt6589_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt6589_pin_drv), + .drv_multibase = true, + .spec_pull_set = mt6589_pull_set, + .dir_offset = 0x0000, + .ies_offset = 0x0100, + .ies_multibase = true, + .pullen_offset = 0x0200, + .pullen_multibase = true, + .smt_offset = 0x0300, + .smt_multibase = true, + .pullsel_offset = 0x0400, + .pullsel_multibase = true, + .dout_offset = 0x0800, + .din_offset = 0x0a00, + .pinmux_offset = 0x0c00, + .spec_pinmux_set = mt6589_pinmux_set, + .type1_start = 114, + .type1_end = 169 + 1, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, + .eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 192, + .db_cnt = 16, + .db_time = debounce_time_mt6795, + }, +}; + +static const struct of_device_id mt6589_pctrl_match[] = { + { .compatible = "mediatek,mt6589-pinctrl", .data = &mt6589_pinctrl_data }, + {}, +}; +MODULE_DEVICE_TABLE(of, mt6589_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mtk_pctrl_common_probe, + .driver = { + .name = "mediatek-mt6589-pinctrl", + .of_match_table = mt6589_pctrl_match, + .pm = pm_sleep_ptr(&mtk_eint_pm_ops), + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} +arch_initcall(mtk_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index f5030a9ea40b42..1ec1ddb317c33e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -272,8 +272,6 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .dout_offset = 0x0400, .din_offset = 0x0500, .pinmux_offset = 0x0600, - .type1_start = 143, - .type1_end = 143, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 77c6ac464e8607..9c9689be33be25 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -292,15 +292,23 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp), .pin_drv_grp = mt8135_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv), + .drv_multibase = true, .spec_pull_set = spec_pull_set, .dir_offset = 0x0000, + .dir_multibase = true, .ies_offset = 0x0100, + .ies_multibase = true, .pullen_offset = 0x0200, + .pullen_multibase = true, .smt_offset = 0x0300, + .smt_multibase = true, .pullsel_offset = 0x0400, + .pullsel_multibase = true, .dout_offset = 0x0800, + .dout_multibase = true, .din_offset = 0x0A00, .pinmux_offset = 0x0C00, + .pinmux_multibase = true, .type1_start = 34, .type1_end = 149, .port_shf = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 143c2662227252..27dfaabbf41ed6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -305,8 +305,6 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .dout_offset = 0x0100, .din_offset = 0x0200, .pinmux_offset = 0x0300, - .type1_start = 125, - .type1_end = 125, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index b214deeafbf1d6..cc1ad89635021b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -313,8 +313,6 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .dout_offset = 0x0400, .din_offset = 0x0500, .pinmux_offset = 0x0600, - .type1_start = 135, - .type1_end = 135, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index e3e0d66cfbbfcb..a58175cd81de17 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -456,9 +456,6 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .smt_offset = 0x0470, .pullen_offset = 0x0860, .pullsel_offset = 0x0900, - .drv_offset = 0x0710, - .type1_start = 145, - .type1_end = 145, .port_shf = 4, .port_mask = 0x1f, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index abda75d4354e28..c91e5f001c1090 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -305,8 +305,6 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .dout_offset = 0x0100, .din_offset = 0x0200, .pinmux_offset = 0x0300, - .type1_start = 125, - .type1_end = 125, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index a4cb6d511fcdb3..f4abb23bd26a59 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -42,14 +42,15 @@ static const char * const mtk_gpio_functions[] = { }; /* - * There are two base address for pull related configuration - * in mt8135, and different GPIO pins use different base address. - * When pin number greater than type1_start and less than type1_end, - * should use the second base address. + * Some chips (e.g., mt8135) have multiple base addresses for pin configuration. + * When multibase is true and the pin number falls within the specified range + * [type1_start, type1_end), the second base address should be used. */ static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, - unsigned long pin) + unsigned long pin, bool multibase) { + if (!multibase) + return pctl->regmap1; if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) return pctl->regmap2; return pctl->regmap1; @@ -82,7 +83,8 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, else reg_addr = SET_ADDR(reg_addr, pctl); - regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), + reg_addr, bit); return 0; } @@ -100,7 +102,8 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) else reg_addr = CLR_ADDR(reg_addr, pctl); - return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); + return regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dout_multibase), + reg_addr, bit); } static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, @@ -108,6 +111,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, { unsigned int reg_addr, offset; unsigned int bit; + bool multibase; /** * Due to some soc are not support ies/smt config, add this special @@ -123,12 +127,18 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) return -EINVAL; + if (arg == PIN_CONFIG_INPUT_ENABLE) + multibase = pctl->devdata->ies_multibase; + else + multibase = pctl->devdata->smt_multibase; + /* * Due to some pins are irregular, their input enable and smt * control register are discontinuous, so we need this special handle. */ if (pctl->devdata->spec_ies_smt_set) { - return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), + return pctl->devdata->spec_ies_smt_set( + mtk_get_regmap(pctl, pin, multibase), pctl->devdata, pin, value, arg); } @@ -144,7 +154,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, else reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); - regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, pin, multibase), reg_addr, bit); return 0; } @@ -229,7 +239,8 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, shift = pin_drv->bit + drv_grp->low_bit; mask <<= shift; val <<= shift; - return regmap_update_bits(mtk_get_regmap(pctl, pin), + return regmap_update_bits( + mtk_get_regmap(pctl, pin, pctl->devdata->drv_multibase), pin_drv->offset, mask, val); } @@ -314,9 +325,9 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, * the parameter should be "MTK_PUPD_SET_R1R0_00". */ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; - ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), - pctl->devdata, pin, isup, - r1r0); + ret = pctl->devdata->spec_pull_set( + mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), + pctl->devdata, pin, isup, r1r0); if (!ret) return 0; } @@ -334,7 +345,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, pctl->devdata->pullen_offset; reg_pullsel = mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset; - ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + /* MT8365 do not use multibase. */ + ret = pctl->devdata->mt8365_set_clr_mode(pctl->regmap1, bit, reg_pullen, reg_pullsel, enable, isup); if (ret) @@ -358,8 +370,10 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset, pctl); - regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); - regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); + regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullen_multibase), + reg_pullen, bit); + regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), + reg_pullsel, bit); return 0; } @@ -710,8 +724,9 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); if (pctl->devdata->spec_pinmux_set) - pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), - pin, mode); + pctl->devdata->spec_pinmux_set( + mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), + pin, mode); reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf) + pctl->devdata->pinmux_offset; @@ -720,8 +735,9 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, bit = pin % pctl->devdata->mode_per_reg; mask <<= (GPIO_MODE_BITS * bit); val = (mode << (GPIO_MODE_BITS * bit)); - return regmap_update_bits(mtk_get_regmap(pctl, pin), - reg_addr, mask, val); + return regmap_update_bits( + mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), + reg_addr, mask, val); } static const struct mtk_desc_pin * @@ -832,7 +848,8 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) if (pctl->devdata->spec_dir_set) pctl->devdata->spec_dir_set(®_addr, offset); - regmap_read(pctl->regmap1, reg_addr, &read_val); + regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), + reg_addr, &read_val); if (read_val & bit) return GPIO_LINE_DIRECTION_OUT; @@ -850,7 +867,8 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) pctl->devdata->din_offset; bit = BIT(offset & pctl->devdata->mode_mask); - regmap_read(pctl->regmap1, reg_addr, &read_val); + regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->din_multibase), + reg_addr, &read_val); return !!(read_val & bit); } @@ -1076,7 +1094,7 @@ int mtk_pctrl_init(struct platform_device *pdev, return dev_err_probe(dev, -EINVAL, "Cannot find pinctrl regmap.\n"); } - /* Only 8135 has two base addr, other SoCs have only one. */ + /* 6589 and 8135 has two base addr, other SoCs have only one. */ node = of_parse_phandle(np, "mediatek,pctl-regmap", 1); if (node) { pctl->regmap2 = syscon_node_to_regmap(node); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 11afa12a96cbc2..81793d2973f866 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -263,7 +263,6 @@ struct mtk_pinctrl_devdata { unsigned int smt_offset; unsigned int pullen_offset; unsigned int pullsel_offset; - unsigned int drv_offset; unsigned int dout_offset; unsigned int din_offset; unsigned int pinmux_offset; @@ -277,6 +276,15 @@ struct mtk_pinctrl_devdata { unsigned int mode_mask; unsigned int mode_per_reg; unsigned int mode_shf; + bool dir_multibase; + bool ies_multibase; + bool smt_multibase; + bool pullen_multibase; + bool pullsel_multibase; + bool drv_multibase; + bool dout_multibase; + bool din_multibase; + bool pinmux_multibase; }; struct mtk_pinctrl { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h new file mode 100644 index 00000000000000..116879d078fb02 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h @@ -0,0 +1,2336 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ + +#ifndef __PINCTRL_MTK_MT6589_H +#define __PINCTRL_MTK_MT6589_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6589[] = { + MTK_PIN(PINCTRL_PIN(0, "GPIO0"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 49), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(2, "EINT49"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "SPI1_MO"), + MTK_FUNCTION(7, "NALE") + ), + MTK_PIN(PINCTRL_PIN(1, "GPIO1"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 48), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "EINT48"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "SPI1_CSN"), + MTK_FUNCTION(7, "NCLE") + ), + MTK_PIN(PINCTRL_PIN(2, "GPIO2"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 47), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "EINT47"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "SPI1_CLK"), + MTK_FUNCTION(7, "NLD4") + ), + MTK_PIN(PINCTRL_PIN(3, "GPIO3"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 46), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "EINT46"), + MTK_FUNCTION(6, "LSCE1B_2X"), + MTK_FUNCTION(7, "NLD5") + ), + MTK_PIN(PINCTRL_PIN(4, "GPIO4"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 50), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "EINT50"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "SPI1_MI"), + MTK_FUNCTION(7, "NLD10") + ), + MTK_PIN(PINCTRL_PIN(5, "GPIO5"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 41), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "EINT41"), + MTK_FUNCTION(6, "LRSTB_2X"), + MTK_FUNCTION(7, "NRNB") + ), + MTK_PIN(PINCTRL_PIN(6, "GPIO6"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 40), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "EINT40"), + MTK_FUNCTION(6, "LPTE"), + MTK_FUNCTION(7, "NREB") + ), + MTK_PIN(PINCTRL_PIN(7, "GPIO7"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 45), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "EINT45"), + MTK_FUNCTION(6, "LSCE0B_2X"), + MTK_FUNCTION(7, "NLD7") + ), + MTK_PIN(PINCTRL_PIN(8, "GPIO8"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 44), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "EINT44"), + MTK_FUNCTION(6, "LSA0_2X"), + MTK_FUNCTION(7, "NLD14") + ), + MTK_PIN(PINCTRL_PIN(9, "GPIO9"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 43), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(2, "EINT43"), + MTK_FUNCTION(6, "LSCK_2X"), + MTK_FUNCTION(7, "NLD11") + ), + MTK_PIN(PINCTRL_PIN(10, "GPIO10"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 42), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(2, "EINT42"), + MTK_FUNCTION(6, "LSDA_2X") + ), + MTK_PIN(PINCTRL_PIN(11, "GPIO11"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 139), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "NCEB0"), + MTK_FUNCTION(2, "EINT139"), + MTK_FUNCTION(7, "TESTA_OUT4") + ), + MTK_PIN(PINCTRL_PIN(12, "GPIO12"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 140), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "NCEB1"), + MTK_FUNCTION(2, "EINT140"), + MTK_FUNCTION(4, "MD1_GPS_SYNC"), + MTK_FUNCTION(5, "MD2_GPS_SYNC"), + MTK_FUNCTION(6, "USB_DRVVBUS"), + MTK_FUNCTION(7, "TESTA_OUT5") + ), + MTK_PIN(PINCTRL_PIN(13, "GPIO13"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 141), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "EINT141"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[0]"), + MTK_FUNCTION(7, "TESTA_OUT6") + ), + MTK_PIN(PINCTRL_PIN(14, "GPIO14"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 142), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "NCLE"), + MTK_FUNCTION(2, "EINT142"), + MTK_FUNCTION(3, "DPI1_CK_1X"), + MTK_FUNCTION(4, "CM2PDN_1X"), + MTK_FUNCTION(6, "NALE"), + MTK_FUNCTION(7, "TESTA_OUT7") + ), + MTK_PIN(PINCTRL_PIN(15, "GPIO15"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 143), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "NALE"), + MTK_FUNCTION(2, "EINT143"), + MTK_FUNCTION(3, "DPI1_DE_1X"), + MTK_FUNCTION(4, "CM2MCLK_1X"), + MTK_FUNCTION(5, "IRDA_RXD"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "TESTA_OUT8") + ), + MTK_PIN(PINCTRL_PIN(16, "GPIO16"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 144), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "NREB"), + MTK_FUNCTION(2, "EINT144"), + MTK_FUNCTION(3, "DPI1_HSYNC_1X"), + MTK_FUNCTION(4, "CM2RST_1X"), + MTK_FUNCTION(5, "IRDA_TXD"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[1]"), + MTK_FUNCTION(7, "TESTA_OUT9") + ), + MTK_PIN(PINCTRL_PIN(17, "GPIO17"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 145), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "NWEB"), + MTK_FUNCTION(2, "EINT145"), + MTK_FUNCTION(3, "DPI1_VSYNC_1X"), + MTK_FUNCTION(4, "CM2PCLK_1X"), + MTK_FUNCTION(5, "IRDA_PDN"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[2]"), + MTK_FUNCTION(7, "TESTA_OUT10") + ), + MTK_PIN(PINCTRL_PIN(18, "GPIO18"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 146), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "NLD0"), + MTK_FUNCTION(2, "EINT146"), + MTK_FUNCTION(3, "DPI1_D_1X[0]"), + MTK_FUNCTION(4, "CM2DAT_1X[0]"), + MTK_FUNCTION(5, "I2SIN_CK"), + MTK_FUNCTION(6, "DAC_CK"), + MTK_FUNCTION(7, "TESTA_OUT11") + ), + MTK_PIN(PINCTRL_PIN(19, "GPIO19"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 147), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "NLD1"), + MTK_FUNCTION(2, "EINT147"), + MTK_FUNCTION(3, "DPI1_D_1X[1]"), + MTK_FUNCTION(4, "CM2DAT_1X[1]"), + MTK_FUNCTION(5, "I2SIN_WS"), + MTK_FUNCTION(6, "DAC_WS"), + MTK_FUNCTION(7, "TESTA_OUT12") + ), + MTK_PIN(PINCTRL_PIN(20, "GPIO20"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 148), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "NLD2"), + MTK_FUNCTION(2, "EINT148"), + MTK_FUNCTION(3, "DPI1_D_1X[2]"), + MTK_FUNCTION(4, "CM2DAT_1X[2]"), + MTK_FUNCTION(5, "I2SOUT_DAT"), + MTK_FUNCTION(6, "DAC_DAT_OUT"), + MTK_FUNCTION(7, "TESTA_OUT13") + ), + MTK_PIN(PINCTRL_PIN(21, "GPIO21"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 149), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "NLD3"), + MTK_FUNCTION(2, "EINT149"), + MTK_FUNCTION(3, "DPI1_D_1X[3]"), + MTK_FUNCTION(4, "CM2DAT_1X[3]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[3]"), + MTK_FUNCTION(7, "TESTA_OUT14") + ), + MTK_PIN(PINCTRL_PIN(22, "GPIO22"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 150), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "NLD4"), + MTK_FUNCTION(2, "EINT150"), + MTK_FUNCTION(3, "DPI1_D_1X[4]"), + MTK_FUNCTION(4, "CM2DAT_1X[4]"), + MTK_FUNCTION(5, "MD1_DAI_RX_GPIO"), + MTK_FUNCTION(6, "MD2_DAI_RX_GPIO"), + MTK_FUNCTION(7, "TESTA_OUT15") + ), + MTK_PIN(PINCTRL_PIN(23, "GPIO23"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 151), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "NLD5"), + MTK_FUNCTION(2, "EINT151"), + MTK_FUNCTION(3, "DPI1_D_1X[5]"), + MTK_FUNCTION(4, "CM2DAT_1X[5]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[4]"), + MTK_FUNCTION(7, "TESTA_OUT16") + ), + MTK_PIN(PINCTRL_PIN(24, "GPIO24"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 152), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "NLD6"), + MTK_FUNCTION(2, "EINT152"), + MTK_FUNCTION(3, "DPI1_D_1X[6]"), + MTK_FUNCTION(4, "CM2DAT_1X[6]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[5]"), + MTK_FUNCTION(7, "TESTA_OUT17") + ), + MTK_PIN(PINCTRL_PIN(25, "GPIO25"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 153), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "NLD7"), + MTK_FUNCTION(2, "EINT153"), + MTK_FUNCTION(3, "DPI1_D_1X[7]"), + MTK_FUNCTION(4, "CM2DAT_1X[7]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[6]"), + MTK_FUNCTION(7, "TESTA_OUT18") + ), + MTK_PIN(PINCTRL_PIN(26, "GPIO26"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 154), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "NLD8"), + MTK_FUNCTION(2, "EINT154"), + MTK_FUNCTION(3, "DPI1_D_1X[8]"), + MTK_FUNCTION(4, "CM2DAT_1X[8]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[7]"), + MTK_FUNCTION(7, "TESTA_OUT19") + ), + MTK_PIN(PINCTRL_PIN(27, "GPIO27"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 155), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "NLD9"), + MTK_FUNCTION(2, "EINT155"), + MTK_FUNCTION(3, "DPI1_D_1X[9]"), + MTK_FUNCTION(4, "CM2DAT_1X[9]"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[8]"), + MTK_FUNCTION(7, "TESTA_OUT20") + ), + MTK_PIN(PINCTRL_PIN(28, "GPIO28"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 156), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "NLD10"), + MTK_FUNCTION(2, "EINT156"), + MTK_FUNCTION(3, "DPI1_D_1X[10]"), + MTK_FUNCTION(4, "CM2VSYNC_1X"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[9]"), + MTK_FUNCTION(7, "TESTA_OUT21") + ), + MTK_PIN(PINCTRL_PIN(29, "GPIO29"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 157), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "NLD11"), + MTK_FUNCTION(2, "EINT157"), + MTK_FUNCTION(3, "DPI1_D_1X[11]"), + MTK_FUNCTION(4, "CM2HSYNC_1X"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[10]"), + MTK_FUNCTION(7, "TESTA_OUT22") + ), + MTK_PIN(PINCTRL_PIN(30, "GPIO30"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 158), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "NLD12"), + MTK_FUNCTION(2, "EINT158"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[11]"), + MTK_FUNCTION(7, "TESTA_OUT23") + ), + MTK_PIN(PINCTRL_PIN(31, "GPIO31"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 159), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "NLD13"), + MTK_FUNCTION(2, "EINT159"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[12]"), + MTK_FUNCTION(7, "TESTA_OUT24") + ), + MTK_PIN(PINCTRL_PIN(32, "GPIO32"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 160), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "NLD14"), + MTK_FUNCTION(2, "EINT160"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[13]"), + MTK_FUNCTION(7, "TESTA_OUT25") + ), + MTK_PIN(PINCTRL_PIN(33, "GPIO33"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 161), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "NLD15"), + MTK_FUNCTION(2, "EINT161"), + MTK_FUNCTION(3, "DISP_PWM"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[14]"), + MTK_FUNCTION(7, "TESTA_OUT26") + ), + MTK_PIN(PINCTRL_PIN(34, "GPIO34"), + NULL, "mt6589", + MTK_EINT_FUNCTION(6, 0), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "EINT0"), + MTK_FUNCTION(2, "PWM1"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(5, "MD2_UTXD"), + MTK_FUNCTION(6, "MD1_EINT1"), + MTK_FUNCTION(7, "USB_SCL") + ), + MTK_PIN(PINCTRL_PIN(35, "GPIO35"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 1), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "EINT1"), + MTK_FUNCTION(2, "PWM2"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(5, "MD2_URXD"), + MTK_FUNCTION(6, "MD1_EINT2"), + MTK_FUNCTION(7, "USB_SDA") + ), + MTK_PIN(PINCTRL_PIN(36, "GPIO36"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 2), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "EINT2"), + MTK_FUNCTION(2, "PWM3"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "SRCLKENAI2"), + MTK_FUNCTION(6, "MD1_EINT3") + ), + MTK_PIN(PINCTRL_PIN(37, "GPIO37"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 3), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "EINT3"), + MTK_FUNCTION(6, "MD1_EINT5"), + MTK_FUNCTION(7, "EXT_26M_CK") + ), + MTK_PIN(PINCTRL_PIN(38, "GPIO38"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 4), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "EINT4"), + MTK_FUNCTION(2, "PWM4"), + MTK_FUNCTION(3, "MD1_GPS_SYNC"), + MTK_FUNCTION(4, "MD2_GPS_SYNC"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "MD1_EINT4") + ), + MTK_PIN(PINCTRL_PIN(39, "GPIO39"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 29), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "PWRAP_SPIDI"), + MTK_FUNCTION(2, "EINT29") + ), + MTK_PIN(PINCTRL_PIN(40, "GPIO40"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 28), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "PWRAP_SPIDO"), + MTK_FUNCTION(2, "EINT28") + ), + MTK_PIN(PINCTRL_PIN(41, "GPIO41"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 27), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "PWRAP_SPICS_B_I"), + MTK_FUNCTION(2, "EINT27") + ), + MTK_PIN(PINCTRL_PIN(42, "GPIO42"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 26), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "PWRAP_SPICK_I"), + MTK_FUNCTION(2, "EINT26") + ), + MTK_PIN(PINCTRL_PIN(43, "GPIO43"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 25), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "PWRAP_EVENT_IN"), + MTK_FUNCTION(2, "EINT25") + ), + MTK_PIN(PINCTRL_PIN(44, "GPIO44"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 30), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "EINT30"), + MTK_FUNCTION(3, "MD1_SIM2_SCLK"), + MTK_FUNCTION(4, "MD2_SIM1_SCLK"), + MTK_FUNCTION(5, "MD2_SIM2_SCLK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[15]") + ), + MTK_PIN(PINCTRL_PIN(45, "GPIO45"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 31), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "EINT31"), + MTK_FUNCTION(3, "MD1_SIM2_SRST"), + MTK_FUNCTION(4, "MD2_SIM1_SRST"), + MTK_FUNCTION(5, "MD2_SIM2_SRST"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[16]") + ), + MTK_PIN(PINCTRL_PIN(46, "GPIO46"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 32), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD1_SIM1_SDAT"), + MTK_FUNCTION(2, "EINT32"), + MTK_FUNCTION(3, "MD1_SIM2_SDAT"), + MTK_FUNCTION(4, "MD2_SIM1_SDAT"), + MTK_FUNCTION(5, "MD2_SIM2_SDAT"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[17]") + ), + MTK_PIN(PINCTRL_PIN(47, "GPIO47"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 33), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "EINT33"), + MTK_FUNCTION(3, "MD1_SIM1_SCLK"), + MTK_FUNCTION(4, "MD2_SIM2_SCLK"), + MTK_FUNCTION(5, "MD2_SIM1_SCLK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[18]") + ), + MTK_PIN(PINCTRL_PIN(48, "GPIO48"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 34), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "EINT34"), + MTK_FUNCTION(3, "MD1_SIM1_SRST"), + MTK_FUNCTION(4, "MD2_SIM2_SRST"), + MTK_FUNCTION(5, "MD2_SIM1_SRST"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[19]") + ), + MTK_PIN(PINCTRL_PIN(49, "GPIO49"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 35), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "MD1_SIM2_SDAT"), + MTK_FUNCTION(2, "EINT35"), + MTK_FUNCTION(3, "MD1_SIM1_SDAT"), + MTK_FUNCTION(4, "MD2_SIM2_SDAT"), + MTK_FUNCTION(5, "MD2_SIM1_SDAT"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[20]") + ), + MTK_PIN(PINCTRL_PIN(50, "GPIO50"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "ADC_CK"), + MTK_FUNCTION(2, "EINT19") + ), + MTK_PIN(PINCTRL_PIN(51, "GPIO51"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "ADC_WS"), + MTK_FUNCTION(2, "EINT21") + ), + MTK_PIN(PINCTRL_PIN(52, "GPIO52"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "ADC_DAT_IN"), + MTK_FUNCTION(2, "EINT20") + ), + MTK_PIN(PINCTRL_PIN(53, "GPIO53"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "DAC_CK"), + MTK_FUNCTION(2, "EINT22") + ), + MTK_PIN(PINCTRL_PIN(54, "GPIO54"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "DAC_WS"), + MTK_FUNCTION(2, "EINT24") + ), + MTK_PIN(PINCTRL_PIN(55, "GPIO55"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "DAC_DAT_OUT"), + MTK_FUNCTION(2, "EINT23") + ), + MTK_PIN(PINCTRL_PIN(56, "GPIO56"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN(PINCTRL_PIN(57, "GPIO57"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 34), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "IDDIG"), + MTK_FUNCTION(2, "EINT34") + ), + MTK_PIN(PINCTRL_PIN(58, "GPIO58"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 36), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "WATCHDOG"), + MTK_FUNCTION(2, "EINT36") + ), + MTK_PIN(PINCTRL_PIN(59, "GPIO59"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 38), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SRCLKENA"), + MTK_FUNCTION(2, "EINT38") + ), + MTK_PIN(PINCTRL_PIN(60, "GPIO60"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 37), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SRCVOLTEN"), + MTK_FUNCTION(2, "EINT37") + ), + MTK_PIN(PINCTRL_PIN(61, "GPIO61"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 188), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "EINT188"), + MTK_FUNCTION(3, "DSP1_ICK"), + MTK_FUNCTION(7, "MD2_TCK_PAD") + ), + MTK_PIN(PINCTRL_PIN(62, "GPIO62"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 190), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "EINT190"), + MTK_FUNCTION(3, "DSP2_IMS"), + MTK_FUNCTION(7, "MD2_TDO_PAD") + ), + MTK_PIN(PINCTRL_PIN(63, "GPIO63"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "JTRST_B"), + MTK_FUNCTION(2, "EINT0"), + MTK_FUNCTION(3, "DSP2_ICK"), + MTK_FUNCTION(7, "MD2_NTRST_PAD") + ), + MTK_PIN(PINCTRL_PIN(64, "GPIO64"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 189), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "EINT189"), + MTK_FUNCTION(3, "DSP1_IMS"), + MTK_FUNCTION(7, "MD2_TDI_PAD") + ), + MTK_PIN(PINCTRL_PIN(65, "GPIO65"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 187), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "JRTCK"), + MTK_FUNCTION(2, "EINT187"), + MTK_FUNCTION(3, "DSP1_ID"), + MTK_FUNCTION(7, "MD2_RTCK_PAD") + ), + MTK_PIN(PINCTRL_PIN(66, "GPIO66"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 191), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "EINT191"), + MTK_FUNCTION(3, "DSP2_ID"), + MTK_FUNCTION(7, "MD2_TMS_PAD") + ), + MTK_PIN(PINCTRL_PIN(67, "GPIO67"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 97), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(2, "EINT97"), + MTK_FUNCTION(7, "A_FUNC_DIN[13]") + ), + MTK_PIN(PINCTRL_PIN(68, "GPIO68"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 96), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(2, "EINT96"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(7, "A_FUNC_DIN[14]") + ), + MTK_PIN(PINCTRL_PIN(69, "GPIO69"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 83), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "EINT83"), + MTK_FUNCTION(3, "BSI2_CLK"), + MTK_FUNCTION(4, "MD1_URXD"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "UTXD2"), + MTK_FUNCTION(7, "MD1_EINT4") + ), + MTK_PIN(PINCTRL_PIN(70, "GPIO70"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 82), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "EINT82"), + MTK_FUNCTION(3, "BSI2_CS"), + MTK_FUNCTION(4, "MD1_UTXD"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(6, "URXD2"), + MTK_FUNCTION(7, "MD1_EINT3") + ), + MTK_PIN(PINCTRL_PIN(71, "GPIO71"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 84), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "EINT84"), + MTK_FUNCTION(3, "BSI2_DATA0"), + MTK_FUNCTION(4, "MD2_UTXD"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "URTS2"), + MTK_FUNCTION(7, "MD2_EINT1") + ), + MTK_PIN(PINCTRL_PIN(72, "GPIO72"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 85), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "EINT85"), + MTK_FUNCTION(3, "BSI2_DATA1"), + MTK_FUNCTION(4, "MD2_URXD"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "UCTS2"), + MTK_FUNCTION(7, "MD2_EINT2") + ), + MTK_PIN(PINCTRL_PIN(73, "GPIO73"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 73), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT73"), + MTK_FUNCTION(3, "MD1_GPS_SYNC"), + MTK_FUNCTION(4, "MD2_GPS_SYNC"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "MD2_TCK_PAD") + ), + MTK_PIN(PINCTRL_PIN(74, "GPIO74"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 74), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT74"), + MTK_FUNCTION(3, "BPI2_BUS11"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "URXD2"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "MD2_RTCK_PAD") + ), + MTK_PIN(PINCTRL_PIN(75, "GPIO75"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 75), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT75"), + MTK_FUNCTION(3, "BPI2_BUS12"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "UTXD2"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "MD2_NTRST_PAD") + ), + MTK_PIN(PINCTRL_PIN(76, "GPIO76"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 76), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "PWM4"), + MTK_FUNCTION(2, "EINT76"), + MTK_FUNCTION(3, "BPI2_BUS13"), + MTK_FUNCTION(4, "PWM7"), + MTK_FUNCTION(6, "DISP_PWM"), + MTK_FUNCTION(7, "MD2_TMS_PAD") + ), + MTK_PIN(PINCTRL_PIN(77, "GPIO77"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 79), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "EINT79"), + MTK_FUNCTION(3, "URXD4"), + MTK_FUNCTION(4, "MD1_URXD"), + MTK_FUNCTION(5, "MD2_URXD"), + MTK_FUNCTION(6, "UTXD1"), + MTK_FUNCTION(7, "MD2_TDO_PAD") + ), + MTK_PIN(PINCTRL_PIN(78, "GPIO78"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 78), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "EINT78"), + MTK_FUNCTION(3, "UTXD4"), + MTK_FUNCTION(4, "MD1_UTXD"), + MTK_FUNCTION(5, "MD2_UTXD"), + MTK_FUNCTION(6, "URXD1"), + MTK_FUNCTION(7, "MD2_TDI_PAD") + ), + MTK_PIN(PINCTRL_PIN(79, "GPIO79"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 80), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(2, "EINT80"), + MTK_FUNCTION(3, "DUAL_BPI1_BUS14"), + MTK_FUNCTION(4, "MD1_UTXD"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(6, "URTS1"), + MTK_FUNCTION(7, "MD1_EINT1") + ), + MTK_PIN(PINCTRL_PIN(80, "GPIO80"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 81), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(2, "EINT81"), + MTK_FUNCTION(3, "DUAL_BPI1_BUS15"), + MTK_FUNCTION(4, "MD1_URXD"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "UCTS1"), + MTK_FUNCTION(7, "MD1_EINT2") + ), + MTK_PIN(PINCTRL_PIN(81, "GPIO81"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 89), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "URXD4"), + MTK_FUNCTION(2, "EINT89"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "MD1_URXD"), + MTK_FUNCTION(5, "MD2_URXD"), + MTK_FUNCTION(6, "UTXD4"), + MTK_FUNCTION(7, "MD2_EINT5") + ), + MTK_PIN(PINCTRL_PIN(82, "GPIO82"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 88), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "UTXD4"), + MTK_FUNCTION(2, "EINT88"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "MD1_UTXD"), + MTK_FUNCTION(5, "MD2_UTXD"), + MTK_FUNCTION(6, "URXD4"), + MTK_FUNCTION(7, "MD1_EINT5") + ), + MTK_PIN(PINCTRL_PIN(83, "GPIO83"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 1), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS0"), + MTK_FUNCTION(2, "EINT1"), + MTK_FUNCTION(3, "BPI2_BUS0"), + MTK_FUNCTION(5, "USB_TEST_IO[0]"), + MTK_FUNCTION(7, "A_FUNC_DIN[31]") + ), + MTK_PIN(PINCTRL_PIN(84, "GPIO84"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 2), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS1"), + MTK_FUNCTION(2, "EINT2"), + MTK_FUNCTION(3, "BPI2_BUS1"), + MTK_FUNCTION(5, "USB_TEST_IO[1]"), + MTK_FUNCTION(7, "A_FUNC_DIN[30]") + ), + MTK_PIN(PINCTRL_PIN(85, "GPIO85"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 3), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS2"), + MTK_FUNCTION(2, "EINT3"), + MTK_FUNCTION(3, "BPI2_BUS2"), + MTK_FUNCTION(5, "USB_TEST_IO[2]"), + MTK_FUNCTION(7, "A_FUNC_DIN[29]") + ), + MTK_PIN(PINCTRL_PIN(86, "GPIO86"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 4), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS3"), + MTK_FUNCTION(2, "EINT4"), + MTK_FUNCTION(3, "BPI2_BUS3"), + MTK_FUNCTION(5, "USB_TEST_IO[3]"), + MTK_FUNCTION(7, "A_FUNC_DIN[28]") + ), + MTK_PIN(PINCTRL_PIN(87, "GPIO87"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 5), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS4"), + MTK_FUNCTION(2, "EINT5"), + MTK_FUNCTION(3, "BPI2_BUS4"), + MTK_FUNCTION(5, "USB_TEST_IO[4]"), + MTK_FUNCTION(7, "A_FUNC_DIN[27]") + ), + MTK_PIN(PINCTRL_PIN(88, "GPIO88"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 6), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS5"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "BPI2_BUS5"), + MTK_FUNCTION(5, "USB_TEST_IO[5]"), + MTK_FUNCTION(7, "A_FUNC_DIN[26]") + ), + MTK_PIN(PINCTRL_PIN(89, "GPIO89"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 7), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS6"), + MTK_FUNCTION(2, "EINT7"), + MTK_FUNCTION(3, "BPI2_BUS6"), + MTK_FUNCTION(5, "USB_TEST_IO[6]"), + MTK_FUNCTION(7, "A_FUNC_DIN[25]") + ), + MTK_PIN(PINCTRL_PIN(90, "GPIO90"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 8), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS7"), + MTK_FUNCTION(2, "EINT8"), + MTK_FUNCTION(3, "MD1_GPS_SYNC"), + MTK_FUNCTION(4, "MD2_GPS_SYNC"), + MTK_FUNCTION(5, "USB_TEST_IO[7]"), + MTK_FUNCTION(6, "USB_DRVVBUS"), + MTK_FUNCTION(7, "A_FUNC_DIN[24]") + ), + MTK_PIN(PINCTRL_PIN(91, "GPIO91"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 9), + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS8"), + MTK_FUNCTION(2, "EINT9"), + MTK_FUNCTION(3, "DUAL_BPI1_BUS14"), + MTK_FUNCTION(5, "USB_TEST_IO[8]"), + MTK_FUNCTION(7, "A_FUNC_DIN[23]") + ), + MTK_PIN(PINCTRL_PIN(92, "GPIO92"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS9"), + MTK_FUNCTION(2, "EINT10"), + MTK_FUNCTION(3, "DUAL_BPI1_BUS15"), + MTK_FUNCTION(5, "USB_TEST_IO[9]"), + MTK_FUNCTION(7, "A_FUNC_DIN[22]") + ), + MTK_PIN(PINCTRL_PIN(93, "GPIO93"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS10"), + MTK_FUNCTION(2, "EINT11"), + MTK_FUNCTION(5, "USB_TEST_IO[10]"), + MTK_FUNCTION(7, "A_FUNC_DIN[21]") + ), + MTK_PIN(PINCTRL_PIN(94, "GPIO94"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS11"), + MTK_FUNCTION(3, "BPI2_BUS11"), + MTK_FUNCTION(5, "USB_TEST_IO[11]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[7]") + ), + MTK_PIN(PINCTRL_PIN(95, "GPIO95"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS12"), + MTK_FUNCTION(3, "BPI2_BUS12"), + MTK_FUNCTION(5, "USB_TEST_IO[12]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[6]") + ), + MTK_PIN(PINCTRL_PIN(96, "GPIO96"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS13"), + MTK_FUNCTION(3, "BPI2_BUS13"), + MTK_FUNCTION(5, "USB_TEST_IO[13]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[5]") + ), + MTK_PIN(PINCTRL_PIN(97, "GPIO97"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS14"), + MTK_FUNCTION(3, "BPI2_BUS16"), + MTK_FUNCTION(5, "USB_TEST_IO[14]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[4]") + ), + MTK_PIN(PINCTRL_PIN(98, "GPIO98"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS17"), + MTK_FUNCTION(2, "EINT16"), + MTK_FUNCTION(3, "BPI2_BUS17"), + MTK_FUNCTION(5, "USB_TEST_IO[15]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[3]") + ), + MTK_PIN(PINCTRL_PIN(99, "GPIO99"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "DUAL_BPI1_BUS15"), + MTK_FUNCTION(2, "EINT17"), + MTK_FUNCTION(3, "BPI2_BUS18"), + MTK_FUNCTION(5, "USB_TEST_IO[16]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[2]") + ), + MTK_PIN(PINCTRL_PIN(100, "GPIO100"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "VM1"), + MTK_FUNCTION(2, "EINT19"), + MTK_FUNCTION(5, "USB_TEST_IO[17]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[0]") + ), + MTK_PIN(PINCTRL_PIN(101, "GPIO101"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "VM0"), + MTK_FUNCTION(2, "EINT18"), + MTK_FUNCTION(5, "USB_TEST_IO[18]"), + MTK_FUNCTION(7, "A_FUNC_DOUT[1]") + ), + MTK_PIN(PINCTRL_PIN(102, "GPIO102"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 26), + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "BSI1B_CS0"), + MTK_FUNCTION(2, "EINT26"), + MTK_FUNCTION(5, "USB_TEST_IO[19]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[21]") + ), + MTK_PIN(PINCTRL_PIN(103, "GPIO103"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 27), + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "BSI1B_DATA0"), + MTK_FUNCTION(2, "EINT27"), + MTK_FUNCTION(5, "USB_TEST_IO[20]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[22]") + ), + MTK_PIN(PINCTRL_PIN(104, "GPIO104"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 25), + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "BSI1B_CLK"), + MTK_FUNCTION(2, "EINT25"), + MTK_FUNCTION(5, "USB_TEST_IO[21]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[23]") + ), + MTK_PIN(PINCTRL_PIN(105, "GPIO105"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 30), + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "TXBPI1"), + MTK_FUNCTION(2, "EINT30") + ), + MTK_PIN(PINCTRL_PIN(106, "GPIO106"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "EXT_CLK_EN") + ), + MTK_PIN(PINCTRL_PIN(107, "GPIO107"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 39), + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "SRCLKENA2"), + MTK_FUNCTION(2, "EINT39") + ), + MTK_PIN(PINCTRL_PIN(108, "GPIO108"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "BSI1A_CS0"), + MTK_FUNCTION(2, "EINT21"), + MTK_FUNCTION(3, "BSI2_CS"), + MTK_FUNCTION(5, "USB_TEST_IO[22]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[24]") + ), + MTK_PIN(PINCTRL_PIN(109, "GPIO109"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "BSI1A_DATA2"), + MTK_FUNCTION(2, "EINT24"), + MTK_FUNCTION(5, "USB_TEST_IO[23]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[25]") + ), + MTK_PIN(PINCTRL_PIN(110, "GPIO110"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "BSI1A_DATA1"), + MTK_FUNCTION(2, "EINT23"), + MTK_FUNCTION(3, "BSI2_DATA1"), + MTK_FUNCTION(5, "USB_TEST_IO[24]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[26]") + ), + MTK_PIN(PINCTRL_PIN(111, "GPIO111"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "BSI1A_DATA0"), + MTK_FUNCTION(2, "EINT22"), + MTK_FUNCTION(3, "BSI2_DATA0"), + MTK_FUNCTION(5, "USB_TEST_IO[25]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[27]") + ), + MTK_PIN(PINCTRL_PIN(112, "GPIO112"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "BSI1A_CLK"), + MTK_FUNCTION(2, "EINT20"), + MTK_FUNCTION(3, "BSI2_CLK"), + MTK_FUNCTION(5, "USB_TEST_IO[26]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[28]") + ), + MTK_PIN(PINCTRL_PIN(113, "GPIO113"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 29), + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "BSI1C_DATA"), + MTK_FUNCTION(2, "EINT29"), + MTK_FUNCTION(3, "MD1_GPS_SYNC"), + MTK_FUNCTION(4, "MD2_GPS_SYNC"), + MTK_FUNCTION(5, "USB_TEST_IO[27]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[29]"), + MTK_FUNCTION(7, "USB_DRVVBUS") + ), + MTK_PIN(PINCTRL_PIN(114, "GPIO114"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 28), + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "BSI1C_CLK"), + MTK_FUNCTION(2, "EINT28"), + MTK_FUNCTION(5, "USB_TEST_IO[28]"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[30]") + ), + MTK_PIN(PINCTRL_PIN(115, "GPIO115"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 10), + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "EINT10"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[31]") + ), + MTK_PIN(PINCTRL_PIN(116, "GPIO116"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 11), + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "EINT11"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[32]") + ), + MTK_PIN(PINCTRL_PIN(117, "GPIO117"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 16), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "EINT16"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[33]") + ), + MTK_PIN(PINCTRL_PIN(118, "GPIO118"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 91), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT91"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(7, "A_FUNC_DIN[19]") + ), + MTK_PIN(PINCTRL_PIN(119, "GPIO119"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 90), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT90"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(7, "A_FUNC_DIN[20]") + ), + MTK_PIN(PINCTRL_PIN(120, "GPIO120"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "I2SIN_CK"), + MTK_FUNCTION(2, "EINT10"), + MTK_FUNCTION(3, "DAC_CK"), + MTK_FUNCTION(4, "PCM1_CK"), + MTK_FUNCTION(5, "DSP1_ICK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[34]") + ), + MTK_PIN(PINCTRL_PIN(121, "GPIO121"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "I2SIN_WS"), + MTK_FUNCTION(3, "DAC_WS"), + MTK_FUNCTION(4, "PCM1_WS"), + MTK_FUNCTION(5, "DSP1_ID"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[35]") + ), + MTK_PIN(PINCTRL_PIN(122, "GPIO122"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "I2SIN_DAT"), + MTK_FUNCTION(2, "EINT11"), + MTK_FUNCTION(4, "PCM1_DI"), + MTK_FUNCTION(5, "DSP1_IMS"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[36]") + ), + MTK_PIN(PINCTRL_PIN(123, "GPIO123"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "I2SOUT_DAT"), + MTK_FUNCTION(3, "DAC_DAT_OUT"), + MTK_FUNCTION(4, "PCM1_DO"), + MTK_FUNCTION(5, "MD2_EINT5"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[37]") + ), + MTK_PIN(PINCTRL_PIN(124, "GPIO124"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 5), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "EINT5"), + MTK_FUNCTION(2, "PWM5"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "MD1_UTXD"), + MTK_FUNCTION(5, "MD2_EINT1"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[38]") + ), + MTK_PIN(PINCTRL_PIN(125, "GPIO125"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 6), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "EINT6"), + MTK_FUNCTION(2, "PWM6"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "MD1_URXD"), + MTK_FUNCTION(5, "MD2_EINT2"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[39]") + ), + MTK_PIN(PINCTRL_PIN(126, "GPIO126"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 7), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "EINT7"), + MTK_FUNCTION(2, "PWM7"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "SRCLKENAI2"), + MTK_FUNCTION(5, "MD2_EINT3"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[40]") + ), + MTK_PIN(PINCTRL_PIN(127, "GPIO127"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 8), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "EINT8"), + MTK_FUNCTION(2, "DISP_PWM"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(5, "MD2_EINT4"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[41]"), + MTK_FUNCTION(7, "EXT_FRAME_SYNC") + ), + MTK_PIN(PINCTRL_PIN(128, "GPIO128"), + NULL, "mt6589", + MTK_EINT_FUNCTION(1, 9), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "EINT9"), + MTK_FUNCTION(3, "MD1_GPS_SYNC"), + MTK_FUNCTION(4, "MD2_GPS_SYNC"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[42]") + ), + MTK_PIN(PINCTRL_PIN(129, "GPIO129"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 77), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "EINT77"), + MTK_FUNCTION(3, "LSDI"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[43]"), + MTK_FUNCTION(7, "PWM3") + ), + MTK_PIN(PINCTRL_PIN(130, "GPIO130"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 133), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "MSDC4_DAT0"), + MTK_FUNCTION(2, "EINT133"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "USB_DRVVBUS"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[46]"), + MTK_FUNCTION(7, "LPTE") + ), + MTK_PIN(PINCTRL_PIN(131, "GPIO131"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 134), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "MSDC4_DAT1"), + MTK_FUNCTION(2, "EINT134"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[47]"), + MTK_FUNCTION(7, "LRSTB_1X") + ), + MTK_PIN(PINCTRL_PIN(132, "GPIO132"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 127), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "LPCE1B"), + MTK_FUNCTION(2, "EINT127"), + MTK_FUNCTION(3, "DPI1_HSYNC_2X"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[44]") + ), + MTK_PIN(PINCTRL_PIN(133, "GPIO133"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 126), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "LPCE0B"), + MTK_FUNCTION(2, "EINT126"), + MTK_FUNCTION(3, "DPI1_VSYNC_2X"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[45]") + ), + MTK_PIN(PINCTRL_PIN(134, "GPIO134"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 136), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "MSDC4_DAT5"), + MTK_FUNCTION(2, "EINT136"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[48]"), + MTK_FUNCTION(7, "SPI1_CSN") + ), + MTK_PIN(PINCTRL_PIN(135, "GPIO135"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 137), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "MSDC4_DAT6"), + MTK_FUNCTION(2, "EINT137"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[49]"), + MTK_FUNCTION(7, "SPI1_MO") + ), + MTK_PIN(PINCTRL_PIN(136, "GPIO136"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 138), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "MSDC4_DAT7"), + MTK_FUNCTION(2, "EINT138"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[50]"), + MTK_FUNCTION(7, "SPI1_MI") + ), + MTK_PIN(PINCTRL_PIN(137, "GPIO137"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 135), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "MSDC4_DAT4"), + MTK_FUNCTION(2, "EINT135"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[51]"), + MTK_FUNCTION(7, "SPI1_CLK") + ), + MTK_PIN(PINCTRL_PIN(138, "GPIO138"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 131), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "MSDC4_DAT2"), + MTK_FUNCTION(2, "EINT131"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "CM2PDN_2X"), + MTK_FUNCTION(5, "DAC_WS"), + MTK_FUNCTION(6, "PCM1_WS"), + MTK_FUNCTION(7, "LSCE0B_1X") + ), + MTK_PIN(PINCTRL_PIN(139, "GPIO139"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 129), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "MSDC4_CLK"), + MTK_FUNCTION(2, "EINT129"), + MTK_FUNCTION(3, "DPI1_CK_2X"), + MTK_FUNCTION(4, "CM2PCLK_2X"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "PCM1_DI"), + MTK_FUNCTION(7, "LSCK_1X") + ), + MTK_PIN(PINCTRL_PIN(140, "GPIO140"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 132), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "MSDC4_DAT3"), + MTK_FUNCTION(2, "EINT132"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "CM2RST_2X"), + MTK_FUNCTION(5, "DAC_DAT_OUT"), + MTK_FUNCTION(6, "PCM1_DO"), + MTK_FUNCTION(7, "LSCE1B_1X") + ), + MTK_PIN(PINCTRL_PIN(141, "GPIO141"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 128), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "MSDC4_CMD"), + MTK_FUNCTION(2, "EINT128"), + MTK_FUNCTION(3, "DPI1_DE_2X"), + MTK_FUNCTION(4, "MD1_GPS_SYNC"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "MD2_GPS_SYNC"), + MTK_FUNCTION(7, "LSDA_1X") + ), + MTK_PIN(PINCTRL_PIN(142, "GPIO142"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 130), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "MSDC4_RSTB"), + MTK_FUNCTION(2, "EINT130"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "CM2MCLK_2X"), + MTK_FUNCTION(5, "DAC_CK"), + MTK_FUNCTION(6, "PCM1_CK"), + MTK_FUNCTION(7, "LSA0_1X") + ), + MTK_PIN(PINCTRL_PIN(143, "GPIO143"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 98), + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "DPI0_VSYNC"), + MTK_FUNCTION(2, "EINT98"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "DAC_CK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[52]"), + MTK_FUNCTION(7, "TESTB_OUT8") + ), + MTK_PIN(PINCTRL_PIN(144, "GPIO144"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 99), + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "DPI0_HSYNC"), + MTK_FUNCTION(2, "EINT99"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "DAC_WS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(6, "IRDA_RXD"), + MTK_FUNCTION(7, "TESTB_OUT9") + ), + MTK_PIN(PINCTRL_PIN(145, "GPIO145"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 100), + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "DPI0_DE"), + MTK_FUNCTION(2, "EINT100"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "DAC_DAT_OUT"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(6, "IRDA_TXD"), + MTK_FUNCTION(7, "TESTB_OUT10") + ), + MTK_PIN(PINCTRL_PIN(146, "GPIO146"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 101), + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "DPI0_CK"), + MTK_FUNCTION(2, "EINT101"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(6, "IRDA_PDN"), + MTK_FUNCTION(7, "TESTB_OUT11") + ), + MTK_PIN(PINCTRL_PIN(147, "GPIO147"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 102), + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "DPI0_B0"), + MTK_FUNCTION(2, "EINT102"), + MTK_FUNCTION(4, "SCL0"), + MTK_FUNCTION(5, "DISP_PWM"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[57]"), + MTK_FUNCTION(7, "TESTB_OUT12") + ), + MTK_PIN(PINCTRL_PIN(148, "GPIO148"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 103), + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "DPI0_B1"), + MTK_FUNCTION(2, "EINT103"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "SDA0"), + MTK_FUNCTION(5, "PWM1"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[58]"), + MTK_FUNCTION(7, "TESTB_OUT13") + ), + MTK_PIN(PINCTRL_PIN(149, "GPIO149"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 104), + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "DPI0_B2"), + MTK_FUNCTION(2, "EINT104"), + MTK_FUNCTION(3, "CLKM1"), + MTK_FUNCTION(4, "SCL1"), + MTK_FUNCTION(5, "PWM2"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[59]"), + MTK_FUNCTION(7, "TESTB_OUT14") + ), + MTK_PIN(PINCTRL_PIN(150, "GPIO150"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 105), + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "DPI0_B3"), + MTK_FUNCTION(2, "EINT105"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "SDA1"), + MTK_FUNCTION(5, "PWM3"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[60]"), + MTK_FUNCTION(7, "TESTB_OUT15") + ), + MTK_PIN(PINCTRL_PIN(151, "GPIO151"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 106), + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "DPI0_B4"), + MTK_FUNCTION(2, "EINT106"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "SCL2"), + MTK_FUNCTION(5, "PWM4"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[61]"), + MTK_FUNCTION(7, "TESTB_OUT16") + ), + MTK_PIN(PINCTRL_PIN(152, "GPIO152"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 107), + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "DPI0_B5"), + MTK_FUNCTION(2, "EINT107"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "SDA2"), + MTK_FUNCTION(5, "PWM5"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[62]"), + MTK_FUNCTION(7, "TESTB_OUT17") + ), + MTK_PIN(PINCTRL_PIN(153, "GPIO153"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 108), + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "DPI0_B6"), + MTK_FUNCTION(2, "EINT108"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "SCL3"), + MTK_FUNCTION(5, "PWM6"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[63]"), + MTK_FUNCTION(7, "TESTB_OUT18") + ), + MTK_PIN(PINCTRL_PIN(154, "GPIO154"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 109), + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "DPI0_B7"), + MTK_FUNCTION(2, "EINT109"), + MTK_FUNCTION(3, "CLKM6"), + MTK_FUNCTION(4, "SDA3"), + MTK_FUNCTION(5, "PWM7"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[0]"), + MTK_FUNCTION(7, "TESTB_OUT19") + ), + MTK_PIN(PINCTRL_PIN(155, "GPIO155"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 110), + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "DPI0_G0"), + MTK_FUNCTION(2, "EINT110"), + MTK_FUNCTION(5, "DSP1_ID"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[1]"), + MTK_FUNCTION(7, "TESTB_OUT20") + ), + MTK_PIN(PINCTRL_PIN(156, "GPIO156"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 111), + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "DPI0_G1"), + MTK_FUNCTION(2, "EINT111"), + MTK_FUNCTION(5, "DSP1_ICK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[56]"), + MTK_FUNCTION(7, "TESTB_OUT21") + ), + MTK_PIN(PINCTRL_PIN(157, "GPIO157"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 112), + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "DPI0_G2"), + MTK_FUNCTION(2, "EINT112"), + MTK_FUNCTION(5, "DSP1_IMS"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[2]"), + MTK_FUNCTION(7, "TESTB_OUT22") + ), + MTK_PIN(PINCTRL_PIN(158, "GPIO158"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 113), + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "DPI0_G3"), + MTK_FUNCTION(2, "EINT113"), + MTK_FUNCTION(5, "DSP2_IMS"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[3]"), + MTK_FUNCTION(7, "TESTB_OUT23") + ), + MTK_PIN(PINCTRL_PIN(159, "GPIO159"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 114), + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "DPI0_G4"), + MTK_FUNCTION(2, "EINT114"), + MTK_FUNCTION(3, "DPI1_D_2X[0]"), + MTK_FUNCTION(4, "CM2DAT_2X[0]"), + MTK_FUNCTION(5, "DSP2_ID"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[53]"), + MTK_FUNCTION(7, "TESTB_OUT24") + ), + MTK_PIN(PINCTRL_PIN(160, "GPIO160"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 115), + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "DPI0_G5"), + MTK_FUNCTION(2, "EINT115"), + MTK_FUNCTION(3, "DPI1_D_2X[1]"), + MTK_FUNCTION(4, "CM2DAT_2X[1]"), + MTK_FUNCTION(5, "DSP2_ICK"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[54]"), + MTK_FUNCTION(7, "TESTB_OUT25") + ), + MTK_PIN(PINCTRL_PIN(161, "GPIO161"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 116), + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "DPI0_G6"), + MTK_FUNCTION(2, "EINT116"), + MTK_FUNCTION(3, "DPI1_D_2X[2]"), + MTK_FUNCTION(4, "CM2DAT_2X[2]"), + MTK_FUNCTION(5, "MD2_RTCK_PAD"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[4]"), + MTK_FUNCTION(7, "TESTB_OUT26") + ), + MTK_PIN(PINCTRL_PIN(162, "GPIO162"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 117), + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "DPI0_G7"), + MTK_FUNCTION(2, "EINT117"), + MTK_FUNCTION(3, "DPI1_D_2X[3]"), + MTK_FUNCTION(4, "CM2DAT_2X[3]"), + MTK_FUNCTION(5, "MD2_TCK_PAD"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[5]"), + MTK_FUNCTION(7, "TESTB_OUT27") + ), + MTK_PIN(PINCTRL_PIN(163, "GPIO163"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 118), + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "DPI0_R0"), + MTK_FUNCTION(2, "EINT118"), + MTK_FUNCTION(3, "DPI1_D_2X[4]"), + MTK_FUNCTION(4, "CM2DAT_2X[4]"), + MTK_FUNCTION(5, "MD2_TDI_PAD"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[6]"), + MTK_FUNCTION(7, "TESTB_OUT28") + ), + MTK_PIN(PINCTRL_PIN(164, "GPIO164"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 119), + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "DPI0_R1"), + MTK_FUNCTION(2, "EINT119"), + MTK_FUNCTION(3, "DPI1_D_2X[5]"), + MTK_FUNCTION(4, "CM2DAT_2X[5]"), + MTK_FUNCTION(5, "MD2_TDO_PAD"), + MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[7]"), + MTK_FUNCTION(7, "TESTB_OUT29") + ), + MTK_PIN(PINCTRL_PIN(165, "GPIO165"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 120), + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "DPI0_R2"), + MTK_FUNCTION(2, "EINT120"), + MTK_FUNCTION(3, "DPI1_D_2X[6]"), + MTK_FUNCTION(4, "CM2DAT_2X[6]"), + MTK_FUNCTION(5, "MD2_TMS_PAD"), + MTK_FUNCTION(7, "TESTB_OUT30") + ), + MTK_PIN(PINCTRL_PIN(166, "GPIO166"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 121), + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "DPI0_R3"), + MTK_FUNCTION(2, "EINT121"), + MTK_FUNCTION(3, "DPI1_D_2X[7]"), + MTK_FUNCTION(4, "CM2DAT_2X[7]"), + MTK_FUNCTION(5, "MD2_NTRST_PAD"), + MTK_FUNCTION(6, "MD_ABB_AFUNC_D[55]"), + MTK_FUNCTION(7, "TESTB_OUT31") + ), + MTK_PIN(PINCTRL_PIN(167, "GPIO167"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 122), + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "DPI0_R4"), + MTK_FUNCTION(2, "EINT122"), + MTK_FUNCTION(3, "DPI1_D_2X[8]"), + MTK_FUNCTION(4, "CM2DAT_2X[8]"), + MTK_FUNCTION(7, "TESTA_OUT0") + ), + MTK_PIN(PINCTRL_PIN(168, "GPIO168"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 123), + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "DPI0_R5"), + MTK_FUNCTION(2, "EINT123"), + MTK_FUNCTION(3, "DPI1_D_2X[9]"), + MTK_FUNCTION(4, "CM2DAT_2X[9]"), + MTK_FUNCTION(5, "MD1_DAI_RX_GPIO"), + MTK_FUNCTION(6, "MD2_DAI_RX_GPIO"), + MTK_FUNCTION(7, "TESTA_OUT1") + ), + MTK_PIN(PINCTRL_PIN(169, "GPIO169"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 124), + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "DPI0_R6"), + MTK_FUNCTION(2, "EINT124"), + MTK_FUNCTION(3, "DPI1_D_2X[10]"), + MTK_FUNCTION(4, "CM2VSYNC_2X"), + MTK_FUNCTION(7, "TESTA_OUT2") + ), + MTK_PIN(PINCTRL_PIN(170, "GPIO170"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 125), + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "DPI0_R7"), + MTK_FUNCTION(2, "EINT125"), + MTK_FUNCTION(3, "DPI1_D_2X[11]"), + MTK_FUNCTION(4, "CM2HSYNC_2X"), + MTK_FUNCTION(7, "TESTA_OUT3") + ), + MTK_PIN(PINCTRL_PIN(171, "GPIO171"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 57), + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "MSDC1_INSI"), + MTK_FUNCTION(2, "EINT57"), + MTK_FUNCTION(3, "SCL5"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[0]"), + MTK_FUNCTION(7, "TESTB_OUT6") + ), + MTK_PIN(PINCTRL_PIN(172, "GPIO172"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 65), + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "MSDC2_INSI"), + MTK_FUNCTION(2, "EINT65"), + MTK_FUNCTION(3, "BPI2_BUS6"), + MTK_FUNCTION(7, "A_FUNC_DIN[6]") + ), + MTK_PIN(PINCTRL_PIN(173, "GPIO173"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 66), + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "MSDC2_SDWPI"), + MTK_FUNCTION(2, "EINT66"), + MTK_FUNCTION(3, "BPI2_BUS17"), + MTK_FUNCTION(4, "DUAL_BPI1_BUS14"), + MTK_FUNCTION(5, "DUAL_BPI1_BUS15"), + MTK_FUNCTION(7, "A_FUNC_DIN[5]") + ), + MTK_PIN(PINCTRL_PIN(174, "GPIO174"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 63), + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "EINT63"), + MTK_FUNCTION(3, "BPI2_BUS4"), + MTK_FUNCTION(4, "DSP2_IMS"), + MTK_FUNCTION(7, "A_FUNC_DIN[8]") + ), + MTK_PIN(PINCTRL_PIN(175, "GPIO175"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 64), + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "EINT64"), + MTK_FUNCTION(3, "BPI2_BUS5"), + MTK_FUNCTION(4, "DSP2_ID"), + MTK_FUNCTION(7, "A_FUNC_DIN[7]") + ), + MTK_PIN(PINCTRL_PIN(176, "GPIO176"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 60), + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "EINT60"), + MTK_FUNCTION(3, "BPI2_BUS1"), + MTK_FUNCTION(4, "DSP1_IMS"), + MTK_FUNCTION(5, "PCM1_WS"), + MTK_FUNCTION(7, "A_FUNC_DIN[11]") + ), + MTK_PIN(PINCTRL_PIN(177, "GPIO177"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 59), + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "EINT59"), + MTK_FUNCTION(3, "BPI2_BUS0"), + MTK_FUNCTION(4, "DSP1_ICK"), + MTK_FUNCTION(5, "PCM1_CK"), + MTK_FUNCTION(7, "A_FUNC_DIN[12]") + ), + MTK_PIN(PINCTRL_PIN(178, "GPIO178"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 62), + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "EINT62"), + MTK_FUNCTION(3, "BPI2_BUS3"), + MTK_FUNCTION(4, "DSP2_ICK"), + MTK_FUNCTION(5, "PCM1_DO"), + MTK_FUNCTION(7, "A_FUNC_DIN[9]") + ), + MTK_PIN(PINCTRL_PIN(179, "GPIO179"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 61), + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "EINT61"), + MTK_FUNCTION(3, "BPI2_BUS2"), + MTK_FUNCTION(4, "DSP1_ID"), + MTK_FUNCTION(5, "PCM1_DI"), + MTK_FUNCTION(7, "A_FUNC_DIN[10]") + ), + MTK_PIN(PINCTRL_PIN(180, "GPIO180"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 53), + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "EINT53"), + MTK_FUNCTION(3, "SCL1"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[1]"), + MTK_FUNCTION(7, "TESTB_OUT2") + ), + MTK_PIN(PINCTRL_PIN(181, "GPIO181"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 54), + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "EINT54"), + MTK_FUNCTION(3, "SDA1"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[2]"), + MTK_FUNCTION(7, "TESTB_OUT3") + ), + MTK_PIN(PINCTRL_PIN(182, "GPIO182"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 58), + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "MSDC1_SDWPI"), + MTK_FUNCTION(2, "EINT58"), + MTK_FUNCTION(3, "SDA5"), + MTK_FUNCTION(4, "PWM7"), + MTK_FUNCTION(5, "CLKM6"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[3]"), + MTK_FUNCTION(7, "TESTB_OUT7") + ), + MTK_PIN(PINCTRL_PIN(183, "GPIO183"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 52), + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "EINT52"), + MTK_FUNCTION(3, "SDA0"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[4]"), + MTK_FUNCTION(7, "TESTB_OUT1") + ), + MTK_PIN(PINCTRL_PIN(184, "GPIO184"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 51), + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "EINT51"), + MTK_FUNCTION(3, "SCL0"), + MTK_FUNCTION(4, "DISP_PWM"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[5]"), + MTK_FUNCTION(7, "TESTB_OUT0") + ), + MTK_PIN(PINCTRL_PIN(185, "GPIO185"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 55), + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "EINT55"), + MTK_FUNCTION(3, "SCL4"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[6]"), + MTK_FUNCTION(7, "TESTB_OUT4") + ), + MTK_PIN(PINCTRL_PIN(186, "GPIO186"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 56), + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "EINT56"), + MTK_FUNCTION(3, "SDA4"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "CLKM4"), + MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[7]"), + MTK_FUNCTION(7, "TESTB_OUT5") + ), + MTK_PIN(PINCTRL_PIN(187, "GPIO187"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 36), + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(2, "EINT36") + ), + MTK_PIN(PINCTRL_PIN(188, "GPIO188"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 35), + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(2, "EINT35") + ), + MTK_PIN(PINCTRL_PIN(189, "GPIO189"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 169), + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(2, "EINT169") + ), + MTK_PIN(PINCTRL_PIN(190, "GPIO190"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 168), + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(2, "EINT168") + ), + MTK_PIN(PINCTRL_PIN(191, "GPIO191"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 163), + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(2, "EINT163") + ), + MTK_PIN(PINCTRL_PIN(192, "GPIO192"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 162), + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(2, "EINT162") + ), + MTK_PIN(PINCTRL_PIN(193, "GPIO193"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 167), + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(2, "EINT167") + ), + MTK_PIN(PINCTRL_PIN(194, "GPIO194"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 166), + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(2, "EINT166") + ), + MTK_PIN(PINCTRL_PIN(195, "GPIO195"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 165), + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(2, "EINT165") + ), + MTK_PIN(PINCTRL_PIN(196, "GPIO196"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 164), + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(2, "EINT164") + ), + MTK_PIN(PINCTRL_PIN(197, "GPIO197"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 175), + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "CMDAT6"), + MTK_FUNCTION(2, "EINT175") + ), + MTK_PIN(PINCTRL_PIN(198, "GPIO198"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 174), + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "CMDAT7"), + MTK_FUNCTION(2, "EINT174") + ), + MTK_PIN(PINCTRL_PIN(199, "GPIO199"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 171), + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "CMDAT8"), + MTK_FUNCTION(2, "EINT171") + ), + MTK_PIN(PINCTRL_PIN(200, "GPIO200"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 170), + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "CMDAT9"), + MTK_FUNCTION(2, "EINT170") + ), + MTK_PIN(PINCTRL_PIN(201, "GPIO201"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 173), + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "CMHSYNC"), + MTK_FUNCTION(2, "EINT173") + ), + MTK_PIN(PINCTRL_PIN(202, "GPIO202"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 172), + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "CMVSYNC"), + MTK_FUNCTION(2, "EINT172") + ), + MTK_PIN(PINCTRL_PIN(203, "GPIO203"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 181), + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "CMDAT2"), + MTK_FUNCTION(2, "EINT181"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN(PINCTRL_PIN(204, "GPIO204"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 180), + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "CMDAT3"), + MTK_FUNCTION(2, "EINT180"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN(PINCTRL_PIN(205, "GPIO205"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 177), + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "CMDAT4"), + MTK_FUNCTION(2, "EINT177") + ), + MTK_PIN(PINCTRL_PIN(206, "GPIO206"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 176), + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "CMDAT5"), + MTK_FUNCTION(2, "EINT176") + ), + MTK_PIN(PINCTRL_PIN(207, "GPIO207"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 179), + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "EINT179"), + MTK_FUNCTION(3, "CMCSD0") + ), + MTK_PIN(PINCTRL_PIN(208, "GPIO208"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 178), + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "EINT178"), + MTK_FUNCTION(3, "CMCSD1") + ), + MTK_PIN(PINCTRL_PIN(209, "GPIO209"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 182), + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "EINT182"), + MTK_FUNCTION(3, "CMCSK"), + MTK_FUNCTION(4, "CM2MCLK_4X"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"), + MTK_FUNCTION(7, "TESTA_OUT27") + ), + MTK_PIN(PINCTRL_PIN(210, "GPIO210"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 183), + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(2, "EINT183"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"), + MTK_FUNCTION(7, "TESTA_OUT28") + ), + MTK_PIN(PINCTRL_PIN(211, "GPIO211"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 185), + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "CMRST"), + MTK_FUNCTION(2, "EINT185"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"), + MTK_FUNCTION(7, "TESTA_OUT30") + ), + MTK_PIN(PINCTRL_PIN(212, "GPIO212"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 184), + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "CMPDN"), + MTK_FUNCTION(2, "EINT184"), + MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"), + MTK_FUNCTION(7, "TESTA_OUT29") + ), + MTK_PIN(PINCTRL_PIN(213, "GPIO213"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 186), + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "CMFLASH"), + MTK_FUNCTION(2, "EINT186"), + MTK_FUNCTION(3, "CM2MCLK_3X"), + MTK_FUNCTION(7, "TESTA_OUT31") + ), + MTK_PIN(PINCTRL_PIN(214, "GPIO214"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 93), + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT93"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB"), + MTK_FUNCTION(7, "A_FUNC_DIN[17]") + ), + MTK_PIN(PINCTRL_PIN(215, "GPIO215"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 92), + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT92"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "TS_AUX_DIN"), + MTK_FUNCTION(7, "A_FUNC_DIN[18]") + ), + MTK_PIN(PINCTRL_PIN(216, "GPIO216"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 95), + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT95"), + MTK_FUNCTION(3, "CLKM5"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "TS_AUX_PWDB"), + MTK_FUNCTION(7, "A_FUNC_DIN[15]") + ), + MTK_PIN(PINCTRL_PIN(217, "GPIO217"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 94), + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT94"), + MTK_FUNCTION(3, "CLKM4"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "TS_AUXADC_TEST_CK"), + MTK_FUNCTION(7, "A_FUNC_DIN[16]") + ), + MTK_PIN(PINCTRL_PIN(218, "GPIO218"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "SRCLKENAI") + ), + MTK_PIN(PINCTRL_PIN(219, "GPIO219"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 87), + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "URXD3"), + MTK_FUNCTION(2, "EINT87"), + MTK_FUNCTION(3, "UTXD3"), + MTK_FUNCTION(4, "MD2_URXD"), + MTK_FUNCTION(5, "TS_AUX_ST"), + MTK_FUNCTION(6, "PWM4"), + MTK_FUNCTION(7, "MD2_EINT4") + ), + MTK_PIN(PINCTRL_PIN(220, "GPIO220"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 86), + MTK_FUNCTION(0, "GPIO220"), + MTK_FUNCTION(1, "UTXD3"), + MTK_FUNCTION(2, "EINT86"), + MTK_FUNCTION(3, "URXD3"), + MTK_FUNCTION(4, "MD2_UTXD"), + MTK_FUNCTION(5, "TS_AUX_CS_B"), + MTK_FUNCTION(6, "PWM3"), + MTK_FUNCTION(7, "MD2_EINT3") + ), + MTK_PIN(PINCTRL_PIN(221, "GPIO221"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO221"), + MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"), + MTK_FUNCTION(3, "I2SIN_CK"), + MTK_FUNCTION(4, "PCM0_CK"), + MTK_FUNCTION(5, "DSP2_ICK"), + MTK_FUNCTION(6, "IMG_TEST_CK"), + MTK_FUNCTION(7, "USB_SCL") + ), + MTK_PIN(PINCTRL_PIN(222, "GPIO222"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO222"), + MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"), + MTK_FUNCTION(2, "EINT16"), + MTK_FUNCTION(3, "I2SIN_WS"), + MTK_FUNCTION(4, "PCM0_WS"), + MTK_FUNCTION(6, "DISP_TEST_CK") + ), + MTK_PIN(PINCTRL_PIN(223, "GPIO223"), + NULL, "mt6589", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO223"), + MTK_FUNCTION(1, "MRG_I2S_PCM_RX"), + MTK_FUNCTION(3, "I2SIN_DAT"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "DSP2_ID"), + MTK_FUNCTION(6, "MFG_TEST_CK"), + MTK_FUNCTION(7, "USB_SDA") + ), + MTK_PIN(PINCTRL_PIN(224, "GPIO224"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO224"), + MTK_FUNCTION(1, "MRG_I2S_PCM_TX"), + MTK_FUNCTION(2, "EINT17"), + MTK_FUNCTION(3, "I2SOUT_DAT"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(6, "VDEC_TEST_CK") + ), + MTK_PIN(PINCTRL_PIN(225, "GPIO225"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO225"), + MTK_FUNCTION(1, "MD1_DAI_RX_GPIO"), + MTK_FUNCTION(2, "EINT18"), + MTK_FUNCTION(3, "BT_SYNC"), + MTK_FUNCTION(4, "MD2_DAI_RX_GPIO"), + MTK_FUNCTION(5, "DSP2_IMS"), + MTK_FUNCTION(6, "VENC_TEST_CK") + ), + MTK_PIN(PINCTRL_PIN(226, "GPIO226"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 71), + MTK_FUNCTION(0, "GPIO226"), + MTK_FUNCTION(1, "MSDC3_DAT2"), + MTK_FUNCTION(2, "EINT71"), + MTK_FUNCTION(3, "SCL6"), + MTK_FUNCTION(4, "PWM5"), + MTK_FUNCTION(5, "CLKM4"), + MTK_FUNCTION(7, "A_FUNC_DIN[0]") + ), + MTK_PIN(PINCTRL_PIN(227, "GPIO227"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 72), + MTK_FUNCTION(0, "GPIO227"), + MTK_FUNCTION(1, "MSDC3_DAT3"), + MTK_FUNCTION(2, "EINT72"), + MTK_FUNCTION(3, "SDA6"), + MTK_FUNCTION(4, "PWM6"), + MTK_FUNCTION(5, "CLKM5"), + MTK_FUNCTION(7, "A_FUNC_CK") + ), + MTK_PIN(PINCTRL_PIN(228, "GPIO228"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 68), + MTK_FUNCTION(0, "GPIO228"), + MTK_FUNCTION(1, "MSDC3_CMD"), + MTK_FUNCTION(2, "EINT68"), + MTK_FUNCTION(3, "SDA2"), + MTK_FUNCTION(4, "PWM2"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(7, "A_FUNC_DIN[3]") + ), + MTK_PIN(PINCTRL_PIN(229, "GPIO229"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 67), + MTK_FUNCTION(0, "GPIO229"), + MTK_FUNCTION(1, "MSDC3_CLK"), + MTK_FUNCTION(2, "EINT67"), + MTK_FUNCTION(3, "SCL2"), + MTK_FUNCTION(4, "PWM1"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "A_FUNC_DIN[4]") + ), + MTK_PIN(PINCTRL_PIN(230, "GPIO230"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 70), + MTK_FUNCTION(0, "GPIO230"), + MTK_FUNCTION(1, "MSDC3_DAT1"), + MTK_FUNCTION(2, "EINT70"), + MTK_FUNCTION(3, "SDA3"), + MTK_FUNCTION(4, "PWM4"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(7, "A_FUNC_DIN[1]") + ), + MTK_PIN(PINCTRL_PIN(231, "GPIO231"), + NULL, "mt6589", + MTK_EINT_FUNCTION(2, 69), + MTK_FUNCTION(0, "GPIO231"), + MTK_FUNCTION(1, "MSDC3_DAT0"), + MTK_FUNCTION(2, "EINT69"), + MTK_FUNCTION(3, "SCL3"), + MTK_FUNCTION(4, "PWM3"), + MTK_FUNCTION(5, "CLKM2"), + MTK_FUNCTION(7, "A_FUNC_DIN[2]") + ), +}; + +#endif /* __PINCTRL_MTK_MT6589_H */ From df344c4eaf4a71bcaa9df2127c439d15207a5a0d Mon Sep 17 00:00:00 2001 From: Tsuyukusa Akari Date: Mon, 12 Jan 2026 13:03:52 +0900 Subject: [PATCH 27/98] arm: dts: mediatek: mt6589: fix pinctrl reg --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index ee7d8d5cc55862..1c627bbe78cf79 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -149,7 +149,7 @@ */ pio: pinctrl@10005000 { compatible = "mediatek,mt6589-pinctrl"; - reg = <0 0x1000b000 0 0x1000>; + reg = <0x1000b000 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; gpio-controller; #gpio-cells = <2>; @@ -162,12 +162,12 @@ syscfg_pctl_a: syscfg_pctl_a@10005000 { compatible = "mediatek,mt6589-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; + reg = <0x10005000 0x1000>; }; syscfg_pctl_b: syscfg_pctl_b@1020c000 { compatible = "mediatek,mt6589-pctl-b-syscfg", "syscon"; - reg = <0 0x1020c000 0 0x1000>; + reg = <0x1020c000 0x1000>; }; timer: timer@10008000 { From 24dcda00a074694359f982682c97f425fdeaee3b Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 18 Jan 2026 16:08:56 +0900 Subject: [PATCH 28/98] dt-bindings: pinctrl: add mt6589 pinfunc header --- include/dt-bindings/pinctrl/mt6589-pinfunc.h | 1636 ++++++++++++++++++ 1 file changed, 1636 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt6589-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt6589-pinfunc.h b/include/dt-bindings/pinctrl/mt6589-pinfunc.h new file mode 100644 index 00000000000000..0b2880f2a639b4 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6589-pinfunc.h @@ -0,0 +1,1636 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: akku + */ + +#ifndef __MT6589_PINFUNC_H +#define __MT6589_PINFUNC_H + +#include + +#define MT6589_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6589_PIN_0_GPIO0__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT6589_PIN_0_GPIO0__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT6589_PIN_0_GPIO0__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT6589_PIN_0_GPIO0__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT6589_PIN_0_GPIO0__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT6589_PIN_0_GPIO0__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT6589_PIN_0_GPIO0__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT6589_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6589_PIN_1_GPIO1__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT6589_PIN_1_GPIO1__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT6589_PIN_1_GPIO1__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT6589_PIN_1_GPIO1__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT6589_PIN_1_GPIO1__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT6589_PIN_1_GPIO1__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT6589_PIN_1_GPIO1__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT6589_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6589_PIN_2_GPIO2__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT6589_PIN_2_GPIO2__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT6589_PIN_2_GPIO2__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT6589_PIN_2_GPIO2__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT6589_PIN_2_GPIO2__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT6589_PIN_2_GPIO2__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT6589_PIN_2_GPIO2__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT6589_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6589_PIN_3_GPIO3__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT6589_PIN_3_GPIO3__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT6589_PIN_3_GPIO3__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT6589_PIN_3_GPIO3__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT6589_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6589_PIN_4_GPIO4__FUNC_MSDC0_RSTB (MTK_PIN_NO(4) | 1) +#define MT6589_PIN_4_GPIO4__FUNC_EINT50 (MTK_PIN_NO(4) | 2) +#define MT6589_PIN_4_GPIO4__FUNC_I2SIN_DAT (MTK_PIN_NO(4) | 3) +#define MT6589_PIN_4_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 5) +#define MT6589_PIN_4_GPIO4__FUNC_SPI1_MI (MTK_PIN_NO(4) | 6) +#define MT6589_PIN_4_GPIO4__FUNC_NLD10 (MTK_PIN_NO(4) | 7) + +#define MT6589_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6589_PIN_5_GPIO5__FUNC_MSDC0_CMD (MTK_PIN_NO(5) | 1) +#define MT6589_PIN_5_GPIO5__FUNC_EINT41 (MTK_PIN_NO(5) | 2) +#define MT6589_PIN_5_GPIO5__FUNC_LRSTB_2X (MTK_PIN_NO(5) | 6) +#define MT6589_PIN_5_GPIO5__FUNC_NRNB (MTK_PIN_NO(5) | 7) + +#define MT6589_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6589_PIN_6_GPIO6__FUNC_MSDC0_CLK (MTK_PIN_NO(6) | 1) +#define MT6589_PIN_6_GPIO6__FUNC_EINT40 (MTK_PIN_NO(6) | 2) +#define MT6589_PIN_6_GPIO6__FUNC_LPTE (MTK_PIN_NO(6) | 6) +#define MT6589_PIN_6_GPIO6__FUNC_NREB (MTK_PIN_NO(6) | 7) + +#define MT6589_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6589_PIN_7_GPIO7__FUNC_MSDC0_DAT3 (MTK_PIN_NO(7) | 1) +#define MT6589_PIN_7_GPIO7__FUNC_EINT45 (MTK_PIN_NO(7) | 2) +#define MT6589_PIN_7_GPIO7__FUNC_LSCE0B_2X (MTK_PIN_NO(7) | 6) +#define MT6589_PIN_7_GPIO7__FUNC_NLD7 (MTK_PIN_NO(7) | 7) + +#define MT6589_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6589_PIN_8_GPIO8__FUNC_MSDC0_DAT2 (MTK_PIN_NO(8) | 1) +#define MT6589_PIN_8_GPIO8__FUNC_EINT44 (MTK_PIN_NO(8) | 2) +#define MT6589_PIN_8_GPIO8__FUNC_LSA0_2X (MTK_PIN_NO(8) | 6) +#define MT6589_PIN_8_GPIO8__FUNC_NLD14 (MTK_PIN_NO(8) | 7) + +#define MT6589_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6589_PIN_9_GPIO9__FUNC_MSDC0_DAT1 (MTK_PIN_NO(9) | 1) +#define MT6589_PIN_9_GPIO9__FUNC_EINT43 (MTK_PIN_NO(9) | 2) +#define MT6589_PIN_9_GPIO9__FUNC_LSCK_2X (MTK_PIN_NO(9) | 6) +#define MT6589_PIN_9_GPIO9__FUNC_NLD11 (MTK_PIN_NO(9) | 7) + +#define MT6589_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6589_PIN_10_GPIO10__FUNC_MSDC0_DAT0 (MTK_PIN_NO(10) | 1) +#define MT6589_PIN_10_GPIO10__FUNC_EINT42 (MTK_PIN_NO(10) | 2) +#define MT6589_PIN_10_GPIO10__FUNC_LSDA_2X (MTK_PIN_NO(10) | 6) + +#define MT6589_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6589_PIN_11_GPIO11__FUNC_NCEB0 (MTK_PIN_NO(11) | 1) +#define MT6589_PIN_11_GPIO11__FUNC_EINT139 (MTK_PIN_NO(11) | 2) +#define MT6589_PIN_11_GPIO11__FUNC_TESTA_OUT4 (MTK_PIN_NO(11) | 7) + +#define MT6589_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6589_PIN_12_GPIO12__FUNC_NCEB1 (MTK_PIN_NO(12) | 1) +#define MT6589_PIN_12_GPIO12__FUNC_EINT140 (MTK_PIN_NO(12) | 2) +#define MT6589_PIN_12_GPIO12__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(12) | 4) +#define MT6589_PIN_12_GPIO12__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(12) | 5) +#define MT6589_PIN_12_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 6) +#define MT6589_PIN_12_GPIO12__FUNC_TESTA_OUT5 (MTK_PIN_NO(12) | 7) + +#define MT6589_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6589_PIN_13_GPIO13__FUNC_NRNB (MTK_PIN_NO(13) | 1) +#define MT6589_PIN_13_GPIO13__FUNC_EINT141 (MTK_PIN_NO(13) | 2) +#define MT6589_PIN_13_GPIO13__FUNC_MD_ABB_AFUNC_D_0 (MTK_PIN_NO(13) | 6) +#define MT6589_PIN_13_GPIO13__FUNC_TESTA_OUT6 (MTK_PIN_NO(13) | 7) + +#define MT6589_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6589_PIN_14_GPIO14__FUNC_NCLE (MTK_PIN_NO(14) | 1) +#define MT6589_PIN_14_GPIO14__FUNC_EINT142 (MTK_PIN_NO(14) | 2) +#define MT6589_PIN_14_GPIO14__FUNC_DPI1_CK_1X (MTK_PIN_NO(14) | 3) +#define MT6589_PIN_14_GPIO14__FUNC_CM2PDN_1X (MTK_PIN_NO(14) | 4) +#define MT6589_PIN_14_GPIO14__FUNC_NALE (MTK_PIN_NO(14) | 6) +#define MT6589_PIN_14_GPIO14__FUNC_TESTA_OUT7 (MTK_PIN_NO(14) | 7) + +#define MT6589_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6589_PIN_15_GPIO15__FUNC_NALE (MTK_PIN_NO(15) | 1) +#define MT6589_PIN_15_GPIO15__FUNC_EINT143 (MTK_PIN_NO(15) | 2) +#define MT6589_PIN_15_GPIO15__FUNC_DPI1_DE_1X (MTK_PIN_NO(15) | 3) +#define MT6589_PIN_15_GPIO15__FUNC_CM2MCLK_1X (MTK_PIN_NO(15) | 4) +#define MT6589_PIN_15_GPIO15__FUNC_IRDA_RXD (MTK_PIN_NO(15) | 5) +#define MT6589_PIN_15_GPIO15__FUNC_NCLE (MTK_PIN_NO(15) | 6) +#define MT6589_PIN_15_GPIO15__FUNC_TESTA_OUT8 (MTK_PIN_NO(15) | 7) + +#define MT6589_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6589_PIN_16_GPIO16__FUNC_NREB (MTK_PIN_NO(16) | 1) +#define MT6589_PIN_16_GPIO16__FUNC_EINT144 (MTK_PIN_NO(16) | 2) +#define MT6589_PIN_16_GPIO16__FUNC_DPI1_HSYNC_1X (MTK_PIN_NO(16) | 3) +#define MT6589_PIN_16_GPIO16__FUNC_CM2RST_1X (MTK_PIN_NO(16) | 4) +#define MT6589_PIN_16_GPIO16__FUNC_IRDA_TXD (MTK_PIN_NO(16) | 5) +#define MT6589_PIN_16_GPIO16__FUNC_MD_ABB_AFUNC_D_1 (MTK_PIN_NO(16) | 6) +#define MT6589_PIN_16_GPIO16__FUNC_TESTA_OUT9 (MTK_PIN_NO(16) | 7) + +#define MT6589_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6589_PIN_17_GPIO17__FUNC_NWEB (MTK_PIN_NO(17) | 1) +#define MT6589_PIN_17_GPIO17__FUNC_EINT145 (MTK_PIN_NO(17) | 2) +#define MT6589_PIN_17_GPIO17__FUNC_DPI1_VSYNC_1X (MTK_PIN_NO(17) | 3) +#define MT6589_PIN_17_GPIO17__FUNC_CM2PCLK_1X (MTK_PIN_NO(17) | 4) +#define MT6589_PIN_17_GPIO17__FUNC_IRDA_PDN (MTK_PIN_NO(17) | 5) +#define MT6589_PIN_17_GPIO17__FUNC_MD_ABB_AFUNC_D_2 (MTK_PIN_NO(17) | 6) +#define MT6589_PIN_17_GPIO17__FUNC_TESTA_OUT10 (MTK_PIN_NO(17) | 7) + +#define MT6589_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6589_PIN_18_GPIO18__FUNC_NLD0 (MTK_PIN_NO(18) | 1) +#define MT6589_PIN_18_GPIO18__FUNC_EINT146 (MTK_PIN_NO(18) | 2) +#define MT6589_PIN_18_GPIO18__FUNC_DPI1_D_1X_0 (MTK_PIN_NO(18) | 3) +#define MT6589_PIN_18_GPIO18__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(18) | 4) +#define MT6589_PIN_18_GPIO18__FUNC_I2SIN_CK (MTK_PIN_NO(18) | 5) +#define MT6589_PIN_18_GPIO18__FUNC_DAC_CK (MTK_PIN_NO(18) | 6) +#define MT6589_PIN_18_GPIO18__FUNC_TESTA_OUT11 (MTK_PIN_NO(18) | 7) + +#define MT6589_PIN_19_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6589_PIN_19_GPIO19__FUNC_NLD1 (MTK_PIN_NO(19) | 1) +#define MT6589_PIN_19_GPIO19__FUNC_EINT147 (MTK_PIN_NO(19) | 2) +#define MT6589_PIN_19_GPIO19__FUNC_DPI1_D_1X_1 (MTK_PIN_NO(19) | 3) +#define MT6589_PIN_19_GPIO19__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(19) | 4) +#define MT6589_PIN_19_GPIO19__FUNC_I2SIN_WS (MTK_PIN_NO(19) | 5) +#define MT6589_PIN_19_GPIO19__FUNC_DAC_WS (MTK_PIN_NO(19) | 6) +#define MT6589_PIN_19_GPIO19__FUNC_TESTA_OUT12 (MTK_PIN_NO(19) | 7) + +#define MT6589_PIN_20_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6589_PIN_20_GPIO20__FUNC_NLD2 (MTK_PIN_NO(20) | 1) +#define MT6589_PIN_20_GPIO20__FUNC_EINT148 (MTK_PIN_NO(20) | 2) +#define MT6589_PIN_20_GPIO20__FUNC_DPI1_D_1X_2 (MTK_PIN_NO(20) | 3) +#define MT6589_PIN_20_GPIO20__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(20) | 4) +#define MT6589_PIN_20_GPIO20__FUNC_I2SOUT_DAT (MTK_PIN_NO(20) | 5) +#define MT6589_PIN_20_GPIO20__FUNC_DAC_DAT_OUT (MTK_PIN_NO(20) | 6) +#define MT6589_PIN_20_GPIO20__FUNC_TESTA_OUT13 (MTK_PIN_NO(20) | 7) + +#define MT6589_PIN_21_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6589_PIN_21_GPIO21__FUNC_NLD3 (MTK_PIN_NO(21) | 1) +#define MT6589_PIN_21_GPIO21__FUNC_EINT149 (MTK_PIN_NO(21) | 2) +#define MT6589_PIN_21_GPIO21__FUNC_DPI1_D_1X_3 (MTK_PIN_NO(21) | 3) +#define MT6589_PIN_21_GPIO21__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(21) | 4) +#define MT6589_PIN_21_GPIO21__FUNC_MD_ABB_AFUNC_D_3 (MTK_PIN_NO(21) | 6) +#define MT6589_PIN_21_GPIO21__FUNC_TESTA_OUT14 (MTK_PIN_NO(21) | 7) + +#define MT6589_PIN_22_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6589_PIN_22_GPIO22__FUNC_NLD4 (MTK_PIN_NO(22) | 1) +#define MT6589_PIN_22_GPIO22__FUNC_EINT150 (MTK_PIN_NO(22) | 2) +#define MT6589_PIN_22_GPIO22__FUNC_DPI1_D_1X_4 (MTK_PIN_NO(22) | 3) +#define MT6589_PIN_22_GPIO22__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(22) | 4) +#define MT6589_PIN_22_GPIO22__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(22) | 5) +#define MT6589_PIN_22_GPIO22__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(22) | 6) +#define MT6589_PIN_22_GPIO22__FUNC_TESTA_OUT15 (MTK_PIN_NO(22) | 7) + +#define MT6589_PIN_23_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6589_PIN_23_GPIO23__FUNC_NLD5 (MTK_PIN_NO(23) | 1) +#define MT6589_PIN_23_GPIO23__FUNC_EINT151 (MTK_PIN_NO(23) | 2) +#define MT6589_PIN_23_GPIO23__FUNC_DPI1_D_1X_5 (MTK_PIN_NO(23) | 3) +#define MT6589_PIN_23_GPIO23__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(23) | 4) +#define MT6589_PIN_23_GPIO23__FUNC_MD_ABB_AFUNC_D_4 (MTK_PIN_NO(23) | 6) +#define MT6589_PIN_23_GPIO23__FUNC_TESTA_OUT16 (MTK_PIN_NO(23) | 7) + +#define MT6589_PIN_24_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6589_PIN_24_GPIO24__FUNC_NLD6 (MTK_PIN_NO(24) | 1) +#define MT6589_PIN_24_GPIO24__FUNC_EINT152 (MTK_PIN_NO(24) | 2) +#define MT6589_PIN_24_GPIO24__FUNC_DPI1_D_1X_6 (MTK_PIN_NO(24) | 3) +#define MT6589_PIN_24_GPIO24__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(24) | 4) +#define MT6589_PIN_24_GPIO24__FUNC_MD_ABB_AFUNC_D_5 (MTK_PIN_NO(24) | 6) +#define MT6589_PIN_24_GPIO24__FUNC_TESTA_OUT17 (MTK_PIN_NO(24) | 7) + +#define MT6589_PIN_25_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6589_PIN_25_GPIO25__FUNC_NLD7 (MTK_PIN_NO(25) | 1) +#define MT6589_PIN_25_GPIO25__FUNC_EINT153 (MTK_PIN_NO(25) | 2) +#define MT6589_PIN_25_GPIO25__FUNC_DPI1_D_1X_7 (MTK_PIN_NO(25) | 3) +#define MT6589_PIN_25_GPIO25__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(25) | 4) +#define MT6589_PIN_25_GPIO25__FUNC_MD_ABB_AFUNC_D_6 (MTK_PIN_NO(25) | 6) +#define MT6589_PIN_25_GPIO25__FUNC_TESTA_OUT18 (MTK_PIN_NO(25) | 7) + +#define MT6589_PIN_26_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6589_PIN_26_GPIO26__FUNC_NLD8 (MTK_PIN_NO(26) | 1) +#define MT6589_PIN_26_GPIO26__FUNC_EINT154 (MTK_PIN_NO(26) | 2) +#define MT6589_PIN_26_GPIO26__FUNC_DPI1_D_1X_8 (MTK_PIN_NO(26) | 3) +#define MT6589_PIN_26_GPIO26__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(26) | 4) +#define MT6589_PIN_26_GPIO26__FUNC_MD_ABB_AFUNC_D_7 (MTK_PIN_NO(26) | 6) +#define MT6589_PIN_26_GPIO26__FUNC_TESTA_OUT19 (MTK_PIN_NO(26) | 7) + +#define MT6589_PIN_27_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6589_PIN_27_GPIO27__FUNC_NLD9 (MTK_PIN_NO(27) | 1) +#define MT6589_PIN_27_GPIO27__FUNC_EINT155 (MTK_PIN_NO(27) | 2) +#define MT6589_PIN_27_GPIO27__FUNC_DPI1_D_1X_9 (MTK_PIN_NO(27) | 3) +#define MT6589_PIN_27_GPIO27__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(27) | 4) +#define MT6589_PIN_27_GPIO27__FUNC_PWM1 (MTK_PIN_NO(27) | 5) +#define MT6589_PIN_27_GPIO27__FUNC_MD_ABB_AFUNC_D_8 (MTK_PIN_NO(27) | 6) +#define MT6589_PIN_27_GPIO27__FUNC_TESTA_OUT20 (MTK_PIN_NO(27) | 7) + +#define MT6589_PIN_28_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6589_PIN_28_GPIO28__FUNC_NLD10 (MTK_PIN_NO(28) | 1) +#define MT6589_PIN_28_GPIO28__FUNC_EINT156 (MTK_PIN_NO(28) | 2) +#define MT6589_PIN_28_GPIO28__FUNC_DPI1_D_1X_10 (MTK_PIN_NO(28) | 3) +#define MT6589_PIN_28_GPIO28__FUNC_CM2VSYNC_1X (MTK_PIN_NO(28) | 4) +#define MT6589_PIN_28_GPIO28__FUNC_PWM2 (MTK_PIN_NO(28) | 5) +#define MT6589_PIN_28_GPIO28__FUNC_MD_ABB_AFUNC_D_9 (MTK_PIN_NO(28) | 6) +#define MT6589_PIN_28_GPIO28__FUNC_TESTA_OUT21 (MTK_PIN_NO(28) | 7) + +#define MT6589_PIN_29_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6589_PIN_29_GPIO29__FUNC_NLD11 (MTK_PIN_NO(29) | 1) +#define MT6589_PIN_29_GPIO29__FUNC_EINT157 (MTK_PIN_NO(29) | 2) +#define MT6589_PIN_29_GPIO29__FUNC_DPI1_D_1X_11 (MTK_PIN_NO(29) | 3) +#define MT6589_PIN_29_GPIO29__FUNC_CM2HSYNC_1X (MTK_PIN_NO(29) | 4) +#define MT6589_PIN_29_GPIO29__FUNC_PWM3 (MTK_PIN_NO(29) | 5) +#define MT6589_PIN_29_GPIO29__FUNC_MD_ABB_AFUNC_D_10 (MTK_PIN_NO(29) | 6) +#define MT6589_PIN_29_GPIO29__FUNC_TESTA_OUT22 (MTK_PIN_NO(29) | 7) + +#define MT6589_PIN_30_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6589_PIN_30_GPIO30__FUNC_NLD12 (MTK_PIN_NO(30) | 1) +#define MT6589_PIN_30_GPIO30__FUNC_EINT158 (MTK_PIN_NO(30) | 2) +#define MT6589_PIN_30_GPIO30__FUNC_I2SIN_CK (MTK_PIN_NO(30) | 3) +#define MT6589_PIN_30_GPIO30__FUNC_DAC_CK (MTK_PIN_NO(30) | 4) +#define MT6589_PIN_30_GPIO30__FUNC_PCM1_CK (MTK_PIN_NO(30) | 5) +#define MT6589_PIN_30_GPIO30__FUNC_MD_ABB_AFUNC_D_11 (MTK_PIN_NO(30) | 6) +#define MT6589_PIN_30_GPIO30__FUNC_TESTA_OUT23 (MTK_PIN_NO(30) | 7) + +#define MT6589_PIN_31_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6589_PIN_31_GPIO31__FUNC_NLD13 (MTK_PIN_NO(31) | 1) +#define MT6589_PIN_31_GPIO31__FUNC_EINT159 (MTK_PIN_NO(31) | 2) +#define MT6589_PIN_31_GPIO31__FUNC_I2SIN_WS (MTK_PIN_NO(31) | 3) +#define MT6589_PIN_31_GPIO31__FUNC_DAC_WS (MTK_PIN_NO(31) | 4) +#define MT6589_PIN_31_GPIO31__FUNC_PCM1_WS (MTK_PIN_NO(31) | 5) +#define MT6589_PIN_31_GPIO31__FUNC_MD_ABB_AFUNC_D_12 (MTK_PIN_NO(31) | 6) +#define MT6589_PIN_31_GPIO31__FUNC_TESTA_OUT24 (MTK_PIN_NO(31) | 7) + +#define MT6589_PIN_32_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6589_PIN_32_GPIO32__FUNC_NLD14 (MTK_PIN_NO(32) | 1) +#define MT6589_PIN_32_GPIO32__FUNC_EINT160 (MTK_PIN_NO(32) | 2) +#define MT6589_PIN_32_GPIO32__FUNC_I2SOUT_DAT (MTK_PIN_NO(32) | 3) +#define MT6589_PIN_32_GPIO32__FUNC_DAC_DAT_OUT (MTK_PIN_NO(32) | 4) +#define MT6589_PIN_32_GPIO32__FUNC_PCM1_DO (MTK_PIN_NO(32) | 5) +#define MT6589_PIN_32_GPIO32__FUNC_MD_ABB_AFUNC_D_13 (MTK_PIN_NO(32) | 6) +#define MT6589_PIN_32_GPIO32__FUNC_TESTA_OUT25 (MTK_PIN_NO(32) | 7) + +#define MT6589_PIN_33_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6589_PIN_33_GPIO33__FUNC_NLD15 (MTK_PIN_NO(33) | 1) +#define MT6589_PIN_33_GPIO33__FUNC_EINT161 (MTK_PIN_NO(33) | 2) +#define MT6589_PIN_33_GPIO33__FUNC_DISP_PWM (MTK_PIN_NO(33) | 3) +#define MT6589_PIN_33_GPIO33__FUNC_PWM4 (MTK_PIN_NO(33) | 4) +#define MT6589_PIN_33_GPIO33__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +#define MT6589_PIN_33_GPIO33__FUNC_MD_ABB_AFUNC_D_14 (MTK_PIN_NO(33) | 6) +#define MT6589_PIN_33_GPIO33__FUNC_TESTA_OUT26 (MTK_PIN_NO(33) | 7) + +#define MT6589_PIN_34_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6589_PIN_34_GPIO34__FUNC_EINT0 (MTK_PIN_NO(34) | 1) +#define MT6589_PIN_34_GPIO34__FUNC_PWM1 (MTK_PIN_NO(34) | 2) +#define MT6589_PIN_34_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 3) +#define MT6589_PIN_34_GPIO34__FUNC_MD2_UTXD (MTK_PIN_NO(34) | 5) +#define MT6589_PIN_34_GPIO34__FUNC_MD1_EINT1 (MTK_PIN_NO(34) | 6) +#define MT6589_PIN_34_GPIO34__FUNC_USB_SCL (MTK_PIN_NO(34) | 7) + +#define MT6589_PIN_35_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6589_PIN_35_GPIO35__FUNC_EINT1 (MTK_PIN_NO(35) | 1) +#define MT6589_PIN_35_GPIO35__FUNC_PWM2 (MTK_PIN_NO(35) | 2) +#define MT6589_PIN_35_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 3) +#define MT6589_PIN_35_GPIO35__FUNC_MD2_URXD (MTK_PIN_NO(35) | 5) +#define MT6589_PIN_35_GPIO35__FUNC_MD1_EINT2 (MTK_PIN_NO(35) | 6) +#define MT6589_PIN_35_GPIO35__FUNC_USB_SDA (MTK_PIN_NO(35) | 7) + +#define MT6589_PIN_36_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6589_PIN_36_GPIO36__FUNC_EINT2 (MTK_PIN_NO(36) | 1) +#define MT6589_PIN_36_GPIO36__FUNC_PWM3 (MTK_PIN_NO(36) | 2) +#define MT6589_PIN_36_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 3) +#define MT6589_PIN_36_GPIO36__FUNC_SRCLKENAI2 (MTK_PIN_NO(36) | 4) +#define MT6589_PIN_36_GPIO36__FUNC_MD1_EINT3 (MTK_PIN_NO(36) | 6) + +#define MT6589_PIN_37_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6589_PIN_37_GPIO37__FUNC_EINT3 (MTK_PIN_NO(37) | 1) +#define MT6589_PIN_37_GPIO37__FUNC_MD1_EINT5 (MTK_PIN_NO(37) | 6) +#define MT6589_PIN_37_GPIO37__FUNC_EXT_26M_CK (MTK_PIN_NO(37) | 7) + +#define MT6589_PIN_38_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6589_PIN_38_GPIO38__FUNC_EINT4 (MTK_PIN_NO(38) | 1) +#define MT6589_PIN_38_GPIO38__FUNC_PWM4 (MTK_PIN_NO(38) | 2) +#define MT6589_PIN_38_GPIO38__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(38) | 3) +#define MT6589_PIN_38_GPIO38__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(38) | 4) +#define MT6589_PIN_38_GPIO38__FUNC_USB_DRVVBUS (MTK_PIN_NO(38) | 5) +#define MT6589_PIN_38_GPIO38__FUNC_MD1_EINT4 (MTK_PIN_NO(38) | 6) + +#define MT6589_PIN_39_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6589_PIN_39_GPIO39__FUNC_PWRAP_SPIDI (MTK_PIN_NO(39) | 1) +#define MT6589_PIN_39_GPIO39__FUNC_EINT29 (MTK_PIN_NO(39) | 2) + +#define MT6589_PIN_40_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6589_PIN_40_GPIO40__FUNC_PWRAP_SPIDO (MTK_PIN_NO(40) | 1) +#define MT6589_PIN_40_GPIO40__FUNC_EINT28 (MTK_PIN_NO(40) | 2) + +#define MT6589_PIN_41_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6589_PIN_41_GPIO41__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(41) | 1) +#define MT6589_PIN_41_GPIO41__FUNC_EINT27 (MTK_PIN_NO(41) | 2) + +#define MT6589_PIN_42_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6589_PIN_42_GPIO42__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(42) | 1) +#define MT6589_PIN_42_GPIO42__FUNC_EINT26 (MTK_PIN_NO(42) | 2) + +#define MT6589_PIN_43_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6589_PIN_43_GPIO43__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(43) | 1) +#define MT6589_PIN_43_GPIO43__FUNC_EINT25 (MTK_PIN_NO(43) | 2) + +#define MT6589_PIN_44_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6589_PIN_44_GPIO44__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(44) | 1) +#define MT6589_PIN_44_GPIO44__FUNC_EINT30 (MTK_PIN_NO(44) | 2) +#define MT6589_PIN_44_GPIO44__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(44) | 3) +#define MT6589_PIN_44_GPIO44__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(44) | 4) +#define MT6589_PIN_44_GPIO44__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(44) | 5) +#define MT6589_PIN_44_GPIO44__FUNC_MD_ABB_AFUNC_D_15 (MTK_PIN_NO(44) | 6) + +#define MT6589_PIN_45_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6589_PIN_45_GPIO45__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(45) | 1) +#define MT6589_PIN_45_GPIO45__FUNC_EINT31 (MTK_PIN_NO(45) | 2) +#define MT6589_PIN_45_GPIO45__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(45) | 3) +#define MT6589_PIN_45_GPIO45__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(45) | 4) +#define MT6589_PIN_45_GPIO45__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(45) | 5) +#define MT6589_PIN_45_GPIO45__FUNC_MD_ABB_AFUNC_D_16 (MTK_PIN_NO(45) | 6) + +#define MT6589_PIN_46_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6589_PIN_46_GPIO46__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(46) | 1) +#define MT6589_PIN_46_GPIO46__FUNC_EINT32 (MTK_PIN_NO(46) | 2) +#define MT6589_PIN_46_GPIO46__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(46) | 3) +#define MT6589_PIN_46_GPIO46__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(46) | 4) +#define MT6589_PIN_46_GPIO46__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(46) | 5) +#define MT6589_PIN_46_GPIO46__FUNC_MD_ABB_AFUNC_D_17 (MTK_PIN_NO(46) | 6) + +#define MT6589_PIN_47_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6589_PIN_47_GPIO47__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(47) | 1) +#define MT6589_PIN_47_GPIO47__FUNC_EINT33 (MTK_PIN_NO(47) | 2) +#define MT6589_PIN_47_GPIO47__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(47) | 3) +#define MT6589_PIN_47_GPIO47__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(47) | 4) +#define MT6589_PIN_47_GPIO47__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(47) | 5) +#define MT6589_PIN_47_GPIO47__FUNC_MD_ABB_AFUNC_D_18 (MTK_PIN_NO(47) | 6) + +#define MT6589_PIN_48_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6589_PIN_48_GPIO48__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(48) | 1) +#define MT6589_PIN_48_GPIO48__FUNC_EINT34 (MTK_PIN_NO(48) | 2) +#define MT6589_PIN_48_GPIO48__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(48) | 3) +#define MT6589_PIN_48_GPIO48__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(48) | 4) +#define MT6589_PIN_48_GPIO48__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(48) | 5) +#define MT6589_PIN_48_GPIO48__FUNC_MD_ABB_AFUNC_D_19 (MTK_PIN_NO(48) | 6) + +#define MT6589_PIN_49_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT6589_PIN_49_GPIO49__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(49) | 1) +#define MT6589_PIN_49_GPIO49__FUNC_EINT35 (MTK_PIN_NO(49) | 2) +#define MT6589_PIN_49_GPIO49__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(49) | 3) +#define MT6589_PIN_49_GPIO49__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(49) | 4) +#define MT6589_PIN_49_GPIO49__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(49) | 5) +#define MT6589_PIN_49_GPIO49__FUNC_MD_ABB_AFUNC_D_20 (MTK_PIN_NO(49) | 6) + +#define MT6589_PIN_50_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT6589_PIN_50_GPIO50__FUNC_ADC_CK (MTK_PIN_NO(50) | 1) +#define MT6589_PIN_50_GPIO50__FUNC_EINT19 (MTK_PIN_NO(50) | 2) + +#define MT6589_PIN_51_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT6589_PIN_51_GPIO51__FUNC_ADC_WS (MTK_PIN_NO(51) | 1) +#define MT6589_PIN_51_GPIO51__FUNC_EINT21 (MTK_PIN_NO(51) | 2) + +#define MT6589_PIN_52_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT6589_PIN_52_GPIO52__FUNC_ADC_DAT_IN (MTK_PIN_NO(52) | 1) +#define MT6589_PIN_52_GPIO52__FUNC_EINT20 (MTK_PIN_NO(52) | 2) + +#define MT6589_PIN_53_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT6589_PIN_53_GPIO53__FUNC_DAC_CK (MTK_PIN_NO(53) | 1) +#define MT6589_PIN_53_GPIO53__FUNC_EINT22 (MTK_PIN_NO(53) | 2) + +#define MT6589_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT6589_PIN_54_GPIO54__FUNC_DAC_WS (MTK_PIN_NO(54) | 1) +#define MT6589_PIN_54_GPIO54__FUNC_EINT24 (MTK_PIN_NO(54) | 2) + +#define MT6589_PIN_55_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT6589_PIN_55_GPIO55__FUNC_DAC_DAT_OUT (MTK_PIN_NO(55) | 1) +#define MT6589_PIN_55_GPIO55__FUNC_EINT23 (MTK_PIN_NO(55) | 2) + +#define MT6589_PIN_56_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT6589_PIN_56_GPIO56__FUNC_RTC32K_CK (MTK_PIN_NO(56) | 1) + +#define MT6589_PIN_57_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT6589_PIN_57_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 1) +#define MT6589_PIN_57_GPIO57__FUNC_EINT34 (MTK_PIN_NO(57) | 2) + +#define MT6589_PIN_58_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT6589_PIN_58_GPIO58__FUNC_WATCHDOG (MTK_PIN_NO(58) | 1) +#define MT6589_PIN_58_GPIO58__FUNC_EINT36 (MTK_PIN_NO(58) | 2) + +#define MT6589_PIN_59_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT6589_PIN_59_GPIO59__FUNC_SRCLKENA (MTK_PIN_NO(59) | 1) +#define MT6589_PIN_59_GPIO59__FUNC_EINT38 (MTK_PIN_NO(59) | 2) + +#define MT6589_PIN_60_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT6589_PIN_60_GPIO60__FUNC_SRCVOLTEN (MTK_PIN_NO(60) | 1) +#define MT6589_PIN_60_GPIO60__FUNC_EINT37 (MTK_PIN_NO(60) | 2) + +#define MT6589_PIN_61_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT6589_PIN_61_GPIO61__FUNC_JTCK (MTK_PIN_NO(61) | 1) +#define MT6589_PIN_61_GPIO61__FUNC_EINT188 (MTK_PIN_NO(61) | 2) +#define MT6589_PIN_61_GPIO61__FUNC_DSP1_ICK (MTK_PIN_NO(61) | 3) +#define MT6589_PIN_61_GPIO61__FUNC_MD2_TCK_PAD (MTK_PIN_NO(61) | 7) + +#define MT6589_PIN_62_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT6589_PIN_62_GPIO62__FUNC_JTDO (MTK_PIN_NO(62) | 1) +#define MT6589_PIN_62_GPIO62__FUNC_EINT190 (MTK_PIN_NO(62) | 2) +#define MT6589_PIN_62_GPIO62__FUNC_DSP2_IMS (MTK_PIN_NO(62) | 3) +#define MT6589_PIN_62_GPIO62__FUNC_MD2_TDO_PAD (MTK_PIN_NO(62) | 7) + +#define MT6589_PIN_63_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT6589_PIN_63_GPIO63__FUNC_JTRST_B (MTK_PIN_NO(63) | 1) +#define MT6589_PIN_63_GPIO63__FUNC_EINT0 (MTK_PIN_NO(63) | 2) +#define MT6589_PIN_63_GPIO63__FUNC_DSP2_ICK (MTK_PIN_NO(63) | 3) +#define MT6589_PIN_63_GPIO63__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(63) | 7) + +#define MT6589_PIN_64_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT6589_PIN_64_GPIO64__FUNC_JTDI (MTK_PIN_NO(64) | 1) +#define MT6589_PIN_64_GPIO64__FUNC_EINT189 (MTK_PIN_NO(64) | 2) +#define MT6589_PIN_64_GPIO64__FUNC_DSP1_IMS (MTK_PIN_NO(64) | 3) +#define MT6589_PIN_64_GPIO64__FUNC_MD2_TDI_PAD (MTK_PIN_NO(64) | 7) + +#define MT6589_PIN_65_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT6589_PIN_65_GPIO65__FUNC_JRTCK (MTK_PIN_NO(65) | 1) +#define MT6589_PIN_65_GPIO65__FUNC_EINT187 (MTK_PIN_NO(65) | 2) +#define MT6589_PIN_65_GPIO65__FUNC_DSP1_ID (MTK_PIN_NO(65) | 3) +#define MT6589_PIN_65_GPIO65__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(65) | 7) + +#define MT6589_PIN_66_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT6589_PIN_66_GPIO66__FUNC_JTMS (MTK_PIN_NO(66) | 1) +#define MT6589_PIN_66_GPIO66__FUNC_EINT191 (MTK_PIN_NO(66) | 2) +#define MT6589_PIN_66_GPIO66__FUNC_DSP2_ID (MTK_PIN_NO(66) | 3) +#define MT6589_PIN_66_GPIO66__FUNC_MD2_TMS_PAD (MTK_PIN_NO(66) | 7) + +#define MT6589_PIN_67_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT6589_PIN_67_GPIO67__FUNC_SDA3 (MTK_PIN_NO(67) | 1) +#define MT6589_PIN_67_GPIO67__FUNC_EINT97 (MTK_PIN_NO(67) | 2) +#define MT6589_PIN_67_GPIO67__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(67) | 7) + +#define MT6589_PIN_68_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT6589_PIN_68_GPIO68__FUNC_SCL3 (MTK_PIN_NO(68) | 1) +#define MT6589_PIN_68_GPIO68__FUNC_EINT96 (MTK_PIN_NO(68) | 2) +#define MT6589_PIN_68_GPIO68__FUNC_CLKM6 (MTK_PIN_NO(68) | 3) +#define MT6589_PIN_68_GPIO68__FUNC_PWM6 (MTK_PIN_NO(68) | 4) +#define MT6589_PIN_68_GPIO68__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(68) | 7) + +#define MT6589_PIN_69_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT6589_PIN_69_GPIO69__FUNC_URXD2 (MTK_PIN_NO(69) | 1) +#define MT6589_PIN_69_GPIO69__FUNC_EINT83 (MTK_PIN_NO(69) | 2) +#define MT6589_PIN_69_GPIO69__FUNC_BSI2_CLK (MTK_PIN_NO(69) | 3) +#define MT6589_PIN_69_GPIO69__FUNC_MD1_URXD (MTK_PIN_NO(69) | 4) +#define MT6589_PIN_69_GPIO69__FUNC_CLKM3 (MTK_PIN_NO(69) | 5) +#define MT6589_PIN_69_GPIO69__FUNC_UTXD2 (MTK_PIN_NO(69) | 6) +#define MT6589_PIN_69_GPIO69__FUNC_MD1_EINT4 (MTK_PIN_NO(69) | 7) + +#define MT6589_PIN_70_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT6589_PIN_70_GPIO70__FUNC_UTXD2 (MTK_PIN_NO(70) | 1) +#define MT6589_PIN_70_GPIO70__FUNC_EINT82 (MTK_PIN_NO(70) | 2) +#define MT6589_PIN_70_GPIO70__FUNC_BSI2_CS (MTK_PIN_NO(70) | 3) +#define MT6589_PIN_70_GPIO70__FUNC_MD1_UTXD (MTK_PIN_NO(70) | 4) +#define MT6589_PIN_70_GPIO70__FUNC_CLKM2 (MTK_PIN_NO(70) | 5) +#define MT6589_PIN_70_GPIO70__FUNC_URXD2 (MTK_PIN_NO(70) | 6) +#define MT6589_PIN_70_GPIO70__FUNC_MD1_EINT3 (MTK_PIN_NO(70) | 7) + +#define MT6589_PIN_71_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT6589_PIN_71_GPIO71__FUNC_UCTS2 (MTK_PIN_NO(71) | 1) +#define MT6589_PIN_71_GPIO71__FUNC_EINT84 (MTK_PIN_NO(71) | 2) +#define MT6589_PIN_71_GPIO71__FUNC_BSI2_DATA0 (MTK_PIN_NO(71) | 3) +#define MT6589_PIN_71_GPIO71__FUNC_MD2_UTXD (MTK_PIN_NO(71) | 4) +#define MT6589_PIN_71_GPIO71__FUNC_PWM1 (MTK_PIN_NO(71) | 5) +#define MT6589_PIN_71_GPIO71__FUNC_URTS2 (MTK_PIN_NO(71) | 6) +#define MT6589_PIN_71_GPIO71__FUNC_MD2_EINT1 (MTK_PIN_NO(71) | 7) + +#define MT6589_PIN_72_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT6589_PIN_72_GPIO72__FUNC_URTS2 (MTK_PIN_NO(72) | 1) +#define MT6589_PIN_72_GPIO72__FUNC_EINT85 (MTK_PIN_NO(72) | 2) +#define MT6589_PIN_72_GPIO72__FUNC_BSI2_DATA1 (MTK_PIN_NO(72) | 3) +#define MT6589_PIN_72_GPIO72__FUNC_MD2_URXD (MTK_PIN_NO(72) | 4) +#define MT6589_PIN_72_GPIO72__FUNC_PWM2 (MTK_PIN_NO(72) | 5) +#define MT6589_PIN_72_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 6) +#define MT6589_PIN_72_GPIO72__FUNC_MD2_EINT2 (MTK_PIN_NO(72) | 7) + +#define MT6589_PIN_73_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT6589_PIN_73_GPIO73__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +#define MT6589_PIN_73_GPIO73__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +#define MT6589_PIN_73_GPIO73__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(73) | 3) +#define MT6589_PIN_73_GPIO73__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(73) | 4) +#define MT6589_PIN_73_GPIO73__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +#define MT6589_PIN_73_GPIO73__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +#define MT6589_PIN_73_GPIO73__FUNC_MD2_TCK_PAD (MTK_PIN_NO(73) | 7) + +#define MT6589_PIN_74_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT6589_PIN_74_GPIO74__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +#define MT6589_PIN_74_GPIO74__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +#define MT6589_PIN_74_GPIO74__FUNC_BPI2_BUS11 (MTK_PIN_NO(74) | 3) +#define MT6589_PIN_74_GPIO74__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +#define MT6589_PIN_74_GPIO74__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +#define MT6589_PIN_74_GPIO74__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +#define MT6589_PIN_74_GPIO74__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(74) | 7) + +#define MT6589_PIN_75_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT6589_PIN_75_GPIO75__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +#define MT6589_PIN_75_GPIO75__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +#define MT6589_PIN_75_GPIO75__FUNC_BPI2_BUS12 (MTK_PIN_NO(75) | 3) +#define MT6589_PIN_75_GPIO75__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +#define MT6589_PIN_75_GPIO75__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +#define MT6589_PIN_75_GPIO75__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +#define MT6589_PIN_75_GPIO75__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(75) | 7) + +#define MT6589_PIN_76_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT6589_PIN_76_GPIO76__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +#define MT6589_PIN_76_GPIO76__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +#define MT6589_PIN_76_GPIO76__FUNC_BPI2_BUS13 (MTK_PIN_NO(76) | 3) +#define MT6589_PIN_76_GPIO76__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +#define MT6589_PIN_76_GPIO76__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +#define MT6589_PIN_76_GPIO76__FUNC_MD2_TMS_PAD (MTK_PIN_NO(76) | 7) + +#define MT6589_PIN_77_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT6589_PIN_77_GPIO77__FUNC_URXD1 (MTK_PIN_NO(77) | 1) +#define MT6589_PIN_77_GPIO77__FUNC_EINT79 (MTK_PIN_NO(77) | 2) +#define MT6589_PIN_77_GPIO77__FUNC_URXD4 (MTK_PIN_NO(77) | 3) +#define MT6589_PIN_77_GPIO77__FUNC_MD1_URXD (MTK_PIN_NO(77) | 4) +#define MT6589_PIN_77_GPIO77__FUNC_MD2_URXD (MTK_PIN_NO(77) | 5) +#define MT6589_PIN_77_GPIO77__FUNC_UTXD1 (MTK_PIN_NO(77) | 6) +#define MT6589_PIN_77_GPIO77__FUNC_MD2_TDO_PAD (MTK_PIN_NO(77) | 7) + +#define MT6589_PIN_78_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT6589_PIN_78_GPIO78__FUNC_UTXD1 (MTK_PIN_NO(78) | 1) +#define MT6589_PIN_78_GPIO78__FUNC_EINT78 (MTK_PIN_NO(78) | 2) +#define MT6589_PIN_78_GPIO78__FUNC_UTXD4 (MTK_PIN_NO(78) | 3) +#define MT6589_PIN_78_GPIO78__FUNC_MD1_UTXD (MTK_PIN_NO(78) | 4) +#define MT6589_PIN_78_GPIO78__FUNC_MD2_UTXD (MTK_PIN_NO(78) | 5) +#define MT6589_PIN_78_GPIO78__FUNC_URXD1 (MTK_PIN_NO(78) | 6) +#define MT6589_PIN_78_GPIO78__FUNC_MD2_TDI_PAD (MTK_PIN_NO(78) | 7) + +#define MT6589_PIN_79_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT6589_PIN_79_GPIO79__FUNC_UCTS1 (MTK_PIN_NO(79) | 1) +#define MT6589_PIN_79_GPIO79__FUNC_EINT80 (MTK_PIN_NO(79) | 2) +#define MT6589_PIN_79_GPIO79__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(79) | 3) +#define MT6589_PIN_79_GPIO79__FUNC_MD1_UTXD (MTK_PIN_NO(79) | 4) +#define MT6589_PIN_79_GPIO79__FUNC_CLKM0 (MTK_PIN_NO(79) | 5) +#define MT6589_PIN_79_GPIO79__FUNC_URTS1 (MTK_PIN_NO(79) | 6) +#define MT6589_PIN_79_GPIO79__FUNC_MD1_EINT1 (MTK_PIN_NO(79) | 7) + +#define MT6589_PIN_80_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT6589_PIN_80_GPIO80__FUNC_URTS1 (MTK_PIN_NO(80) | 1) +#define MT6589_PIN_80_GPIO80__FUNC_EINT81 (MTK_PIN_NO(80) | 2) +#define MT6589_PIN_80_GPIO80__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(80) | 3) +#define MT6589_PIN_80_GPIO80__FUNC_MD1_URXD (MTK_PIN_NO(80) | 4) +#define MT6589_PIN_80_GPIO80__FUNC_CLKM1 (MTK_PIN_NO(80) | 5) +#define MT6589_PIN_80_GPIO80__FUNC_UCTS1 (MTK_PIN_NO(80) | 6) +#define MT6589_PIN_80_GPIO80__FUNC_MD1_EINT2 (MTK_PIN_NO(80) | 7) + +#define MT6589_PIN_81_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT6589_PIN_81_GPIO81__FUNC_URXD4 (MTK_PIN_NO(81) | 1) +#define MT6589_PIN_81_GPIO81__FUNC_EINT89 (MTK_PIN_NO(81) | 2) +#define MT6589_PIN_81_GPIO81__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT6589_PIN_81_GPIO81__FUNC_MD1_URXD (MTK_PIN_NO(81) | 4) +#define MT6589_PIN_81_GPIO81__FUNC_MD2_URXD (MTK_PIN_NO(81) | 5) +#define MT6589_PIN_81_GPIO81__FUNC_UTXD4 (MTK_PIN_NO(81) | 6) +#define MT6589_PIN_81_GPIO81__FUNC_MD2_EINT5 (MTK_PIN_NO(81) | 7) + +#define MT6589_PIN_82_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT6589_PIN_82_GPIO82__FUNC_UTXD4 (MTK_PIN_NO(82) | 1) +#define MT6589_PIN_82_GPIO82__FUNC_EINT88 (MTK_PIN_NO(82) | 2) +#define MT6589_PIN_82_GPIO82__FUNC_UTXD1 (MTK_PIN_NO(82) | 3) +#define MT6589_PIN_82_GPIO82__FUNC_MD1_UTXD (MTK_PIN_NO(82) | 4) +#define MT6589_PIN_82_GPIO82__FUNC_MD2_UTXD (MTK_PIN_NO(82) | 5) +#define MT6589_PIN_82_GPIO82__FUNC_URXD4 (MTK_PIN_NO(82) | 6) +#define MT6589_PIN_82_GPIO82__FUNC_MD1_EINT5 (MTK_PIN_NO(82) | 7) + +#define MT6589_PIN_83_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT6589_PIN_83_GPIO83__FUNC_DUAL_BPI1_BUS0 (MTK_PIN_NO(83) | 1) +#define MT6589_PIN_83_GPIO83__FUNC_EINT1 (MTK_PIN_NO(83) | 2) +#define MT6589_PIN_83_GPIO83__FUNC_BPI2_BUS0 (MTK_PIN_NO(83) | 3) +#define MT6589_PIN_83_GPIO83__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(83) | 5) +#define MT6589_PIN_83_GPIO83__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(83) | 7) + +#define MT6589_PIN_84_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT6589_PIN_84_GPIO84__FUNC_DUAL_BPI1_BUS1 (MTK_PIN_NO(84) | 1) +#define MT6589_PIN_84_GPIO84__FUNC_EINT2 (MTK_PIN_NO(84) | 2) +#define MT6589_PIN_84_GPIO84__FUNC_BPI2_BUS1 (MTK_PIN_NO(84) | 3) +#define MT6589_PIN_84_GPIO84__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(84) | 5) +#define MT6589_PIN_84_GPIO84__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(84) | 7) + +#define MT6589_PIN_85_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT6589_PIN_85_GPIO85__FUNC_DUAL_BPI1_BUS2 (MTK_PIN_NO(85) | 1) +#define MT6589_PIN_85_GPIO85__FUNC_EINT3 (MTK_PIN_NO(85) | 2) +#define MT6589_PIN_85_GPIO85__FUNC_BPI2_BUS2 (MTK_PIN_NO(85) | 3) +#define MT6589_PIN_85_GPIO85__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(85) | 5) +#define MT6589_PIN_85_GPIO85__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(85) | 7) + +#define MT6589_PIN_86_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT6589_PIN_86_GPIO86__FUNC_DUAL_BPI1_BUS3 (MTK_PIN_NO(86) | 1) +#define MT6589_PIN_86_GPIO86__FUNC_EINT4 (MTK_PIN_NO(86) | 2) +#define MT6589_PIN_86_GPIO86__FUNC_BPI2_BUS3 (MTK_PIN_NO(86) | 3) +#define MT6589_PIN_86_GPIO86__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(86) | 5) +#define MT6589_PIN_86_GPIO86__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(86) | 7) + +#define MT6589_PIN_87_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT6589_PIN_87_GPIO87__FUNC_DUAL_BPI1_BUS4 (MTK_PIN_NO(87) | 1) +#define MT6589_PIN_87_GPIO87__FUNC_EINT5 (MTK_PIN_NO(87) | 2) +#define MT6589_PIN_87_GPIO87__FUNC_BPI2_BUS4 (MTK_PIN_NO(87) | 3) +#define MT6589_PIN_87_GPIO87__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(87) | 5) +#define MT6589_PIN_87_GPIO87__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(87) | 7) + +#define MT6589_PIN_88_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT6589_PIN_88_GPIO88__FUNC_DUAL_BPI1_BUS5 (MTK_PIN_NO(88) | 1) +#define MT6589_PIN_88_GPIO88__FUNC_EINT6 (MTK_PIN_NO(88) | 2) +#define MT6589_PIN_88_GPIO88__FUNC_BPI2_BUS5 (MTK_PIN_NO(88) | 3) +#define MT6589_PIN_88_GPIO88__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(88) | 5) +#define MT6589_PIN_88_GPIO88__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(88) | 7) + +#define MT6589_PIN_89_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT6589_PIN_89_GPIO89__FUNC_DUAL_BPI1_BUS6 (MTK_PIN_NO(89) | 1) +#define MT6589_PIN_89_GPIO89__FUNC_EINT7 (MTK_PIN_NO(89) | 2) +#define MT6589_PIN_89_GPIO89__FUNC_BPI2_BUS6 (MTK_PIN_NO(89) | 3) +#define MT6589_PIN_89_GPIO89__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(89) | 5) +#define MT6589_PIN_89_GPIO89__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(89) | 7) + +#define MT6589_PIN_90_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT6589_PIN_90_GPIO90__FUNC_DUAL_BPI1_BUS7 (MTK_PIN_NO(90) | 1) +#define MT6589_PIN_90_GPIO90__FUNC_EINT8 (MTK_PIN_NO(90) | 2) +#define MT6589_PIN_90_GPIO90__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(90) | 3) +#define MT6589_PIN_90_GPIO90__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(90) | 4) +#define MT6589_PIN_90_GPIO90__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(90) | 5) +#define MT6589_PIN_90_GPIO90__FUNC_USB_DRVVBUS (MTK_PIN_NO(90) | 6) +#define MT6589_PIN_90_GPIO90__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(90) | 7) + +#define MT6589_PIN_91_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT6589_PIN_91_GPIO91__FUNC_DUAL_BPI1_BUS8 (MTK_PIN_NO(91) | 1) +#define MT6589_PIN_91_GPIO91__FUNC_EINT9 (MTK_PIN_NO(91) | 2) +#define MT6589_PIN_91_GPIO91__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(91) | 3) +#define MT6589_PIN_91_GPIO91__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(91) | 5) +#define MT6589_PIN_91_GPIO91__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(91) | 7) + +#define MT6589_PIN_92_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT6589_PIN_92_GPIO92__FUNC_DUAL_BPI1_BUS9 (MTK_PIN_NO(92) | 1) +#define MT6589_PIN_92_GPIO92__FUNC_EINT10 (MTK_PIN_NO(92) | 2) +#define MT6589_PIN_92_GPIO92__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(92) | 3) +#define MT6589_PIN_92_GPIO92__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(92) | 5) +#define MT6589_PIN_92_GPIO92__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(92) | 7) + +#define MT6589_PIN_93_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT6589_PIN_93_GPIO93__FUNC_DUAL_BPI1_BUS10 (MTK_PIN_NO(93) | 1) +#define MT6589_PIN_93_GPIO93__FUNC_EINT11 (MTK_PIN_NO(93) | 2) +#define MT6589_PIN_93_GPIO93__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(93) | 5) +#define MT6589_PIN_93_GPIO93__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(93) | 7) + +#define MT6589_PIN_94_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT6589_PIN_94_GPIO94__FUNC_DUAL_BPI1_BUS11 (MTK_PIN_NO(94) | 1) +#define MT6589_PIN_94_GPIO94__FUNC_BPI2_BUS11 (MTK_PIN_NO(94) | 3) +#define MT6589_PIN_94_GPIO94__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(94) | 5) +#define MT6589_PIN_94_GPIO94__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(94) | 7) + +#define MT6589_PIN_95_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT6589_PIN_95_GPIO95__FUNC_DUAL_BPI1_BUS12 (MTK_PIN_NO(95) | 1) +#define MT6589_PIN_95_GPIO95__FUNC_BPI2_BUS12 (MTK_PIN_NO(95) | 3) +#define MT6589_PIN_95_GPIO95__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(95) | 5) +#define MT6589_PIN_95_GPIO95__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(95) | 7) + +#define MT6589_PIN_96_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT6589_PIN_96_GPIO96__FUNC_DUAL_BPI1_BUS13 (MTK_PIN_NO(96) | 1) +#define MT6589_PIN_96_GPIO96__FUNC_BPI2_BUS13 (MTK_PIN_NO(96) | 3) +#define MT6589_PIN_96_GPIO96__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(96) | 5) +#define MT6589_PIN_96_GPIO96__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(96) | 7) + +#define MT6589_PIN_97_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT6589_PIN_97_GPIO97__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(97) | 1) +#define MT6589_PIN_97_GPIO97__FUNC_BPI2_BUS16 (MTK_PIN_NO(97) | 3) +#define MT6589_PIN_97_GPIO97__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(97) | 5) +#define MT6589_PIN_97_GPIO97__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(97) | 7) + +#define MT6589_PIN_98_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT6589_PIN_98_GPIO98__FUNC_DUAL_BPI1_BUS17 (MTK_PIN_NO(98) | 1) +#define MT6589_PIN_98_GPIO98__FUNC_EINT16 (MTK_PIN_NO(98) | 2) +#define MT6589_PIN_98_GPIO98__FUNC_BPI2_BUS17 (MTK_PIN_NO(98) | 3) +#define MT6589_PIN_98_GPIO98__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(98) | 5) +#define MT6589_PIN_98_GPIO98__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(98) | 7) + +#define MT6589_PIN_99_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT6589_PIN_99_GPIO99__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(99) | 1) +#define MT6589_PIN_99_GPIO99__FUNC_EINT17 (MTK_PIN_NO(99) | 2) +#define MT6589_PIN_99_GPIO99__FUNC_BPI2_BUS18 (MTK_PIN_NO(99) | 3) +#define MT6589_PIN_99_GPIO99__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(99) | 5) +#define MT6589_PIN_99_GPIO99__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(99) | 7) + +#define MT6589_PIN_100_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT6589_PIN_100_GPIO100__FUNC_VM1 (MTK_PIN_NO(100) | 1) +#define MT6589_PIN_100_GPIO100__FUNC_EINT19 (MTK_PIN_NO(100) | 2) +#define MT6589_PIN_100_GPIO100__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(100) | 5) +#define MT6589_PIN_100_GPIO100__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(100) | 7) + +#define MT6589_PIN_101_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT6589_PIN_101_GPIO101__FUNC_VM0 (MTK_PIN_NO(101) | 1) +#define MT6589_PIN_101_GPIO101__FUNC_EINT18 (MTK_PIN_NO(101) | 2) +#define MT6589_PIN_101_GPIO101__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(101) | 5) +#define MT6589_PIN_101_GPIO101__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(101) | 7) + +#define MT6589_PIN_102_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT6589_PIN_102_GPIO102__FUNC_BSI1B_CS0 (MTK_PIN_NO(102) | 1) +#define MT6589_PIN_102_GPIO102__FUNC_EINT26 (MTK_PIN_NO(102) | 2) +#define MT6589_PIN_102_GPIO102__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(102) | 5) +#define MT6589_PIN_102_GPIO102__FUNC_MD_ABB_AFUNC_D_21 (MTK_PIN_NO(102) | 6) + +#define MT6589_PIN_103_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT6589_PIN_103_GPIO103__FUNC_BSI1B_DATA0 (MTK_PIN_NO(103) | 1) +#define MT6589_PIN_103_GPIO103__FUNC_EINT27 (MTK_PIN_NO(103) | 2) +#define MT6589_PIN_103_GPIO103__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(103) | 5) +#define MT6589_PIN_103_GPIO103__FUNC_MD_ABB_AFUNC_D_22 (MTK_PIN_NO(103) | 6) + +#define MT6589_PIN_104_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT6589_PIN_104_GPIO104__FUNC_BSI1B_CLK (MTK_PIN_NO(104) | 1) +#define MT6589_PIN_104_GPIO104__FUNC_EINT25 (MTK_PIN_NO(104) | 2) +#define MT6589_PIN_104_GPIO104__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(104) | 5) +#define MT6589_PIN_104_GPIO104__FUNC_MD_ABB_AFUNC_D_23 (MTK_PIN_NO(104) | 6) + +#define MT6589_PIN_105_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT6589_PIN_105_GPIO105__FUNC_TXBPI1 (MTK_PIN_NO(105) | 1) +#define MT6589_PIN_105_GPIO105__FUNC_EINT30 (MTK_PIN_NO(105) | 2) + +#define MT6589_PIN_106_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT6589_PIN_106_GPIO106__FUNC_EXT_CLK_EN (MTK_PIN_NO(106) | 1) + +#define MT6589_PIN_107_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT6589_PIN_107_GPIO107__FUNC_SRCLKENA2 (MTK_PIN_NO(107) | 1) +#define MT6589_PIN_107_GPIO107__FUNC_EINT39 (MTK_PIN_NO(107) | 2) + +#define MT6589_PIN_108_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT6589_PIN_108_GPIO108__FUNC_BSI1A_CS0 (MTK_PIN_NO(108) | 1) +#define MT6589_PIN_108_GPIO108__FUNC_EINT21 (MTK_PIN_NO(108) | 2) +#define MT6589_PIN_108_GPIO108__FUNC_BSI2_CS (MTK_PIN_NO(108) | 3) +#define MT6589_PIN_108_GPIO108__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +#define MT6589_PIN_108_GPIO108__FUNC_MD_ABB_AFUNC_D_24 (MTK_PIN_NO(108) | 6) + +#define MT6589_PIN_109_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT6589_PIN_109_GPIO109__FUNC_BSI1A_DATA2 (MTK_PIN_NO(109) | 1) +#define MT6589_PIN_109_GPIO109__FUNC_EINT24 (MTK_PIN_NO(109) | 2) +#define MT6589_PIN_109_GPIO109__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +#define MT6589_PIN_109_GPIO109__FUNC_MD_ABB_AFUNC_D_25 (MTK_PIN_NO(109) | 6) + +#define MT6589_PIN_110_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT6589_PIN_110_GPIO110__FUNC_BSI1A_DATA1 (MTK_PIN_NO(110) | 1) +#define MT6589_PIN_110_GPIO110__FUNC_EINT23 (MTK_PIN_NO(110) | 2) +#define MT6589_PIN_110_GPIO110__FUNC_BSI2_DATA1 (MTK_PIN_NO(110) | 3) +#define MT6589_PIN_110_GPIO110__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +#define MT6589_PIN_110_GPIO110__FUNC_MD_ABB_AFUNC_D_26 (MTK_PIN_NO(110) | 6) + +#define MT6589_PIN_111_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT6589_PIN_111_GPIO111__FUNC_BSI1A_DATA0 (MTK_PIN_NO(111) | 1) +#define MT6589_PIN_111_GPIO111__FUNC_EINT22 (MTK_PIN_NO(111) | 2) +#define MT6589_PIN_111_GPIO111__FUNC_BSI2_DATA0 (MTK_PIN_NO(111) | 3) +#define MT6589_PIN_111_GPIO111__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +#define MT6589_PIN_111_GPIO111__FUNC_MD_ABB_AFUNC_D_27 (MTK_PIN_NO(111) | 6) + +#define MT6589_PIN_112_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT6589_PIN_112_GPIO112__FUNC_BSI1A_CLK (MTK_PIN_NO(112) | 1) +#define MT6589_PIN_112_GPIO112__FUNC_EINT20 (MTK_PIN_NO(112) | 2) +#define MT6589_PIN_112_GPIO112__FUNC_BSI2_CLK (MTK_PIN_NO(112) | 3) +#define MT6589_PIN_112_GPIO112__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +#define MT6589_PIN_112_GPIO112__FUNC_MD_ABB_AFUNC_D_28 (MTK_PIN_NO(112) | 6) + +#define MT6589_PIN_113_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT6589_PIN_113_GPIO113__FUNC_BSI1C_DATA (MTK_PIN_NO(113) | 1) +#define MT6589_PIN_113_GPIO113__FUNC_EINT29 (MTK_PIN_NO(113) | 2) +#define MT6589_PIN_113_GPIO113__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(113) | 3) +#define MT6589_PIN_113_GPIO113__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(113) | 4) +#define MT6589_PIN_113_GPIO113__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(113) | 5) +#define MT6589_PIN_113_GPIO113__FUNC_MD_ABB_AFUNC_D_29 (MTK_PIN_NO(113) | 6) +#define MT6589_PIN_113_GPIO113__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 7) + +#define MT6589_PIN_114_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT6589_PIN_114_GPIO114__FUNC_BSI1C_CLK (MTK_PIN_NO(114) | 1) +#define MT6589_PIN_114_GPIO114__FUNC_EINT28 (MTK_PIN_NO(114) | 2) +#define MT6589_PIN_114_GPIO114__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(114) | 5) +#define MT6589_PIN_114_GPIO114__FUNC_MD_ABB_AFUNC_D_30 (MTK_PIN_NO(114) | 6) + +#define MT6589_PIN_115_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT6589_PIN_115_GPIO115__FUNC_EINT10 (MTK_PIN_NO(115) | 1) +#define MT6589_PIN_115_GPIO115__FUNC_MD_ABB_AFUNC_D_31 (MTK_PIN_NO(115) | 6) + +#define MT6589_PIN_116_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT6589_PIN_116_GPIO116__FUNC_EINT11 (MTK_PIN_NO(116) | 1) +#define MT6589_PIN_116_GPIO116__FUNC_MD_ABB_AFUNC_D_32 (MTK_PIN_NO(116) | 6) + +#define MT6589_PIN_117_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT6589_PIN_117_GPIO117__FUNC_EINT16 (MTK_PIN_NO(117) | 1) +#define MT6589_PIN_117_GPIO117__FUNC_MD_ABB_AFUNC_D_33 (MTK_PIN_NO(117) | 6) + +#define MT6589_PIN_118_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT6589_PIN_118_GPIO118__FUNC_SDA0 (MTK_PIN_NO(118) | 1) +#define MT6589_PIN_118_GPIO118__FUNC_EINT91 (MTK_PIN_NO(118) | 2) +#define MT6589_PIN_118_GPIO118__FUNC_CLKM1 (MTK_PIN_NO(118) | 3) +#define MT6589_PIN_118_GPIO118__FUNC_PWM1 (MTK_PIN_NO(118) | 4) +#define MT6589_PIN_118_GPIO118__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(118) | 7) + +#define MT6589_PIN_119_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT6589_PIN_119_GPIO119__FUNC_SCL0 (MTK_PIN_NO(119) | 1) +#define MT6589_PIN_119_GPIO119__FUNC_EINT90 (MTK_PIN_NO(119) | 2) +#define MT6589_PIN_119_GPIO119__FUNC_CLKM0 (MTK_PIN_NO(119) | 3) +#define MT6589_PIN_119_GPIO119__FUNC_DISP_PWM (MTK_PIN_NO(119) | 4) +#define MT6589_PIN_119_GPIO119__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(119) | 7) + +#define MT6589_PIN_120_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT6589_PIN_120_GPIO120__FUNC_I2SIN_CK (MTK_PIN_NO(120) | 1) +#define MT6589_PIN_120_GPIO120__FUNC_EINT10 (MTK_PIN_NO(120) | 2) +#define MT6589_PIN_120_GPIO120__FUNC_DAC_CK (MTK_PIN_NO(120) | 3) +#define MT6589_PIN_120_GPIO120__FUNC_PCM1_CK (MTK_PIN_NO(120) | 4) +#define MT6589_PIN_120_GPIO120__FUNC_DSP1_ICK (MTK_PIN_NO(120) | 5) +#define MT6589_PIN_120_GPIO120__FUNC_MD_ABB_AFUNC_D_34 (MTK_PIN_NO(120) | 6) + +#define MT6589_PIN_121_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT6589_PIN_121_GPIO121__FUNC_I2SIN_WS (MTK_PIN_NO(121) | 1) +#define MT6589_PIN_121_GPIO121__FUNC_DAC_WS (MTK_PIN_NO(121) | 3) +#define MT6589_PIN_121_GPIO121__FUNC_PCM1_WS (MTK_PIN_NO(121) | 4) +#define MT6589_PIN_121_GPIO121__FUNC_DSP1_ID (MTK_PIN_NO(121) | 5) +#define MT6589_PIN_121_GPIO121__FUNC_MD_ABB_AFUNC_D_35 (MTK_PIN_NO(121) | 6) + +#define MT6589_PIN_122_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT6589_PIN_122_GPIO122__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 1) +#define MT6589_PIN_122_GPIO122__FUNC_EINT11 (MTK_PIN_NO(122) | 2) +#define MT6589_PIN_122_GPIO122__FUNC_PCM1_DI (MTK_PIN_NO(122) | 4) +#define MT6589_PIN_122_GPIO122__FUNC_DSP1_IMS (MTK_PIN_NO(122) | 5) +#define MT6589_PIN_122_GPIO122__FUNC_MD_ABB_AFUNC_D_36 (MTK_PIN_NO(122) | 6) + +#define MT6589_PIN_123_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT6589_PIN_123_GPIO123__FUNC_I2SOUT_DAT (MTK_PIN_NO(123) | 1) +#define MT6589_PIN_123_GPIO123__FUNC_DAC_DAT_OUT (MTK_PIN_NO(123) | 3) +#define MT6589_PIN_123_GPIO123__FUNC_PCM1_DO (MTK_PIN_NO(123) | 4) +#define MT6589_PIN_123_GPIO123__FUNC_MD2_EINT5 (MTK_PIN_NO(123) | 5) +#define MT6589_PIN_123_GPIO123__FUNC_MD_ABB_AFUNC_D_37 (MTK_PIN_NO(123) | 6) + +#define MT6589_PIN_124_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT6589_PIN_124_GPIO124__FUNC_EINT5 (MTK_PIN_NO(124) | 1) +#define MT6589_PIN_124_GPIO124__FUNC_PWM5 (MTK_PIN_NO(124) | 2) +#define MT6589_PIN_124_GPIO124__FUNC_CLKM3 (MTK_PIN_NO(124) | 3) +#define MT6589_PIN_124_GPIO124__FUNC_MD1_UTXD (MTK_PIN_NO(124) | 4) +#define MT6589_PIN_124_GPIO124__FUNC_MD2_EINT1 (MTK_PIN_NO(124) | 5) +#define MT6589_PIN_124_GPIO124__FUNC_MD_ABB_AFUNC_D_38 (MTK_PIN_NO(124) | 6) + +#define MT6589_PIN_125_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT6589_PIN_125_GPIO125__FUNC_EINT6 (MTK_PIN_NO(125) | 1) +#define MT6589_PIN_125_GPIO125__FUNC_PWM6 (MTK_PIN_NO(125) | 2) +#define MT6589_PIN_125_GPIO125__FUNC_CLKM4 (MTK_PIN_NO(125) | 3) +#define MT6589_PIN_125_GPIO125__FUNC_MD1_URXD (MTK_PIN_NO(125) | 4) +#define MT6589_PIN_125_GPIO125__FUNC_MD2_EINT2 (MTK_PIN_NO(125) | 5) +#define MT6589_PIN_125_GPIO125__FUNC_MD_ABB_AFUNC_D_39 (MTK_PIN_NO(125) | 6) + +#define MT6589_PIN_126_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT6589_PIN_126_GPIO126__FUNC_EINT7 (MTK_PIN_NO(126) | 1) +#define MT6589_PIN_126_GPIO126__FUNC_PWM7 (MTK_PIN_NO(126) | 2) +#define MT6589_PIN_126_GPIO126__FUNC_CLKM5 (MTK_PIN_NO(126) | 3) +#define MT6589_PIN_126_GPIO126__FUNC_SRCLKENAI2 (MTK_PIN_NO(126) | 4) +#define MT6589_PIN_126_GPIO126__FUNC_MD2_EINT3 (MTK_PIN_NO(126) | 5) +#define MT6589_PIN_126_GPIO126__FUNC_MD_ABB_AFUNC_D_40 (MTK_PIN_NO(126) | 6) + +#define MT6589_PIN_127_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT6589_PIN_127_GPIO127__FUNC_EINT8 (MTK_PIN_NO(127) | 1) +#define MT6589_PIN_127_GPIO127__FUNC_DISP_PWM (MTK_PIN_NO(127) | 2) +#define MT6589_PIN_127_GPIO127__FUNC_CLKM6 (MTK_PIN_NO(127) | 3) +#define MT6589_PIN_127_GPIO127__FUNC_MD2_EINT4 (MTK_PIN_NO(127) | 5) +#define MT6589_PIN_127_GPIO127__FUNC_MD_ABB_AFUNC_D_41 (MTK_PIN_NO(127) | 6) +#define MT6589_PIN_127_GPIO127__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(127) | 7) + +#define MT6589_PIN_128_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT6589_PIN_128_GPIO128__FUNC_EINT9 (MTK_PIN_NO(128) | 1) +#define MT6589_PIN_128_GPIO128__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(128) | 3) +#define MT6589_PIN_128_GPIO128__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(128) | 4) +#define MT6589_PIN_128_GPIO128__FUNC_USB_DRVVBUS (MTK_PIN_NO(128) | 5) +#define MT6589_PIN_128_GPIO128__FUNC_MD_ABB_AFUNC_D_42 (MTK_PIN_NO(128) | 6) + +#define MT6589_PIN_129_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT6589_PIN_129_GPIO129__FUNC_DISP_PWM (MTK_PIN_NO(129) | 1) +#define MT6589_PIN_129_GPIO129__FUNC_EINT77 (MTK_PIN_NO(129) | 2) +#define MT6589_PIN_129_GPIO129__FUNC_LSDI (MTK_PIN_NO(129) | 3) +#define MT6589_PIN_129_GPIO129__FUNC_PWM1 (MTK_PIN_NO(129) | 4) +#define MT6589_PIN_129_GPIO129__FUNC_PWM2 (MTK_PIN_NO(129) | 5) +#define MT6589_PIN_129_GPIO129__FUNC_MD_ABB_AFUNC_D_43 (MTK_PIN_NO(129) | 6) +#define MT6589_PIN_129_GPIO129__FUNC_PWM3 (MTK_PIN_NO(129) | 7) + +#define MT6589_PIN_130_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT6589_PIN_130_GPIO130__FUNC_MSDC4_DAT0 (MTK_PIN_NO(130) | 1) +#define MT6589_PIN_130_GPIO130__FUNC_EINT133 (MTK_PIN_NO(130) | 2) +#define MT6589_PIN_130_GPIO130__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(130) | 4) +#define MT6589_PIN_130_GPIO130__FUNC_USB_DRVVBUS (MTK_PIN_NO(130) | 5) +#define MT6589_PIN_130_GPIO130__FUNC_MD_ABB_AFUNC_D_46 (MTK_PIN_NO(130) | 6) +#define MT6589_PIN_130_GPIO130__FUNC_LPTE (MTK_PIN_NO(130) | 7) + +#define MT6589_PIN_131_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT6589_PIN_131_GPIO131__FUNC_MSDC4_DAT1 (MTK_PIN_NO(131) | 1) +#define MT6589_PIN_131_GPIO131__FUNC_EINT134 (MTK_PIN_NO(131) | 2) +#define MT6589_PIN_131_GPIO131__FUNC_MD_ABB_AFUNC_D_47 (MTK_PIN_NO(131) | 6) +#define MT6589_PIN_131_GPIO131__FUNC_LRSTB_1X (MTK_PIN_NO(131) | 7) + +#define MT6589_PIN_132_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT6589_PIN_132_GPIO132__FUNC_LPCE1B (MTK_PIN_NO(132) | 1) +#define MT6589_PIN_132_GPIO132__FUNC_EINT127 (MTK_PIN_NO(132) | 2) +#define MT6589_PIN_132_GPIO132__FUNC_DPI1_HSYNC_2X (MTK_PIN_NO(132) | 3) +#define MT6589_PIN_132_GPIO132__FUNC_PWM2 (MTK_PIN_NO(132) | 5) +#define MT6589_PIN_132_GPIO132__FUNC_MD_ABB_AFUNC_D_44 (MTK_PIN_NO(132) | 6) + +#define MT6589_PIN_133_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT6589_PIN_133_GPIO133__FUNC_LPCE0B (MTK_PIN_NO(133) | 1) +#define MT6589_PIN_133_GPIO133__FUNC_EINT126 (MTK_PIN_NO(133) | 2) +#define MT6589_PIN_133_GPIO133__FUNC_DPI1_VSYNC_2X (MTK_PIN_NO(133) | 3) +#define MT6589_PIN_133_GPIO133__FUNC_PWM1 (MTK_PIN_NO(133) | 5) +#define MT6589_PIN_133_GPIO133__FUNC_MD_ABB_AFUNC_D_45 (MTK_PIN_NO(133) | 6) + +#define MT6589_PIN_134_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT6589_PIN_134_GPIO134__FUNC_MSDC4_DAT5 (MTK_PIN_NO(134) | 1) +#define MT6589_PIN_134_GPIO134__FUNC_EINT136 (MTK_PIN_NO(134) | 2) +#define MT6589_PIN_134_GPIO134__FUNC_I2SIN_WS (MTK_PIN_NO(134) | 3) +#define MT6589_PIN_134_GPIO134__FUNC_DAC_WS (MTK_PIN_NO(134) | 4) +#define MT6589_PIN_134_GPIO134__FUNC_PCM1_WS (MTK_PIN_NO(134) | 5) +#define MT6589_PIN_134_GPIO134__FUNC_MD_ABB_AFUNC_D_48 (MTK_PIN_NO(134) | 6) +#define MT6589_PIN_134_GPIO134__FUNC_SPI1_CSN (MTK_PIN_NO(134) | 7) + +#define MT6589_PIN_135_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT6589_PIN_135_GPIO135__FUNC_MSDC4_DAT6 (MTK_PIN_NO(135) | 1) +#define MT6589_PIN_135_GPIO135__FUNC_EINT137 (MTK_PIN_NO(135) | 2) +#define MT6589_PIN_135_GPIO135__FUNC_I2SOUT_DAT (MTK_PIN_NO(135) | 3) +#define MT6589_PIN_135_GPIO135__FUNC_DAC_DAT_OUT (MTK_PIN_NO(135) | 4) +#define MT6589_PIN_135_GPIO135__FUNC_PCM1_DO (MTK_PIN_NO(135) | 5) +#define MT6589_PIN_135_GPIO135__FUNC_MD_ABB_AFUNC_D_49 (MTK_PIN_NO(135) | 6) +#define MT6589_PIN_135_GPIO135__FUNC_SPI1_MO (MTK_PIN_NO(135) | 7) + +#define MT6589_PIN_136_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT6589_PIN_136_GPIO136__FUNC_MSDC4_DAT7 (MTK_PIN_NO(136) | 1) +#define MT6589_PIN_136_GPIO136__FUNC_EINT138 (MTK_PIN_NO(136) | 2) +#define MT6589_PIN_136_GPIO136__FUNC_I2SIN_DAT (MTK_PIN_NO(136) | 3) +#define MT6589_PIN_136_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 5) +#define MT6589_PIN_136_GPIO136__FUNC_MD_ABB_AFUNC_D_50 (MTK_PIN_NO(136) | 6) +#define MT6589_PIN_136_GPIO136__FUNC_SPI1_MI (MTK_PIN_NO(136) | 7) + +#define MT6589_PIN_137_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT6589_PIN_137_GPIO137__FUNC_MSDC4_DAT4 (MTK_PIN_NO(137) | 1) +#define MT6589_PIN_137_GPIO137__FUNC_EINT135 (MTK_PIN_NO(137) | 2) +#define MT6589_PIN_137_GPIO137__FUNC_I2SIN_CK (MTK_PIN_NO(137) | 3) +#define MT6589_PIN_137_GPIO137__FUNC_DAC_CK (MTK_PIN_NO(137) | 4) +#define MT6589_PIN_137_GPIO137__FUNC_PCM1_CK (MTK_PIN_NO(137) | 5) +#define MT6589_PIN_137_GPIO137__FUNC_MD_ABB_AFUNC_D_51 (MTK_PIN_NO(137) | 6) +#define MT6589_PIN_137_GPIO137__FUNC_SPI1_CLK (MTK_PIN_NO(137) | 7) + +#define MT6589_PIN_138_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT6589_PIN_138_GPIO138__FUNC_MSDC4_DAT2 (MTK_PIN_NO(138) | 1) +#define MT6589_PIN_138_GPIO138__FUNC_EINT131 (MTK_PIN_NO(138) | 2) +#define MT6589_PIN_138_GPIO138__FUNC_I2SIN_WS (MTK_PIN_NO(138) | 3) +#define MT6589_PIN_138_GPIO138__FUNC_CM2PDN_2X (MTK_PIN_NO(138) | 4) +#define MT6589_PIN_138_GPIO138__FUNC_DAC_WS (MTK_PIN_NO(138) | 5) +#define MT6589_PIN_138_GPIO138__FUNC_PCM1_WS (MTK_PIN_NO(138) | 6) +#define MT6589_PIN_138_GPIO138__FUNC_LSCE0B_1X (MTK_PIN_NO(138) | 7) + +#define MT6589_PIN_139_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT6589_PIN_139_GPIO139__FUNC_MSDC4_CLK (MTK_PIN_NO(139) | 1) +#define MT6589_PIN_139_GPIO139__FUNC_EINT129 (MTK_PIN_NO(139) | 2) +#define MT6589_PIN_139_GPIO139__FUNC_DPI1_CK_2X (MTK_PIN_NO(139) | 3) +#define MT6589_PIN_139_GPIO139__FUNC_CM2PCLK_2X (MTK_PIN_NO(139) | 4) +#define MT6589_PIN_139_GPIO139__FUNC_PWM4 (MTK_PIN_NO(139) | 5) +#define MT6589_PIN_139_GPIO139__FUNC_PCM1_DI (MTK_PIN_NO(139) | 6) +#define MT6589_PIN_139_GPIO139__FUNC_LSCK_1X (MTK_PIN_NO(139) | 7) + +#define MT6589_PIN_140_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT6589_PIN_140_GPIO140__FUNC_MSDC4_DAT3 (MTK_PIN_NO(140) | 1) +#define MT6589_PIN_140_GPIO140__FUNC_EINT132 (MTK_PIN_NO(140) | 2) +#define MT6589_PIN_140_GPIO140__FUNC_I2SOUT_DAT (MTK_PIN_NO(140) | 3) +#define MT6589_PIN_140_GPIO140__FUNC_CM2RST_2X (MTK_PIN_NO(140) | 4) +#define MT6589_PIN_140_GPIO140__FUNC_DAC_DAT_OUT (MTK_PIN_NO(140) | 5) +#define MT6589_PIN_140_GPIO140__FUNC_PCM1_DO (MTK_PIN_NO(140) | 6) +#define MT6589_PIN_140_GPIO140__FUNC_LSCE1B_1X (MTK_PIN_NO(140) | 7) + +#define MT6589_PIN_141_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT6589_PIN_141_GPIO141__FUNC_MSDC4_CMD (MTK_PIN_NO(141) | 1) +#define MT6589_PIN_141_GPIO141__FUNC_EINT128 (MTK_PIN_NO(141) | 2) +#define MT6589_PIN_141_GPIO141__FUNC_DPI1_DE_2X (MTK_PIN_NO(141) | 3) +#define MT6589_PIN_141_GPIO141__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(141) | 4) +#define MT6589_PIN_141_GPIO141__FUNC_PWM3 (MTK_PIN_NO(141) | 5) +#define MT6589_PIN_141_GPIO141__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(141) | 6) +#define MT6589_PIN_141_GPIO141__FUNC_LSDA_1X (MTK_PIN_NO(141) | 7) + +#define MT6589_PIN_142_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT6589_PIN_142_GPIO142__FUNC_MSDC4_RSTB (MTK_PIN_NO(142) | 1) +#define MT6589_PIN_142_GPIO142__FUNC_EINT130 (MTK_PIN_NO(142) | 2) +#define MT6589_PIN_142_GPIO142__FUNC_I2SIN_CK (MTK_PIN_NO(142) | 3) +#define MT6589_PIN_142_GPIO142__FUNC_CM2MCLK_2X (MTK_PIN_NO(142) | 4) +#define MT6589_PIN_142_GPIO142__FUNC_DAC_CK (MTK_PIN_NO(142) | 5) +#define MT6589_PIN_142_GPIO142__FUNC_PCM1_CK (MTK_PIN_NO(142) | 6) +#define MT6589_PIN_142_GPIO142__FUNC_LSA0_1X (MTK_PIN_NO(142) | 7) + +#define MT6589_PIN_143_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT6589_PIN_143_GPIO143__FUNC_DPI0_VSYNC (MTK_PIN_NO(143) | 1) +#define MT6589_PIN_143_GPIO143__FUNC_EINT98 (MTK_PIN_NO(143) | 2) +#define MT6589_PIN_143_GPIO143__FUNC_I2SIN_CK (MTK_PIN_NO(143) | 3) +#define MT6589_PIN_143_GPIO143__FUNC_DAC_CK (MTK_PIN_NO(143) | 4) +#define MT6589_PIN_143_GPIO143__FUNC_PCM1_CK (MTK_PIN_NO(143) | 5) +#define MT6589_PIN_143_GPIO143__FUNC_MD_ABB_AFUNC_D_52 (MTK_PIN_NO(143) | 6) +#define MT6589_PIN_143_GPIO143__FUNC_TESTB_OUT8 (MTK_PIN_NO(143) | 7) + +#define MT6589_PIN_144_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT6589_PIN_144_GPIO144__FUNC_DPI0_HSYNC (MTK_PIN_NO(144) | 1) +#define MT6589_PIN_144_GPIO144__FUNC_EINT99 (MTK_PIN_NO(144) | 2) +#define MT6589_PIN_144_GPIO144__FUNC_I2SIN_WS (MTK_PIN_NO(144) | 3) +#define MT6589_PIN_144_GPIO144__FUNC_DAC_WS (MTK_PIN_NO(144) | 4) +#define MT6589_PIN_144_GPIO144__FUNC_PCM1_WS (MTK_PIN_NO(144) | 5) +#define MT6589_PIN_144_GPIO144__FUNC_IRDA_RXD (MTK_PIN_NO(144) | 6) +#define MT6589_PIN_144_GPIO144__FUNC_TESTB_OUT9 (MTK_PIN_NO(144) | 7) + +#define MT6589_PIN_145_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT6589_PIN_145_GPIO145__FUNC_DPI0_DE (MTK_PIN_NO(145) | 1) +#define MT6589_PIN_145_GPIO145__FUNC_EINT100 (MTK_PIN_NO(145) | 2) +#define MT6589_PIN_145_GPIO145__FUNC_I2SOUT_DAT (MTK_PIN_NO(145) | 3) +#define MT6589_PIN_145_GPIO145__FUNC_DAC_DAT_OUT (MTK_PIN_NO(145) | 4) +#define MT6589_PIN_145_GPIO145__FUNC_PCM1_DO (MTK_PIN_NO(145) | 5) +#define MT6589_PIN_145_GPIO145__FUNC_IRDA_TXD (MTK_PIN_NO(145) | 6) +#define MT6589_PIN_145_GPIO145__FUNC_TESTB_OUT10 (MTK_PIN_NO(145) | 7) + +#define MT6589_PIN_146_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT6589_PIN_146_GPIO146__FUNC_DPI0_CK (MTK_PIN_NO(146) | 1) +#define MT6589_PIN_146_GPIO146__FUNC_EINT101 (MTK_PIN_NO(146) | 2) +#define MT6589_PIN_146_GPIO146__FUNC_I2SIN_DAT (MTK_PIN_NO(146) | 3) +#define MT6589_PIN_146_GPIO146__FUNC_PCM1_DI (MTK_PIN_NO(146) | 5) +#define MT6589_PIN_146_GPIO146__FUNC_IRDA_PDN (MTK_PIN_NO(146) | 6) +#define MT6589_PIN_146_GPIO146__FUNC_TESTB_OUT11 (MTK_PIN_NO(146) | 7) + +#define MT6589_PIN_147_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT6589_PIN_147_GPIO147__FUNC_DPI0_B0 (MTK_PIN_NO(147) | 1) +#define MT6589_PIN_147_GPIO147__FUNC_EINT102 (MTK_PIN_NO(147) | 2) +#define MT6589_PIN_147_GPIO147__FUNC_SCL0 (MTK_PIN_NO(147) | 4) +#define MT6589_PIN_147_GPIO147__FUNC_DISP_PWM (MTK_PIN_NO(147) | 5) +#define MT6589_PIN_147_GPIO147__FUNC_MD_ABB_AFUNC_D_57 (MTK_PIN_NO(147) | 6) +#define MT6589_PIN_147_GPIO147__FUNC_TESTB_OUT12 (MTK_PIN_NO(147) | 7) + +#define MT6589_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT6589_PIN_148_GPIO148__FUNC_DPI0_B1 (MTK_PIN_NO(148) | 1) +#define MT6589_PIN_148_GPIO148__FUNC_EINT103 (MTK_PIN_NO(148) | 2) +#define MT6589_PIN_148_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 3) +#define MT6589_PIN_148_GPIO148__FUNC_SDA0 (MTK_PIN_NO(148) | 4) +#define MT6589_PIN_148_GPIO148__FUNC_PWM1 (MTK_PIN_NO(148) | 5) +#define MT6589_PIN_148_GPIO148__FUNC_MD_ABB_AFUNC_D_58 (MTK_PIN_NO(148) | 6) +#define MT6589_PIN_148_GPIO148__FUNC_TESTB_OUT13 (MTK_PIN_NO(148) | 7) + +#define MT6589_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT6589_PIN_149_GPIO149__FUNC_DPI0_B2 (MTK_PIN_NO(149) | 1) +#define MT6589_PIN_149_GPIO149__FUNC_EINT104 (MTK_PIN_NO(149) | 2) +#define MT6589_PIN_149_GPIO149__FUNC_CLKM1 (MTK_PIN_NO(149) | 3) +#define MT6589_PIN_149_GPIO149__FUNC_SCL1 (MTK_PIN_NO(149) | 4) +#define MT6589_PIN_149_GPIO149__FUNC_PWM2 (MTK_PIN_NO(149) | 5) +#define MT6589_PIN_149_GPIO149__FUNC_MD_ABB_AFUNC_D_59 (MTK_PIN_NO(149) | 6) +#define MT6589_PIN_149_GPIO149__FUNC_TESTB_OUT14 (MTK_PIN_NO(149) | 7) + +#define MT6589_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT6589_PIN_150_GPIO150__FUNC_DPI0_B3 (MTK_PIN_NO(150) | 1) +#define MT6589_PIN_150_GPIO150__FUNC_EINT105 (MTK_PIN_NO(150) | 2) +#define MT6589_PIN_150_GPIO150__FUNC_CLKM2 (MTK_PIN_NO(150) | 3) +#define MT6589_PIN_150_GPIO150__FUNC_SDA1 (MTK_PIN_NO(150) | 4) +#define MT6589_PIN_150_GPIO150__FUNC_PWM3 (MTK_PIN_NO(150) | 5) +#define MT6589_PIN_150_GPIO150__FUNC_MD_ABB_AFUNC_D_60 (MTK_PIN_NO(150) | 6) +#define MT6589_PIN_150_GPIO150__FUNC_TESTB_OUT15 (MTK_PIN_NO(150) | 7) + +#define MT6589_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT6589_PIN_151_GPIO151__FUNC_DPI0_B4 (MTK_PIN_NO(151) | 1) +#define MT6589_PIN_151_GPIO151__FUNC_EINT106 (MTK_PIN_NO(151) | 2) +#define MT6589_PIN_151_GPIO151__FUNC_CLKM3 (MTK_PIN_NO(151) | 3) +#define MT6589_PIN_151_GPIO151__FUNC_SCL2 (MTK_PIN_NO(151) | 4) +#define MT6589_PIN_151_GPIO151__FUNC_PWM4 (MTK_PIN_NO(151) | 5) +#define MT6589_PIN_151_GPIO151__FUNC_MD_ABB_AFUNC_D_61 (MTK_PIN_NO(151) | 6) +#define MT6589_PIN_151_GPIO151__FUNC_TESTB_OUT16 (MTK_PIN_NO(151) | 7) + +#define MT6589_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT6589_PIN_152_GPIO152__FUNC_DPI0_B5 (MTK_PIN_NO(152) | 1) +#define MT6589_PIN_152_GPIO152__FUNC_EINT107 (MTK_PIN_NO(152) | 2) +#define MT6589_PIN_152_GPIO152__FUNC_CLKM4 (MTK_PIN_NO(152) | 3) +#define MT6589_PIN_152_GPIO152__FUNC_SDA2 (MTK_PIN_NO(152) | 4) +#define MT6589_PIN_152_GPIO152__FUNC_PWM5 (MTK_PIN_NO(152) | 5) +#define MT6589_PIN_152_GPIO152__FUNC_MD_ABB_AFUNC_D_62 (MTK_PIN_NO(152) | 6) +#define MT6589_PIN_152_GPIO152__FUNC_TESTB_OUT17 (MTK_PIN_NO(152) | 7) + +#define MT6589_PIN_153_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT6589_PIN_153_GPIO153__FUNC_DPI0_B6 (MTK_PIN_NO(153) | 1) +#define MT6589_PIN_153_GPIO153__FUNC_EINT108 (MTK_PIN_NO(153) | 2) +#define MT6589_PIN_153_GPIO153__FUNC_CLKM5 (MTK_PIN_NO(153) | 3) +#define MT6589_PIN_153_GPIO153__FUNC_SCL3 (MTK_PIN_NO(153) | 4) +#define MT6589_PIN_153_GPIO153__FUNC_PWM6 (MTK_PIN_NO(153) | 5) +#define MT6589_PIN_153_GPIO153__FUNC_MD_ABB_AFUNC_D_63 (MTK_PIN_NO(153) | 6) +#define MT6589_PIN_153_GPIO153__FUNC_TESTB_OUT18 (MTK_PIN_NO(153) | 7) + +#define MT6589_PIN_154_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT6589_PIN_154_GPIO154__FUNC_DPI0_B7 (MTK_PIN_NO(154) | 1) +#define MT6589_PIN_154_GPIO154__FUNC_EINT109 (MTK_PIN_NO(154) | 2) +#define MT6589_PIN_154_GPIO154__FUNC_CLKM6 (MTK_PIN_NO(154) | 3) +#define MT6589_PIN_154_GPIO154__FUNC_SDA3 (MTK_PIN_NO(154) | 4) +#define MT6589_PIN_154_GPIO154__FUNC_PWM7 (MTK_PIN_NO(154) | 5) +#define MT6589_PIN_154_GPIO154__FUNC_MD1_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(154) | 6) +#define MT6589_PIN_154_GPIO154__FUNC_TESTB_OUT19 (MTK_PIN_NO(154) | 7) + +#define MT6589_PIN_155_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT6589_PIN_155_GPIO155__FUNC_DPI0_G0 (MTK_PIN_NO(155) | 1) +#define MT6589_PIN_155_GPIO155__FUNC_EINT110 (MTK_PIN_NO(155) | 2) +#define MT6589_PIN_155_GPIO155__FUNC_DSP1_ID (MTK_PIN_NO(155) | 5) +#define MT6589_PIN_155_GPIO155__FUNC_MD1_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(155) | 6) +#define MT6589_PIN_155_GPIO155__FUNC_TESTB_OUT20 (MTK_PIN_NO(155) | 7) + +#define MT6589_PIN_156_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT6589_PIN_156_GPIO156__FUNC_DPI0_G1 (MTK_PIN_NO(156) | 1) +#define MT6589_PIN_156_GPIO156__FUNC_EINT111 (MTK_PIN_NO(156) | 2) +#define MT6589_PIN_156_GPIO156__FUNC_DSP1_ICK (MTK_PIN_NO(156) | 5) +#define MT6589_PIN_156_GPIO156__FUNC_MD_ABB_AFUNC_D_56 (MTK_PIN_NO(156) | 6) +#define MT6589_PIN_156_GPIO156__FUNC_TESTB_OUT21 (MTK_PIN_NO(156) | 7) + +#define MT6589_PIN_157_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT6589_PIN_157_GPIO157__FUNC_DPI0_G2 (MTK_PIN_NO(157) | 1) +#define MT6589_PIN_157_GPIO157__FUNC_EINT112 (MTK_PIN_NO(157) | 2) +#define MT6589_PIN_157_GPIO157__FUNC_DSP1_IMS (MTK_PIN_NO(157) | 5) +#define MT6589_PIN_157_GPIO157__FUNC_MD1_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(157) | 6) +#define MT6589_PIN_157_GPIO157__FUNC_TESTB_OUT22 (MTK_PIN_NO(157) | 7) + +#define MT6589_PIN_158_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT6589_PIN_158_GPIO158__FUNC_DPI0_G3 (MTK_PIN_NO(158) | 1) +#define MT6589_PIN_158_GPIO158__FUNC_EINT113 (MTK_PIN_NO(158) | 2) +#define MT6589_PIN_158_GPIO158__FUNC_DSP2_IMS (MTK_PIN_NO(158) | 5) +#define MT6589_PIN_158_GPIO158__FUNC_MD1_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(158) | 6) +#define MT6589_PIN_158_GPIO158__FUNC_TESTB_OUT23 (MTK_PIN_NO(158) | 7) + +#define MT6589_PIN_159_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT6589_PIN_159_GPIO159__FUNC_DPI0_G4 (MTK_PIN_NO(159) | 1) +#define MT6589_PIN_159_GPIO159__FUNC_EINT114 (MTK_PIN_NO(159) | 2) +#define MT6589_PIN_159_GPIO159__FUNC_DPI1_D_2X_0 (MTK_PIN_NO(159) | 3) +#define MT6589_PIN_159_GPIO159__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(159) | 4) +#define MT6589_PIN_159_GPIO159__FUNC_DSP2_ID (MTK_PIN_NO(159) | 5) +#define MT6589_PIN_159_GPIO159__FUNC_MD_ABB_AFUNC_D_53 (MTK_PIN_NO(159) | 6) +#define MT6589_PIN_159_GPIO159__FUNC_TESTB_OUT24 (MTK_PIN_NO(159) | 7) + +#define MT6589_PIN_160_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT6589_PIN_160_GPIO160__FUNC_DPI0_G5 (MTK_PIN_NO(160) | 1) +#define MT6589_PIN_160_GPIO160__FUNC_EINT115 (MTK_PIN_NO(160) | 2) +#define MT6589_PIN_160_GPIO160__FUNC_DPI1_D_2X_1 (MTK_PIN_NO(160) | 3) +#define MT6589_PIN_160_GPIO160__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(160) | 4) +#define MT6589_PIN_160_GPIO160__FUNC_DSP2_ICK (MTK_PIN_NO(160) | 5) +#define MT6589_PIN_160_GPIO160__FUNC_MD_ABB_AFUNC_D_54 (MTK_PIN_NO(160) | 6) +#define MT6589_PIN_160_GPIO160__FUNC_TESTB_OUT25 (MTK_PIN_NO(160) | 7) + +#define MT6589_PIN_161_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT6589_PIN_161_GPIO161__FUNC_DPI0_G6 (MTK_PIN_NO(161) | 1) +#define MT6589_PIN_161_GPIO161__FUNC_EINT116 (MTK_PIN_NO(161) | 2) +#define MT6589_PIN_161_GPIO161__FUNC_DPI1_D_2X_2 (MTK_PIN_NO(161) | 3) +#define MT6589_PIN_161_GPIO161__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(161) | 4) +#define MT6589_PIN_161_GPIO161__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(161) | 5) +#define MT6589_PIN_161_GPIO161__FUNC_MD1_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(161) | 6) +#define MT6589_PIN_161_GPIO161__FUNC_TESTB_OUT26 (MTK_PIN_NO(161) | 7) + +#define MT6589_PIN_162_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT6589_PIN_162_GPIO162__FUNC_DPI0_G7 (MTK_PIN_NO(162) | 1) +#define MT6589_PIN_162_GPIO162__FUNC_EINT117 (MTK_PIN_NO(162) | 2) +#define MT6589_PIN_162_GPIO162__FUNC_DPI1_D_2X_3 (MTK_PIN_NO(162) | 3) +#define MT6589_PIN_162_GPIO162__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(162) | 4) +#define MT6589_PIN_162_GPIO162__FUNC_MD2_TCK_PAD (MTK_PIN_NO(162) | 5) +#define MT6589_PIN_162_GPIO162__FUNC_MD1_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(162) | 6) +#define MT6589_PIN_162_GPIO162__FUNC_TESTB_OUT27 (MTK_PIN_NO(162) | 7) + +#define MT6589_PIN_163_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT6589_PIN_163_GPIO163__FUNC_DPI0_R0 (MTK_PIN_NO(163) | 1) +#define MT6589_PIN_163_GPIO163__FUNC_EINT118 (MTK_PIN_NO(163) | 2) +#define MT6589_PIN_163_GPIO163__FUNC_DPI1_D_2X_4 (MTK_PIN_NO(163) | 3) +#define MT6589_PIN_163_GPIO163__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(163) | 4) +#define MT6589_PIN_163_GPIO163__FUNC_MD2_TDI_PAD (MTK_PIN_NO(163) | 5) +#define MT6589_PIN_163_GPIO163__FUNC_MD1_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(163) | 6) +#define MT6589_PIN_163_GPIO163__FUNC_TESTB_OUT28 (MTK_PIN_NO(163) | 7) + +#define MT6589_PIN_164_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT6589_PIN_164_GPIO164__FUNC_DPI0_R1 (MTK_PIN_NO(164) | 1) +#define MT6589_PIN_164_GPIO164__FUNC_EINT119 (MTK_PIN_NO(164) | 2) +#define MT6589_PIN_164_GPIO164__FUNC_DPI1_D_2X_5 (MTK_PIN_NO(164) | 3) +#define MT6589_PIN_164_GPIO164__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(164) | 4) +#define MT6589_PIN_164_GPIO164__FUNC_MD2_TDO_PAD (MTK_PIN_NO(164) | 5) +#define MT6589_PIN_164_GPIO164__FUNC_MD1_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(164) | 6) +#define MT6589_PIN_164_GPIO164__FUNC_TESTB_OUT29 (MTK_PIN_NO(164) | 7) + +#define MT6589_PIN_165_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define MT6589_PIN_165_GPIO165__FUNC_DPI0_R2 (MTK_PIN_NO(165) | 1) +#define MT6589_PIN_165_GPIO165__FUNC_EINT120 (MTK_PIN_NO(165) | 2) +#define MT6589_PIN_165_GPIO165__FUNC_DPI1_D_2X_6 (MTK_PIN_NO(165) | 3) +#define MT6589_PIN_165_GPIO165__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(165) | 4) +#define MT6589_PIN_165_GPIO165__FUNC_MD2_TMS_PAD (MTK_PIN_NO(165) | 5) +#define MT6589_PIN_165_GPIO165__FUNC_TESTB_OUT30 (MTK_PIN_NO(165) | 7) + +#define MT6589_PIN_166_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define MT6589_PIN_166_GPIO166__FUNC_DPI0_R3 (MTK_PIN_NO(166) | 1) +#define MT6589_PIN_166_GPIO166__FUNC_EINT121 (MTK_PIN_NO(166) | 2) +#define MT6589_PIN_166_GPIO166__FUNC_DPI1_D_2X_7 (MTK_PIN_NO(166) | 3) +#define MT6589_PIN_166_GPIO166__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(166) | 4) +#define MT6589_PIN_166_GPIO166__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(166) | 5) +#define MT6589_PIN_166_GPIO166__FUNC_MD_ABB_AFUNC_D_55 (MTK_PIN_NO(166) | 6) +#define MT6589_PIN_166_GPIO166__FUNC_TESTB_OUT31 (MTK_PIN_NO(166) | 7) + +#define MT6589_PIN_167_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define MT6589_PIN_167_GPIO167__FUNC_DPI0_R4 (MTK_PIN_NO(167) | 1) +#define MT6589_PIN_167_GPIO167__FUNC_EINT122 (MTK_PIN_NO(167) | 2) +#define MT6589_PIN_167_GPIO167__FUNC_DPI1_D_2X_8 (MTK_PIN_NO(167) | 3) +#define MT6589_PIN_167_GPIO167__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(167) | 4) +#define MT6589_PIN_167_GPIO167__FUNC_TESTA_OUT0 (MTK_PIN_NO(167) | 7) + +#define MT6589_PIN_168_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define MT6589_PIN_168_GPIO168__FUNC_DPI0_R5 (MTK_PIN_NO(168) | 1) +#define MT6589_PIN_168_GPIO168__FUNC_EINT123 (MTK_PIN_NO(168) | 2) +#define MT6589_PIN_168_GPIO168__FUNC_DPI1_D_2X_9 (MTK_PIN_NO(168) | 3) +#define MT6589_PIN_168_GPIO168__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(168) | 4) +#define MT6589_PIN_168_GPIO168__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(168) | 5) +#define MT6589_PIN_168_GPIO168__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(168) | 6) +#define MT6589_PIN_168_GPIO168__FUNC_TESTA_OUT1 (MTK_PIN_NO(168) | 7) + +#define MT6589_PIN_169_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT6589_PIN_169_GPIO169__FUNC_DPI0_R6 (MTK_PIN_NO(169) | 1) +#define MT6589_PIN_169_GPIO169__FUNC_EINT124 (MTK_PIN_NO(169) | 2) +#define MT6589_PIN_169_GPIO169__FUNC_DPI1_D_2X_10 (MTK_PIN_NO(169) | 3) +#define MT6589_PIN_169_GPIO169__FUNC_CM2VSYNC_2X (MTK_PIN_NO(169) | 4) +#define MT6589_PIN_169_GPIO169__FUNC_TESTA_OUT2 (MTK_PIN_NO(169) | 7) + +#define MT6589_PIN_170_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT6589_PIN_170_GPIO170__FUNC_DPI0_R7 (MTK_PIN_NO(170) | 1) +#define MT6589_PIN_170_GPIO170__FUNC_EINT125 (MTK_PIN_NO(170) | 2) +#define MT6589_PIN_170_GPIO170__FUNC_DPI1_D_2X_11 (MTK_PIN_NO(170) | 3) +#define MT6589_PIN_170_GPIO170__FUNC_CM2HSYNC_2X (MTK_PIN_NO(170) | 4) +#define MT6589_PIN_170_GPIO170__FUNC_TESTA_OUT3 (MTK_PIN_NO(170) | 7) + +#define MT6589_PIN_171_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT6589_PIN_171_GPIO171__FUNC_MSDC1_INSI (MTK_PIN_NO(171) | 1) +#define MT6589_PIN_171_GPIO171__FUNC_EINT57 (MTK_PIN_NO(171) | 2) +#define MT6589_PIN_171_GPIO171__FUNC_SCL5 (MTK_PIN_NO(171) | 3) +#define MT6589_PIN_171_GPIO171__FUNC_PWM6 (MTK_PIN_NO(171) | 4) +#define MT6589_PIN_171_GPIO171__FUNC_CLKM5 (MTK_PIN_NO(171) | 5) +#define MT6589_PIN_171_GPIO171__FUNC_MD2_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(171) | 6) +#define MT6589_PIN_171_GPIO171__FUNC_TESTB_OUT6 (MTK_PIN_NO(171) | 7) + +#define MT6589_PIN_172_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT6589_PIN_172_GPIO172__FUNC_MSDC2_INSI (MTK_PIN_NO(172) | 1) +#define MT6589_PIN_172_GPIO172__FUNC_EINT65 (MTK_PIN_NO(172) | 2) +#define MT6589_PIN_172_GPIO172__FUNC_BPI2_BUS6 (MTK_PIN_NO(172) | 3) +#define MT6589_PIN_172_GPIO172__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(172) | 7) + +#define MT6589_PIN_173_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT6589_PIN_173_GPIO173__FUNC_MSDC2_SDWPI (MTK_PIN_NO(173) | 1) +#define MT6589_PIN_173_GPIO173__FUNC_EINT66 (MTK_PIN_NO(173) | 2) +#define MT6589_PIN_173_GPIO173__FUNC_BPI2_BUS17 (MTK_PIN_NO(173) | 3) +#define MT6589_PIN_173_GPIO173__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(173) | 4) +#define MT6589_PIN_173_GPIO173__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(173) | 5) +#define MT6589_PIN_173_GPIO173__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(173) | 7) + +#define MT6589_PIN_174_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT6589_PIN_174_GPIO174__FUNC_MSDC2_DAT2 (MTK_PIN_NO(174) | 1) +#define MT6589_PIN_174_GPIO174__FUNC_EINT63 (MTK_PIN_NO(174) | 2) +#define MT6589_PIN_174_GPIO174__FUNC_BPI2_BUS4 (MTK_PIN_NO(174) | 3) +#define MT6589_PIN_174_GPIO174__FUNC_DSP2_IMS (MTK_PIN_NO(174) | 4) +#define MT6589_PIN_174_GPIO174__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(174) | 7) + +#define MT6589_PIN_175_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT6589_PIN_175_GPIO175__FUNC_MSDC2_DAT3 (MTK_PIN_NO(175) | 1) +#define MT6589_PIN_175_GPIO175__FUNC_EINT64 (MTK_PIN_NO(175) | 2) +#define MT6589_PIN_175_GPIO175__FUNC_BPI2_BUS5 (MTK_PIN_NO(175) | 3) +#define MT6589_PIN_175_GPIO175__FUNC_DSP2_ID (MTK_PIN_NO(175) | 4) +#define MT6589_PIN_175_GPIO175__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(175) | 7) + +#define MT6589_PIN_176_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT6589_PIN_176_GPIO176__FUNC_MSDC2_CMD (MTK_PIN_NO(176) | 1) +#define MT6589_PIN_176_GPIO176__FUNC_EINT60 (MTK_PIN_NO(176) | 2) +#define MT6589_PIN_176_GPIO176__FUNC_BPI2_BUS1 (MTK_PIN_NO(176) | 3) +#define MT6589_PIN_176_GPIO176__FUNC_DSP1_IMS (MTK_PIN_NO(176) | 4) +#define MT6589_PIN_176_GPIO176__FUNC_PCM1_WS (MTK_PIN_NO(176) | 5) +#define MT6589_PIN_176_GPIO176__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(176) | 7) + +#define MT6589_PIN_177_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT6589_PIN_177_GPIO177__FUNC_MSDC2_CLK (MTK_PIN_NO(177) | 1) +#define MT6589_PIN_177_GPIO177__FUNC_EINT59 (MTK_PIN_NO(177) | 2) +#define MT6589_PIN_177_GPIO177__FUNC_BPI2_BUS0 (MTK_PIN_NO(177) | 3) +#define MT6589_PIN_177_GPIO177__FUNC_DSP1_ICK (MTK_PIN_NO(177) | 4) +#define MT6589_PIN_177_GPIO177__FUNC_PCM1_CK (MTK_PIN_NO(177) | 5) +#define MT6589_PIN_177_GPIO177__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(177) | 7) + +#define MT6589_PIN_178_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT6589_PIN_178_GPIO178__FUNC_MSDC2_DAT1 (MTK_PIN_NO(178) | 1) +#define MT6589_PIN_178_GPIO178__FUNC_EINT62 (MTK_PIN_NO(178) | 2) +#define MT6589_PIN_178_GPIO178__FUNC_BPI2_BUS3 (MTK_PIN_NO(178) | 3) +#define MT6589_PIN_178_GPIO178__FUNC_DSP2_ICK (MTK_PIN_NO(178) | 4) +#define MT6589_PIN_178_GPIO178__FUNC_PCM1_DO (MTK_PIN_NO(178) | 5) +#define MT6589_PIN_178_GPIO178__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(178) | 7) + +#define MT6589_PIN_179_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT6589_PIN_179_GPIO179__FUNC_MSDC2_DAT0 (MTK_PIN_NO(179) | 1) +#define MT6589_PIN_179_GPIO179__FUNC_EINT61 (MTK_PIN_NO(179) | 2) +#define MT6589_PIN_179_GPIO179__FUNC_BPI2_BUS2 (MTK_PIN_NO(179) | 3) +#define MT6589_PIN_179_GPIO179__FUNC_DSP1_ID (MTK_PIN_NO(179) | 4) +#define MT6589_PIN_179_GPIO179__FUNC_PCM1_DI (MTK_PIN_NO(179) | 5) +#define MT6589_PIN_179_GPIO179__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(179) | 7) + +#define MT6589_PIN_180_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT6589_PIN_180_GPIO180__FUNC_MSDC1_DAT0 (MTK_PIN_NO(180) | 1) +#define MT6589_PIN_180_GPIO180__FUNC_EINT53 (MTK_PIN_NO(180) | 2) +#define MT6589_PIN_180_GPIO180__FUNC_SCL1 (MTK_PIN_NO(180) | 3) +#define MT6589_PIN_180_GPIO180__FUNC_PWM2 (MTK_PIN_NO(180) | 4) +#define MT6589_PIN_180_GPIO180__FUNC_CLKM1 (MTK_PIN_NO(180) | 5) +#define MT6589_PIN_180_GPIO180__FUNC_MD2_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(180) | 6) +#define MT6589_PIN_180_GPIO180__FUNC_TESTB_OUT2 (MTK_PIN_NO(180) | 7) + +#define MT6589_PIN_181_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT6589_PIN_181_GPIO181__FUNC_MSDC1_DAT1 (MTK_PIN_NO(181) | 1) +#define MT6589_PIN_181_GPIO181__FUNC_EINT54 (MTK_PIN_NO(181) | 2) +#define MT6589_PIN_181_GPIO181__FUNC_SDA1 (MTK_PIN_NO(181) | 3) +#define MT6589_PIN_181_GPIO181__FUNC_PWM3 (MTK_PIN_NO(181) | 4) +#define MT6589_PIN_181_GPIO181__FUNC_CLKM2 (MTK_PIN_NO(181) | 5) +#define MT6589_PIN_181_GPIO181__FUNC_MD2_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(181) | 6) +#define MT6589_PIN_181_GPIO181__FUNC_TESTB_OUT3 (MTK_PIN_NO(181) | 7) + +#define MT6589_PIN_182_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT6589_PIN_182_GPIO182__FUNC_MSDC1_SDWPI (MTK_PIN_NO(182) | 1) +#define MT6589_PIN_182_GPIO182__FUNC_EINT58 (MTK_PIN_NO(182) | 2) +#define MT6589_PIN_182_GPIO182__FUNC_SDA5 (MTK_PIN_NO(182) | 3) +#define MT6589_PIN_182_GPIO182__FUNC_PWM7 (MTK_PIN_NO(182) | 4) +#define MT6589_PIN_182_GPIO182__FUNC_CLKM6 (MTK_PIN_NO(182) | 5) +#define MT6589_PIN_182_GPIO182__FUNC_MD2_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(182) | 6) +#define MT6589_PIN_182_GPIO182__FUNC_TESTB_OUT7 (MTK_PIN_NO(182) | 7) + +#define MT6589_PIN_183_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT6589_PIN_183_GPIO183__FUNC_MSDC1_CMD (MTK_PIN_NO(183) | 1) +#define MT6589_PIN_183_GPIO183__FUNC_EINT52 (MTK_PIN_NO(183) | 2) +#define MT6589_PIN_183_GPIO183__FUNC_SDA0 (MTK_PIN_NO(183) | 3) +#define MT6589_PIN_183_GPIO183__FUNC_PWM1 (MTK_PIN_NO(183) | 4) +#define MT6589_PIN_183_GPIO183__FUNC_CLKM0 (MTK_PIN_NO(183) | 5) +#define MT6589_PIN_183_GPIO183__FUNC_MD2_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(183) | 6) +#define MT6589_PIN_183_GPIO183__FUNC_TESTB_OUT1 (MTK_PIN_NO(183) | 7) + +#define MT6589_PIN_184_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT6589_PIN_184_GPIO184__FUNC_MSDC1_CLK (MTK_PIN_NO(184) | 1) +#define MT6589_PIN_184_GPIO184__FUNC_EINT51 (MTK_PIN_NO(184) | 2) +#define MT6589_PIN_184_GPIO184__FUNC_SCL0 (MTK_PIN_NO(184) | 3) +#define MT6589_PIN_184_GPIO184__FUNC_DISP_PWM (MTK_PIN_NO(184) | 4) +#define MT6589_PIN_184_GPIO184__FUNC_MD2_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(184) | 6) +#define MT6589_PIN_184_GPIO184__FUNC_TESTB_OUT0 (MTK_PIN_NO(184) | 7) + +#define MT6589_PIN_185_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT6589_PIN_185_GPIO185__FUNC_MSDC1_DAT2 (MTK_PIN_NO(185) | 1) +#define MT6589_PIN_185_GPIO185__FUNC_EINT55 (MTK_PIN_NO(185) | 2) +#define MT6589_PIN_185_GPIO185__FUNC_SCL4 (MTK_PIN_NO(185) | 3) +#define MT6589_PIN_185_GPIO185__FUNC_PWM4 (MTK_PIN_NO(185) | 4) +#define MT6589_PIN_185_GPIO185__FUNC_CLKM3 (MTK_PIN_NO(185) | 5) +#define MT6589_PIN_185_GPIO185__FUNC_MD2_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(185) | 6) +#define MT6589_PIN_185_GPIO185__FUNC_TESTB_OUT4 (MTK_PIN_NO(185) | 7) + +#define MT6589_PIN_186_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT6589_PIN_186_GPIO186__FUNC_MSDC1_DAT3 (MTK_PIN_NO(186) | 1) +#define MT6589_PIN_186_GPIO186__FUNC_EINT56 (MTK_PIN_NO(186) | 2) +#define MT6589_PIN_186_GPIO186__FUNC_SDA4 (MTK_PIN_NO(186) | 3) +#define MT6589_PIN_186_GPIO186__FUNC_PWM5 (MTK_PIN_NO(186) | 4) +#define MT6589_PIN_186_GPIO186__FUNC_CLKM4 (MTK_PIN_NO(186) | 5) +#define MT6589_PIN_186_GPIO186__FUNC_MD2_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(186) | 6) +#define MT6589_PIN_186_GPIO186__FUNC_TESTB_OUT5 (MTK_PIN_NO(186) | 7) + +#define MT6589_PIN_187_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT6589_PIN_187_GPIO187__FUNC_EINT36 (MTK_PIN_NO(187) | 2) + +#define MT6589_PIN_188_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT6589_PIN_188_GPIO188__FUNC_EINT35 (MTK_PIN_NO(188) | 2) + +#define MT6589_PIN_189_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT6589_PIN_189_GPIO189__FUNC_EINT169 (MTK_PIN_NO(189) | 2) + +#define MT6589_PIN_190_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT6589_PIN_190_GPIO190__FUNC_EINT168 (MTK_PIN_NO(190) | 2) + +#define MT6589_PIN_191_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT6589_PIN_191_GPIO191__FUNC_EINT163 (MTK_PIN_NO(191) | 2) + +#define MT6589_PIN_192_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT6589_PIN_192_GPIO192__FUNC_EINT162 (MTK_PIN_NO(192) | 2) + +#define MT6589_PIN_193_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT6589_PIN_193_GPIO193__FUNC_EINT167 (MTK_PIN_NO(193) | 2) + +#define MT6589_PIN_194_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT6589_PIN_194_GPIO194__FUNC_EINT166 (MTK_PIN_NO(194) | 2) + +#define MT6589_PIN_195_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT6589_PIN_195_GPIO195__FUNC_EINT165 (MTK_PIN_NO(195) | 2) + +#define MT6589_PIN_196_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT6589_PIN_196_GPIO196__FUNC_EINT164 (MTK_PIN_NO(196) | 2) + +#define MT6589_PIN_197_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT6589_PIN_197_GPIO197__FUNC_CMDAT6 (MTK_PIN_NO(197) | 1) +#define MT6589_PIN_197_GPIO197__FUNC_EINT175 (MTK_PIN_NO(197) | 2) + +#define MT6589_PIN_198_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT6589_PIN_198_GPIO198__FUNC_CMDAT7 (MTK_PIN_NO(198) | 1) +#define MT6589_PIN_198_GPIO198__FUNC_EINT174 (MTK_PIN_NO(198) | 2) + +#define MT6589_PIN_199_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT6589_PIN_199_GPIO199__FUNC_CMDAT8 (MTK_PIN_NO(199) | 1) +#define MT6589_PIN_199_GPIO199__FUNC_EINT171 (MTK_PIN_NO(199) | 2) + +#define MT6589_PIN_200_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT6589_PIN_200_GPIO200__FUNC_CMDAT9 (MTK_PIN_NO(200) | 1) +#define MT6589_PIN_200_GPIO200__FUNC_EINT170 (MTK_PIN_NO(200) | 2) + +#define MT6589_PIN_201_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT6589_PIN_201_GPIO201__FUNC_CMHSYNC (MTK_PIN_NO(201) | 1) +#define MT6589_PIN_201_GPIO201__FUNC_EINT173 (MTK_PIN_NO(201) | 2) + +#define MT6589_PIN_202_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT6589_PIN_202_GPIO202__FUNC_CMVSYNC (MTK_PIN_NO(202) | 1) +#define MT6589_PIN_202_GPIO202__FUNC_EINT172 (MTK_PIN_NO(202) | 2) + +#define MT6589_PIN_203_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT6589_PIN_203_GPIO203__FUNC_CMDAT2 (MTK_PIN_NO(203) | 1) +#define MT6589_PIN_203_GPIO203__FUNC_EINT181 (MTK_PIN_NO(203) | 2) +#define MT6589_PIN_203_GPIO203__FUNC_CMCSD2 (MTK_PIN_NO(203) | 3) + +#define MT6589_PIN_204_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT6589_PIN_204_GPIO204__FUNC_CMDAT3 (MTK_PIN_NO(204) | 1) +#define MT6589_PIN_204_GPIO204__FUNC_EINT180 (MTK_PIN_NO(204) | 2) +#define MT6589_PIN_204_GPIO204__FUNC_CMCSD3 (MTK_PIN_NO(204) | 3) + +#define MT6589_PIN_205_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT6589_PIN_205_GPIO205__FUNC_CMDAT4 (MTK_PIN_NO(205) | 1) +#define MT6589_PIN_205_GPIO205__FUNC_EINT177 (MTK_PIN_NO(205) | 2) + +#define MT6589_PIN_206_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT6589_PIN_206_GPIO206__FUNC_CMDAT5 (MTK_PIN_NO(206) | 1) +#define MT6589_PIN_206_GPIO206__FUNC_EINT176 (MTK_PIN_NO(206) | 2) + +#define MT6589_PIN_207_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT6589_PIN_207_GPIO207__FUNC_CMDAT0 (MTK_PIN_NO(207) | 1) +#define MT6589_PIN_207_GPIO207__FUNC_EINT179 (MTK_PIN_NO(207) | 2) +#define MT6589_PIN_207_GPIO207__FUNC_CMCSD0 (MTK_PIN_NO(207) | 3) + +#define MT6589_PIN_208_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT6589_PIN_208_GPIO208__FUNC_CMDAT1 (MTK_PIN_NO(208) | 1) +#define MT6589_PIN_208_GPIO208__FUNC_EINT178 (MTK_PIN_NO(208) | 2) +#define MT6589_PIN_208_GPIO208__FUNC_CMCSD1 (MTK_PIN_NO(208) | 3) + +#define MT6589_PIN_209_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT6589_PIN_209_GPIO209__FUNC_CMPCLK (MTK_PIN_NO(209) | 1) +#define MT6589_PIN_209_GPIO209__FUNC_EINT182 (MTK_PIN_NO(209) | 2) +#define MT6589_PIN_209_GPIO209__FUNC_CMCSK (MTK_PIN_NO(209) | 3) +#define MT6589_PIN_209_GPIO209__FUNC_CM2MCLK_4X (MTK_PIN_NO(209) | 4) +#define MT6589_PIN_209_GPIO209__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(209) | 5) +#define MT6589_PIN_209_GPIO209__FUNC_TESTA_OUT27 (MTK_PIN_NO(209) | 7) + +#define MT6589_PIN_210_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define MT6589_PIN_210_GPIO210__FUNC_CMMCLK (MTK_PIN_NO(210) | 1) +#define MT6589_PIN_210_GPIO210__FUNC_EINT183 (MTK_PIN_NO(210) | 2) +#define MT6589_PIN_210_GPIO210__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(210) | 5) +#define MT6589_PIN_210_GPIO210__FUNC_TESTA_OUT28 (MTK_PIN_NO(210) | 7) + +#define MT6589_PIN_211_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define MT6589_PIN_211_GPIO211__FUNC_CMRST (MTK_PIN_NO(211) | 1) +#define MT6589_PIN_211_GPIO211__FUNC_EINT185 (MTK_PIN_NO(211) | 2) +#define MT6589_PIN_211_GPIO211__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(211) | 5) +#define MT6589_PIN_211_GPIO211__FUNC_TESTA_OUT30 (MTK_PIN_NO(211) | 7) + +#define MT6589_PIN_212_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define MT6589_PIN_212_GPIO212__FUNC_CMPDN (MTK_PIN_NO(212) | 1) +#define MT6589_PIN_212_GPIO212__FUNC_EINT184 (MTK_PIN_NO(212) | 2) +#define MT6589_PIN_212_GPIO212__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(212) | 5) +#define MT6589_PIN_212_GPIO212__FUNC_TESTA_OUT29 (MTK_PIN_NO(212) | 7) + +#define MT6589_PIN_213_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define MT6589_PIN_213_GPIO213__FUNC_CMFLASH (MTK_PIN_NO(213) | 1) +#define MT6589_PIN_213_GPIO213__FUNC_EINT186 (MTK_PIN_NO(213) | 2) +#define MT6589_PIN_213_GPIO213__FUNC_CM2MCLK_3X (MTK_PIN_NO(213) | 3) +#define MT6589_PIN_213_GPIO213__FUNC_TESTA_OUT31 (MTK_PIN_NO(213) | 7) + +#define MT6589_PIN_214_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define MT6589_PIN_214_GPIO214__FUNC_SDA1 (MTK_PIN_NO(214) | 1) +#define MT6589_PIN_214_GPIO214__FUNC_EINT93 (MTK_PIN_NO(214) | 2) +#define MT6589_PIN_214_GPIO214__FUNC_CLKM3 (MTK_PIN_NO(214) | 3) +#define MT6589_PIN_214_GPIO214__FUNC_PWM3 (MTK_PIN_NO(214) | 4) +#define MT6589_PIN_214_GPIO214__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(214) | 5) +#define MT6589_PIN_214_GPIO214__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(214) | 7) + +#define MT6589_PIN_215_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define MT6589_PIN_215_GPIO215__FUNC_SCL1 (MTK_PIN_NO(215) | 1) +#define MT6589_PIN_215_GPIO215__FUNC_EINT92 (MTK_PIN_NO(215) | 2) +#define MT6589_PIN_215_GPIO215__FUNC_CLKM2 (MTK_PIN_NO(215) | 3) +#define MT6589_PIN_215_GPIO215__FUNC_PWM2 (MTK_PIN_NO(215) | 4) +#define MT6589_PIN_215_GPIO215__FUNC_TS_AUX_DIN (MTK_PIN_NO(215) | 5) +#define MT6589_PIN_215_GPIO215__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(215) | 7) + +#define MT6589_PIN_216_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define MT6589_PIN_216_GPIO216__FUNC_SDA2 (MTK_PIN_NO(216) | 1) +#define MT6589_PIN_216_GPIO216__FUNC_EINT95 (MTK_PIN_NO(216) | 2) +#define MT6589_PIN_216_GPIO216__FUNC_CLKM5 (MTK_PIN_NO(216) | 3) +#define MT6589_PIN_216_GPIO216__FUNC_PWM5 (MTK_PIN_NO(216) | 4) +#define MT6589_PIN_216_GPIO216__FUNC_TS_AUX_PWDB (MTK_PIN_NO(216) | 5) +#define MT6589_PIN_216_GPIO216__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(216) | 7) + +#define MT6589_PIN_217_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define MT6589_PIN_217_GPIO217__FUNC_SCL2 (MTK_PIN_NO(217) | 1) +#define MT6589_PIN_217_GPIO217__FUNC_EINT94 (MTK_PIN_NO(217) | 2) +#define MT6589_PIN_217_GPIO217__FUNC_CLKM4 (MTK_PIN_NO(217) | 3) +#define MT6589_PIN_217_GPIO217__FUNC_PWM4 (MTK_PIN_NO(217) | 4) +#define MT6589_PIN_217_GPIO217__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(217) | 5) +#define MT6589_PIN_217_GPIO217__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(217) | 7) + +#define MT6589_PIN_218_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define MT6589_PIN_218_GPIO218__FUNC_SRCLKENAI (MTK_PIN_NO(218) | 1) + +#define MT6589_PIN_219_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define MT6589_PIN_219_GPIO219__FUNC_URXD3 (MTK_PIN_NO(219) | 1) +#define MT6589_PIN_219_GPIO219__FUNC_EINT87 (MTK_PIN_NO(219) | 2) +#define MT6589_PIN_219_GPIO219__FUNC_UTXD3 (MTK_PIN_NO(219) | 3) +#define MT6589_PIN_219_GPIO219__FUNC_MD2_URXD (MTK_PIN_NO(219) | 4) +#define MT6589_PIN_219_GPIO219__FUNC_TS_AUX_ST (MTK_PIN_NO(219) | 5) +#define MT6589_PIN_219_GPIO219__FUNC_PWM4 (MTK_PIN_NO(219) | 6) +#define MT6589_PIN_219_GPIO219__FUNC_MD2_EINT4 (MTK_PIN_NO(219) | 7) + +#define MT6589_PIN_220_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +#define MT6589_PIN_220_GPIO220__FUNC_UTXD3 (MTK_PIN_NO(220) | 1) +#define MT6589_PIN_220_GPIO220__FUNC_EINT86 (MTK_PIN_NO(220) | 2) +#define MT6589_PIN_220_GPIO220__FUNC_URXD3 (MTK_PIN_NO(220) | 3) +#define MT6589_PIN_220_GPIO220__FUNC_MD2_UTXD (MTK_PIN_NO(220) | 4) +#define MT6589_PIN_220_GPIO220__FUNC_TS_AUX_CS_B (MTK_PIN_NO(220) | 5) +#define MT6589_PIN_220_GPIO220__FUNC_PWM3 (MTK_PIN_NO(220) | 6) +#define MT6589_PIN_220_GPIO220__FUNC_MD2_EINT3 (MTK_PIN_NO(220) | 7) + +#define MT6589_PIN_221_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +#define MT6589_PIN_221_GPIO221__FUNC_MRG_I2S_PCM_CLK (MTK_PIN_NO(221) | 1) +#define MT6589_PIN_221_GPIO221__FUNC_I2SIN_CK (MTK_PIN_NO(221) | 3) +#define MT6589_PIN_221_GPIO221__FUNC_PCM0_CK (MTK_PIN_NO(221) | 4) +#define MT6589_PIN_221_GPIO221__FUNC_DSP2_ICK (MTK_PIN_NO(221) | 5) +#define MT6589_PIN_221_GPIO221__FUNC_IMG_TEST_CK (MTK_PIN_NO(221) | 6) +#define MT6589_PIN_221_GPIO221__FUNC_USB_SCL (MTK_PIN_NO(221) | 7) + +#define MT6589_PIN_222_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +#define MT6589_PIN_222_GPIO222__FUNC_MRG_I2S_PCM_SYNC (MTK_PIN_NO(222) | 1) +#define MT6589_PIN_222_GPIO222__FUNC_EINT16 (MTK_PIN_NO(222) | 2) +#define MT6589_PIN_222_GPIO222__FUNC_I2SIN_WS (MTK_PIN_NO(222) | 3) +#define MT6589_PIN_222_GPIO222__FUNC_PCM0_WS (MTK_PIN_NO(222) | 4) +#define MT6589_PIN_222_GPIO222__FUNC_DISP_TEST_CK (MTK_PIN_NO(222) | 6) + +#define MT6589_PIN_223_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +#define MT6589_PIN_223_GPIO223__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(223) | 1) +#define MT6589_PIN_223_GPIO223__FUNC_I2SIN_DAT (MTK_PIN_NO(223) | 3) +#define MT6589_PIN_223_GPIO223__FUNC_PCM0_DI (MTK_PIN_NO(223) | 4) +#define MT6589_PIN_223_GPIO223__FUNC_DSP2_ID (MTK_PIN_NO(223) | 5) +#define MT6589_PIN_223_GPIO223__FUNC_MFG_TEST_CK (MTK_PIN_NO(223) | 6) +#define MT6589_PIN_223_GPIO223__FUNC_USB_SDA (MTK_PIN_NO(223) | 7) + +#define MT6589_PIN_224_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +#define MT6589_PIN_224_GPIO224__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(224) | 1) +#define MT6589_PIN_224_GPIO224__FUNC_EINT17 (MTK_PIN_NO(224) | 2) +#define MT6589_PIN_224_GPIO224__FUNC_I2SOUT_DAT (MTK_PIN_NO(224) | 3) +#define MT6589_PIN_224_GPIO224__FUNC_PCM0_DO (MTK_PIN_NO(224) | 4) +#define MT6589_PIN_224_GPIO224__FUNC_VDEC_TEST_CK (MTK_PIN_NO(224) | 6) + +#define MT6589_PIN_225_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +#define MT6589_PIN_225_GPIO225__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(225) | 1) +#define MT6589_PIN_225_GPIO225__FUNC_EINT18 (MTK_PIN_NO(225) | 2) +#define MT6589_PIN_225_GPIO225__FUNC_BT_SYNC (MTK_PIN_NO(225) | 3) +#define MT6589_PIN_225_GPIO225__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(225) | 4) +#define MT6589_PIN_225_GPIO225__FUNC_DSP2_IMS (MTK_PIN_NO(225) | 5) +#define MT6589_PIN_225_GPIO225__FUNC_VENC_TEST_CK (MTK_PIN_NO(225) | 6) + +#define MT6589_PIN_226_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +#define MT6589_PIN_226_GPIO226__FUNC_MSDC3_DAT2 (MTK_PIN_NO(226) | 1) +#define MT6589_PIN_226_GPIO226__FUNC_EINT71 (MTK_PIN_NO(226) | 2) +#define MT6589_PIN_226_GPIO226__FUNC_SCL6 (MTK_PIN_NO(226) | 3) +#define MT6589_PIN_226_GPIO226__FUNC_PWM5 (MTK_PIN_NO(226) | 4) +#define MT6589_PIN_226_GPIO226__FUNC_CLKM4 (MTK_PIN_NO(226) | 5) +#define MT6589_PIN_226_GPIO226__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(226) | 7) + +#define MT6589_PIN_227_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +#define MT6589_PIN_227_GPIO227__FUNC_MSDC3_DAT3 (MTK_PIN_NO(227) | 1) +#define MT6589_PIN_227_GPIO227__FUNC_EINT72 (MTK_PIN_NO(227) | 2) +#define MT6589_PIN_227_GPIO227__FUNC_SDA6 (MTK_PIN_NO(227) | 3) +#define MT6589_PIN_227_GPIO227__FUNC_PWM6 (MTK_PIN_NO(227) | 4) +#define MT6589_PIN_227_GPIO227__FUNC_CLKM5 (MTK_PIN_NO(227) | 5) +#define MT6589_PIN_227_GPIO227__FUNC_A_FUNC_CK (MTK_PIN_NO(227) | 7) + +#define MT6589_PIN_228_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +#define MT6589_PIN_228_GPIO228__FUNC_MSDC3_CMD (MTK_PIN_NO(228) | 1) +#define MT6589_PIN_228_GPIO228__FUNC_EINT68 (MTK_PIN_NO(228) | 2) +#define MT6589_PIN_228_GPIO228__FUNC_SDA2 (MTK_PIN_NO(228) | 3) +#define MT6589_PIN_228_GPIO228__FUNC_PWM2 (MTK_PIN_NO(228) | 4) +#define MT6589_PIN_228_GPIO228__FUNC_CLKM1 (MTK_PIN_NO(228) | 5) +#define MT6589_PIN_228_GPIO228__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(228) | 7) + +#define MT6589_PIN_229_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +#define MT6589_PIN_229_GPIO229__FUNC_MSDC3_CLK (MTK_PIN_NO(229) | 1) +#define MT6589_PIN_229_GPIO229__FUNC_EINT67 (MTK_PIN_NO(229) | 2) +#define MT6589_PIN_229_GPIO229__FUNC_SCL2 (MTK_PIN_NO(229) | 3) +#define MT6589_PIN_229_GPIO229__FUNC_PWM1 (MTK_PIN_NO(229) | 4) +#define MT6589_PIN_229_GPIO229__FUNC_CLKM0 (MTK_PIN_NO(229) | 5) +#define MT6589_PIN_229_GPIO229__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(229) | 7) + +#define MT6589_PIN_230_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +#define MT6589_PIN_230_GPIO230__FUNC_MSDC3_DAT1 (MTK_PIN_NO(230) | 1) +#define MT6589_PIN_230_GPIO230__FUNC_EINT70 (MTK_PIN_NO(230) | 2) +#define MT6589_PIN_230_GPIO230__FUNC_SDA3 (MTK_PIN_NO(230) | 3) +#define MT6589_PIN_230_GPIO230__FUNC_PWM4 (MTK_PIN_NO(230) | 4) +#define MT6589_PIN_230_GPIO230__FUNC_CLKM3 (MTK_PIN_NO(230) | 5) +#define MT6589_PIN_230_GPIO230__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(230) | 7) + +#define MT6589_PIN_231_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +#define MT6589_PIN_231_GPIO231__FUNC_MSDC3_DAT0 (MTK_PIN_NO(231) | 1) +#define MT6589_PIN_231_GPIO231__FUNC_EINT69 (MTK_PIN_NO(231) | 2) +#define MT6589_PIN_231_GPIO231__FUNC_SCL3 (MTK_PIN_NO(231) | 3) +#define MT6589_PIN_231_GPIO231__FUNC_PWM3 (MTK_PIN_NO(231) | 4) +#define MT6589_PIN_231_GPIO231__FUNC_CLKM2 (MTK_PIN_NO(231) | 5) +#define MT6589_PIN_231_GPIO231__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(231) | 7) + +#endif /* __MT6589_PINFUNC_H */ From aea15fa3ea8b103357fb5aa72fa1b9cdb408aca9 Mon Sep 17 00:00:00 2001 From: Tsuyukusa Akari Date: Sun, 18 Jan 2026 21:19:11 +0900 Subject: [PATCH 29/98] clk: mediatek: mt6589-infracfg: fix TOP_CKMUXSEL offset --- drivers/clk/mediatek/clk-mt6589-infracfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt6589-infracfg.c b/drivers/clk/mediatek/clk-mt6589-infracfg.c index dea3488a4116ac..f16bd9167bb241 100644 --- a/drivers/clk/mediatek/clk-mt6589-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6589-infracfg.c @@ -10,7 +10,7 @@ #include -#define TOP_CKMUXSEL 0x10001000 +#define TOP_CKMUXSEL 0x0 static const char * const infra_mux1_parents[] = { "clk26m", From b0b2196659a7e81b1bfbc34705328ecf6bd3ccf5 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Thu, 26 Feb 2026 01:59:16 +0900 Subject: [PATCH 30/98] dt-bindings: reset: mt6589: format --- include/dt-bindings/reset/mt6589-resets.h | 64 +++++++++++------------ 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/include/dt-bindings/reset/mt6589-resets.h b/include/dt-bindings/reset/mt6589-resets.h index 12f2c784aecd4f..54570146ba8bfd 100644 --- a/include/dt-bindings/reset/mt6589-resets.h +++ b/include/dt-bindings/reset/mt6589-resets.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2026 akku + * Copyright (c) 2026 Akari Tsuyukusa */ #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT6589 @@ -11,61 +11,61 @@ #define MT6589_PERI_UART1_SW_RST 1 #define MT6589_PERI_UART2_SW_RST 2 #define MT6589_PERI_UART3_SW_RST 3 -#define MT6589_PERI_IRDA_SW_RST 4 -#define MT6589_PERI_PTP_RST 5 +#define MT6589_PERI_IRDA_SW_RST 4 +#define MT6589_PERI_PTP_RST 5 #define MT6589_PERI_AP_HIF_SW_RST 6 #define MT6589_PERI_MD_HIF_SW_RST 8 -#define MT6589_PERI_NLI_SW_RST 9 +#define MT6589_PERI_NLI_SW_RST 9 #define MT6589_PERI_AUXADC_SW_RST 10 #define MT6589_PERI_DMA_SW_RS_RST 11 #define MT6589_PERI_NFI_SW_RST_RST 14 -#define MT6589_PERI_PWM_SW_RST 15 +#define MT6589_PERI_PWM_SW_RST 15 #define MT6589_PERI_THERM_SW_RST 16 #define MT6589_PERI_MSDC0_SW_RST 17 #define MT6589_PERI_MSDC1_SW_RST 18 #define MT6589_PERI_MSDC2_SW_RST 19 #define MT6589_PERI_MSDC3_SW_RST 20 -#define MT6589_PERI_I2C0_SW_RST 22 -#define MT6589_PERI_I2C1_SW_RST 23 -#define MT6589_PERI_I2C2_SW_RST 24 -#define MT6589_PERI_I2C3_SW_RST 25 -#define MT6589_PERI_I2C4_SW_RST 26 -#define MT6589_PERI_I2C5_SW_RST 27 -#define MT6589_PERI_I2C6_SW_RST 28 -#define MT6589_PERI_USB_SW_RST 29 -#define MT6589_PERI_SPI0_SW_RST 33 +#define MT6589_PERI_I2C0_SW_RST 22 +#define MT6589_PERI_I2C1_SW_RST 23 +#define MT6589_PERI_I2C2_SW_RST 24 +#define MT6589_PERI_I2C3_SW_RST 25 +#define MT6589_PERI_I2C4_SW_RST 26 +#define MT6589_PERI_I2C5_SW_RST 27 +#define MT6589_PERI_I2C6_SW_RST 28 +#define MT6589_PERI_USB_SW_RST 29 +#define MT6589_PERI_SPI0_SW_RST 33 /* INFRA */ #define MT6589_INFRA_EMI_REG_RST 0 #define MT6589_INFRA_DRAMC0_AO_RST 1 -#define MT6589_INFRA_CCIF0_RST 2 +#define MT6589_INFRA_CCIF0_RST 2 #define MT6589_INFRA_AP_CIRP_EINT_RST 3 -#define MT6589_INFRA_APXGPT_RST 4 -#define MT6589_INFRA_SCPSYS_RST 5 -#define MT6589_INFRA_CCIF1_RST 6 +#define MT6589_INFRA_APXGPT_RST 4 +#define MT6589_INFRA_SCPSYS_RST 5 +#define MT6589_INFRA_CCIF1_RST 6 #define MT6589_INFRA_PMIC_WRAP_RST 7 -#define MT6589_INFRA_KP_RST 8 -#define MT6589_INFRA_EMI_RST 32 -#define MT6589_INFRA_DRAMC0_RST 34 -#define MT6589_INFRA_SMI_RST 35 -#define MT6589_INFRA_M4U_RST 36 +#define MT6589_INFRA_KP_RST 8 +#define MT6589_INFRA_EMI_RST 32 +#define MT6589_INFRA_DRAMC0_RST 34 +#define MT6589_INFRA_SMI_RST 35 +#define MT6589_INFRA_M4U_RST 36 /* TOPRGU */ -#define MT6589_TOPRGU_INFRA_RST 0 -#define MT6589_TOPRGU_DISP_RST 1 -#define MT6589_TOPRGU_MFG_RST 2 -#define MT6589_TOPRGU_VENC_RST 3 -#define MT6589_TOPRGU_VDEC_RST 4 -#define MT6589_TOPRGU_IMG_RST 5 +#define MT6589_TOPRGU_INFRA_RST 0 +#define MT6589_TOPRGU_DISP_RST 1 +#define MT6589_TOPRGU_MFG_RST 2 +#define MT6589_TOPRGU_VENC_RST 3 +#define MT6589_TOPRGU_VDEC_RST 4 +#define MT6589_TOPRGU_IMG_RST 5 #define MT6589_TOPRGU_DDRPHY_RST 6 -#define MT6589_TOPRGU_MD_RST 7 +#define MT6589_TOPRGU_MD_RST 7 #define MT6589_TOPRGU_INFRA_AO_RST 8 #define MT6589_TOPRGU_MD_LITE_RST 9 #define MT6589_TOPRGU_APMIXED_RST 10 #define MT6589_TOPRGU_PWRAP_SPICTL_RST 11 /* MFG */ -#define MT6589_MFG_AXI_RESET 0 -#define MT6589_MFG_G3D_RESET 1 +#define MT6589_MFG_AXI_RESET 0 +#define MT6589_MFG_G3D_RESET 1 #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT6589 */ From dbdb7fe426316c18b172530b4f69336d1faf3b86 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:15:47 +0900 Subject: [PATCH 31/98] dt-bindings: mmc: mtk-sd: add mediatek,mt6589-mmc Signed-off-by: Akari Tsuyukusa --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 6dd26ad314916a..12e32abd21457d 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -28,7 +28,9 @@ properties: - mediatek,mt8196-mmc - mediatek,mt8516-mmc - items: - - const: mediatek,mt7623-mmc + - enum: + - mediatek,mt6589-mmc + - mediatek,mt7623-mmc - const: mediatek,mt2701-mmc - items: - enum: @@ -182,6 +184,7 @@ allOf: compatible: enum: - mediatek,mt2701-mmc + - mediatek,mt6589-mmc - mediatek,mt6779-mmc - mediatek,mt6795-mmc - mediatek,mt7620-mmc From 67fbf5d51c5501d17ee68ba38941ac2c2b1658e3 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:17:24 +0900 Subject: [PATCH 32/98] arm: configs: lenovo-blade: add regulator-fixed Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 13cbcc326d43cf..1a7768cff2090e 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -115,6 +115,10 @@ CONFIG_MMC_MTK=y ## Battery +## Regulator +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y + ## Audio ## Video Accelerator From 46cece3a13f5e64f55e125cdda3e5486e2a43ddf Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:17:40 +0900 Subject: [PATCH 33/98] arm: configs: lenovo-blade: add debugfs Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 1a7768cff2090e..76b5a30f33b0a8 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -154,6 +154,7 @@ CONFIG_BLK_DEV_LOOP=y ### FS CONFIG_UNICODE=y CONFIG_EXT4_FS=y +CONFIG_DEBUG_FS=y CONFIG_VFAT_FS=y # VFAT CONFIG_NLS_CODEPAGE_437=y From f29dac49641f7b223ad46cda3857b1ed7671709f Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:21:33 +0900 Subject: [PATCH 34/98] dt-bindings: pinctrl: re-format mt6589 pinfunc Signed-off-by: Akari Tsuyukusa --- include/dt-bindings/pinctrl/mt6589-pinfunc.h | 3250 +++++++++--------- 1 file changed, 1625 insertions(+), 1625 deletions(-) diff --git a/include/dt-bindings/pinctrl/mt6589-pinfunc.h b/include/dt-bindings/pinctrl/mt6589-pinfunc.h index 0b2880f2a639b4..6399513531a9af 100644 --- a/include/dt-bindings/pinctrl/mt6589-pinfunc.h +++ b/include/dt-bindings/pinctrl/mt6589-pinfunc.h @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #ifndef __MT6589_PINFUNC_H @@ -8,1629 +8,1629 @@ #include -#define MT6589_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT6589_PIN_0_GPIO0__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) -#define MT6589_PIN_0_GPIO0__FUNC_EINT49 (MTK_PIN_NO(0) | 2) -#define MT6589_PIN_0_GPIO0__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) -#define MT6589_PIN_0_GPIO0__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) -#define MT6589_PIN_0_GPIO0__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) -#define MT6589_PIN_0_GPIO0__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) -#define MT6589_PIN_0_GPIO0__FUNC_NALE (MTK_PIN_NO(0) | 7) - -#define MT6589_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT6589_PIN_1_GPIO1__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) -#define MT6589_PIN_1_GPIO1__FUNC_EINT48 (MTK_PIN_NO(1) | 2) -#define MT6589_PIN_1_GPIO1__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) -#define MT6589_PIN_1_GPIO1__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) -#define MT6589_PIN_1_GPIO1__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) -#define MT6589_PIN_1_GPIO1__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) -#define MT6589_PIN_1_GPIO1__FUNC_NCLE (MTK_PIN_NO(1) | 7) - -#define MT6589_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT6589_PIN_2_GPIO2__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) -#define MT6589_PIN_2_GPIO2__FUNC_EINT47 (MTK_PIN_NO(2) | 2) -#define MT6589_PIN_2_GPIO2__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) -#define MT6589_PIN_2_GPIO2__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) -#define MT6589_PIN_2_GPIO2__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) -#define MT6589_PIN_2_GPIO2__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) -#define MT6589_PIN_2_GPIO2__FUNC_NLD4 (MTK_PIN_NO(2) | 7) - -#define MT6589_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT6589_PIN_3_GPIO3__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) -#define MT6589_PIN_3_GPIO3__FUNC_EINT46 (MTK_PIN_NO(3) | 2) -#define MT6589_PIN_3_GPIO3__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) -#define MT6589_PIN_3_GPIO3__FUNC_NLD5 (MTK_PIN_NO(3) | 7) - -#define MT6589_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT6589_PIN_4_GPIO4__FUNC_MSDC0_RSTB (MTK_PIN_NO(4) | 1) -#define MT6589_PIN_4_GPIO4__FUNC_EINT50 (MTK_PIN_NO(4) | 2) -#define MT6589_PIN_4_GPIO4__FUNC_I2SIN_DAT (MTK_PIN_NO(4) | 3) -#define MT6589_PIN_4_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 5) -#define MT6589_PIN_4_GPIO4__FUNC_SPI1_MI (MTK_PIN_NO(4) | 6) -#define MT6589_PIN_4_GPIO4__FUNC_NLD10 (MTK_PIN_NO(4) | 7) - -#define MT6589_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT6589_PIN_5_GPIO5__FUNC_MSDC0_CMD (MTK_PIN_NO(5) | 1) -#define MT6589_PIN_5_GPIO5__FUNC_EINT41 (MTK_PIN_NO(5) | 2) -#define MT6589_PIN_5_GPIO5__FUNC_LRSTB_2X (MTK_PIN_NO(5) | 6) -#define MT6589_PIN_5_GPIO5__FUNC_NRNB (MTK_PIN_NO(5) | 7) - -#define MT6589_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT6589_PIN_6_GPIO6__FUNC_MSDC0_CLK (MTK_PIN_NO(6) | 1) -#define MT6589_PIN_6_GPIO6__FUNC_EINT40 (MTK_PIN_NO(6) | 2) -#define MT6589_PIN_6_GPIO6__FUNC_LPTE (MTK_PIN_NO(6) | 6) -#define MT6589_PIN_6_GPIO6__FUNC_NREB (MTK_PIN_NO(6) | 7) - -#define MT6589_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT6589_PIN_7_GPIO7__FUNC_MSDC0_DAT3 (MTK_PIN_NO(7) | 1) -#define MT6589_PIN_7_GPIO7__FUNC_EINT45 (MTK_PIN_NO(7) | 2) -#define MT6589_PIN_7_GPIO7__FUNC_LSCE0B_2X (MTK_PIN_NO(7) | 6) -#define MT6589_PIN_7_GPIO7__FUNC_NLD7 (MTK_PIN_NO(7) | 7) - -#define MT6589_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT6589_PIN_8_GPIO8__FUNC_MSDC0_DAT2 (MTK_PIN_NO(8) | 1) -#define MT6589_PIN_8_GPIO8__FUNC_EINT44 (MTK_PIN_NO(8) | 2) -#define MT6589_PIN_8_GPIO8__FUNC_LSA0_2X (MTK_PIN_NO(8) | 6) -#define MT6589_PIN_8_GPIO8__FUNC_NLD14 (MTK_PIN_NO(8) | 7) - -#define MT6589_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT6589_PIN_9_GPIO9__FUNC_MSDC0_DAT1 (MTK_PIN_NO(9) | 1) -#define MT6589_PIN_9_GPIO9__FUNC_EINT43 (MTK_PIN_NO(9) | 2) -#define MT6589_PIN_9_GPIO9__FUNC_LSCK_2X (MTK_PIN_NO(9) | 6) -#define MT6589_PIN_9_GPIO9__FUNC_NLD11 (MTK_PIN_NO(9) | 7) - -#define MT6589_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT6589_PIN_10_GPIO10__FUNC_MSDC0_DAT0 (MTK_PIN_NO(10) | 1) -#define MT6589_PIN_10_GPIO10__FUNC_EINT42 (MTK_PIN_NO(10) | 2) -#define MT6589_PIN_10_GPIO10__FUNC_LSDA_2X (MTK_PIN_NO(10) | 6) - -#define MT6589_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT6589_PIN_11_GPIO11__FUNC_NCEB0 (MTK_PIN_NO(11) | 1) -#define MT6589_PIN_11_GPIO11__FUNC_EINT139 (MTK_PIN_NO(11) | 2) -#define MT6589_PIN_11_GPIO11__FUNC_TESTA_OUT4 (MTK_PIN_NO(11) | 7) - -#define MT6589_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT6589_PIN_12_GPIO12__FUNC_NCEB1 (MTK_PIN_NO(12) | 1) -#define MT6589_PIN_12_GPIO12__FUNC_EINT140 (MTK_PIN_NO(12) | 2) -#define MT6589_PIN_12_GPIO12__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(12) | 4) -#define MT6589_PIN_12_GPIO12__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(12) | 5) -#define MT6589_PIN_12_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 6) -#define MT6589_PIN_12_GPIO12__FUNC_TESTA_OUT5 (MTK_PIN_NO(12) | 7) - -#define MT6589_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT6589_PIN_13_GPIO13__FUNC_NRNB (MTK_PIN_NO(13) | 1) -#define MT6589_PIN_13_GPIO13__FUNC_EINT141 (MTK_PIN_NO(13) | 2) -#define MT6589_PIN_13_GPIO13__FUNC_MD_ABB_AFUNC_D_0 (MTK_PIN_NO(13) | 6) -#define MT6589_PIN_13_GPIO13__FUNC_TESTA_OUT6 (MTK_PIN_NO(13) | 7) - -#define MT6589_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT6589_PIN_14_GPIO14__FUNC_NCLE (MTK_PIN_NO(14) | 1) -#define MT6589_PIN_14_GPIO14__FUNC_EINT142 (MTK_PIN_NO(14) | 2) -#define MT6589_PIN_14_GPIO14__FUNC_DPI1_CK_1X (MTK_PIN_NO(14) | 3) -#define MT6589_PIN_14_GPIO14__FUNC_CM2PDN_1X (MTK_PIN_NO(14) | 4) -#define MT6589_PIN_14_GPIO14__FUNC_NALE (MTK_PIN_NO(14) | 6) -#define MT6589_PIN_14_GPIO14__FUNC_TESTA_OUT7 (MTK_PIN_NO(14) | 7) - -#define MT6589_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT6589_PIN_15_GPIO15__FUNC_NALE (MTK_PIN_NO(15) | 1) -#define MT6589_PIN_15_GPIO15__FUNC_EINT143 (MTK_PIN_NO(15) | 2) -#define MT6589_PIN_15_GPIO15__FUNC_DPI1_DE_1X (MTK_PIN_NO(15) | 3) -#define MT6589_PIN_15_GPIO15__FUNC_CM2MCLK_1X (MTK_PIN_NO(15) | 4) -#define MT6589_PIN_15_GPIO15__FUNC_IRDA_RXD (MTK_PIN_NO(15) | 5) -#define MT6589_PIN_15_GPIO15__FUNC_NCLE (MTK_PIN_NO(15) | 6) -#define MT6589_PIN_15_GPIO15__FUNC_TESTA_OUT8 (MTK_PIN_NO(15) | 7) - -#define MT6589_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT6589_PIN_16_GPIO16__FUNC_NREB (MTK_PIN_NO(16) | 1) -#define MT6589_PIN_16_GPIO16__FUNC_EINT144 (MTK_PIN_NO(16) | 2) -#define MT6589_PIN_16_GPIO16__FUNC_DPI1_HSYNC_1X (MTK_PIN_NO(16) | 3) -#define MT6589_PIN_16_GPIO16__FUNC_CM2RST_1X (MTK_PIN_NO(16) | 4) -#define MT6589_PIN_16_GPIO16__FUNC_IRDA_TXD (MTK_PIN_NO(16) | 5) -#define MT6589_PIN_16_GPIO16__FUNC_MD_ABB_AFUNC_D_1 (MTK_PIN_NO(16) | 6) -#define MT6589_PIN_16_GPIO16__FUNC_TESTA_OUT9 (MTK_PIN_NO(16) | 7) - -#define MT6589_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT6589_PIN_17_GPIO17__FUNC_NWEB (MTK_PIN_NO(17) | 1) -#define MT6589_PIN_17_GPIO17__FUNC_EINT145 (MTK_PIN_NO(17) | 2) -#define MT6589_PIN_17_GPIO17__FUNC_DPI1_VSYNC_1X (MTK_PIN_NO(17) | 3) -#define MT6589_PIN_17_GPIO17__FUNC_CM2PCLK_1X (MTK_PIN_NO(17) | 4) -#define MT6589_PIN_17_GPIO17__FUNC_IRDA_PDN (MTK_PIN_NO(17) | 5) -#define MT6589_PIN_17_GPIO17__FUNC_MD_ABB_AFUNC_D_2 (MTK_PIN_NO(17) | 6) -#define MT6589_PIN_17_GPIO17__FUNC_TESTA_OUT10 (MTK_PIN_NO(17) | 7) - -#define MT6589_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT6589_PIN_18_GPIO18__FUNC_NLD0 (MTK_PIN_NO(18) | 1) -#define MT6589_PIN_18_GPIO18__FUNC_EINT146 (MTK_PIN_NO(18) | 2) -#define MT6589_PIN_18_GPIO18__FUNC_DPI1_D_1X_0 (MTK_PIN_NO(18) | 3) -#define MT6589_PIN_18_GPIO18__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(18) | 4) -#define MT6589_PIN_18_GPIO18__FUNC_I2SIN_CK (MTK_PIN_NO(18) | 5) -#define MT6589_PIN_18_GPIO18__FUNC_DAC_CK (MTK_PIN_NO(18) | 6) -#define MT6589_PIN_18_GPIO18__FUNC_TESTA_OUT11 (MTK_PIN_NO(18) | 7) - -#define MT6589_PIN_19_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT6589_PIN_19_GPIO19__FUNC_NLD1 (MTK_PIN_NO(19) | 1) -#define MT6589_PIN_19_GPIO19__FUNC_EINT147 (MTK_PIN_NO(19) | 2) -#define MT6589_PIN_19_GPIO19__FUNC_DPI1_D_1X_1 (MTK_PIN_NO(19) | 3) -#define MT6589_PIN_19_GPIO19__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(19) | 4) -#define MT6589_PIN_19_GPIO19__FUNC_I2SIN_WS (MTK_PIN_NO(19) | 5) -#define MT6589_PIN_19_GPIO19__FUNC_DAC_WS (MTK_PIN_NO(19) | 6) -#define MT6589_PIN_19_GPIO19__FUNC_TESTA_OUT12 (MTK_PIN_NO(19) | 7) - -#define MT6589_PIN_20_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT6589_PIN_20_GPIO20__FUNC_NLD2 (MTK_PIN_NO(20) | 1) -#define MT6589_PIN_20_GPIO20__FUNC_EINT148 (MTK_PIN_NO(20) | 2) -#define MT6589_PIN_20_GPIO20__FUNC_DPI1_D_1X_2 (MTK_PIN_NO(20) | 3) -#define MT6589_PIN_20_GPIO20__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(20) | 4) -#define MT6589_PIN_20_GPIO20__FUNC_I2SOUT_DAT (MTK_PIN_NO(20) | 5) -#define MT6589_PIN_20_GPIO20__FUNC_DAC_DAT_OUT (MTK_PIN_NO(20) | 6) -#define MT6589_PIN_20_GPIO20__FUNC_TESTA_OUT13 (MTK_PIN_NO(20) | 7) - -#define MT6589_PIN_21_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT6589_PIN_21_GPIO21__FUNC_NLD3 (MTK_PIN_NO(21) | 1) -#define MT6589_PIN_21_GPIO21__FUNC_EINT149 (MTK_PIN_NO(21) | 2) -#define MT6589_PIN_21_GPIO21__FUNC_DPI1_D_1X_3 (MTK_PIN_NO(21) | 3) -#define MT6589_PIN_21_GPIO21__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(21) | 4) -#define MT6589_PIN_21_GPIO21__FUNC_MD_ABB_AFUNC_D_3 (MTK_PIN_NO(21) | 6) -#define MT6589_PIN_21_GPIO21__FUNC_TESTA_OUT14 (MTK_PIN_NO(21) | 7) - -#define MT6589_PIN_22_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT6589_PIN_22_GPIO22__FUNC_NLD4 (MTK_PIN_NO(22) | 1) -#define MT6589_PIN_22_GPIO22__FUNC_EINT150 (MTK_PIN_NO(22) | 2) -#define MT6589_PIN_22_GPIO22__FUNC_DPI1_D_1X_4 (MTK_PIN_NO(22) | 3) -#define MT6589_PIN_22_GPIO22__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(22) | 4) -#define MT6589_PIN_22_GPIO22__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(22) | 5) -#define MT6589_PIN_22_GPIO22__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(22) | 6) -#define MT6589_PIN_22_GPIO22__FUNC_TESTA_OUT15 (MTK_PIN_NO(22) | 7) - -#define MT6589_PIN_23_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT6589_PIN_23_GPIO23__FUNC_NLD5 (MTK_PIN_NO(23) | 1) -#define MT6589_PIN_23_GPIO23__FUNC_EINT151 (MTK_PIN_NO(23) | 2) -#define MT6589_PIN_23_GPIO23__FUNC_DPI1_D_1X_5 (MTK_PIN_NO(23) | 3) -#define MT6589_PIN_23_GPIO23__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(23) | 4) -#define MT6589_PIN_23_GPIO23__FUNC_MD_ABB_AFUNC_D_4 (MTK_PIN_NO(23) | 6) -#define MT6589_PIN_23_GPIO23__FUNC_TESTA_OUT16 (MTK_PIN_NO(23) | 7) - -#define MT6589_PIN_24_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT6589_PIN_24_GPIO24__FUNC_NLD6 (MTK_PIN_NO(24) | 1) -#define MT6589_PIN_24_GPIO24__FUNC_EINT152 (MTK_PIN_NO(24) | 2) -#define MT6589_PIN_24_GPIO24__FUNC_DPI1_D_1X_6 (MTK_PIN_NO(24) | 3) -#define MT6589_PIN_24_GPIO24__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(24) | 4) -#define MT6589_PIN_24_GPIO24__FUNC_MD_ABB_AFUNC_D_5 (MTK_PIN_NO(24) | 6) -#define MT6589_PIN_24_GPIO24__FUNC_TESTA_OUT17 (MTK_PIN_NO(24) | 7) - -#define MT6589_PIN_25_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT6589_PIN_25_GPIO25__FUNC_NLD7 (MTK_PIN_NO(25) | 1) -#define MT6589_PIN_25_GPIO25__FUNC_EINT153 (MTK_PIN_NO(25) | 2) -#define MT6589_PIN_25_GPIO25__FUNC_DPI1_D_1X_7 (MTK_PIN_NO(25) | 3) -#define MT6589_PIN_25_GPIO25__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(25) | 4) -#define MT6589_PIN_25_GPIO25__FUNC_MD_ABB_AFUNC_D_6 (MTK_PIN_NO(25) | 6) -#define MT6589_PIN_25_GPIO25__FUNC_TESTA_OUT18 (MTK_PIN_NO(25) | 7) - -#define MT6589_PIN_26_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT6589_PIN_26_GPIO26__FUNC_NLD8 (MTK_PIN_NO(26) | 1) -#define MT6589_PIN_26_GPIO26__FUNC_EINT154 (MTK_PIN_NO(26) | 2) -#define MT6589_PIN_26_GPIO26__FUNC_DPI1_D_1X_8 (MTK_PIN_NO(26) | 3) -#define MT6589_PIN_26_GPIO26__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(26) | 4) -#define MT6589_PIN_26_GPIO26__FUNC_MD_ABB_AFUNC_D_7 (MTK_PIN_NO(26) | 6) -#define MT6589_PIN_26_GPIO26__FUNC_TESTA_OUT19 (MTK_PIN_NO(26) | 7) - -#define MT6589_PIN_27_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT6589_PIN_27_GPIO27__FUNC_NLD9 (MTK_PIN_NO(27) | 1) -#define MT6589_PIN_27_GPIO27__FUNC_EINT155 (MTK_PIN_NO(27) | 2) -#define MT6589_PIN_27_GPIO27__FUNC_DPI1_D_1X_9 (MTK_PIN_NO(27) | 3) -#define MT6589_PIN_27_GPIO27__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(27) | 4) -#define MT6589_PIN_27_GPIO27__FUNC_PWM1 (MTK_PIN_NO(27) | 5) -#define MT6589_PIN_27_GPIO27__FUNC_MD_ABB_AFUNC_D_8 (MTK_PIN_NO(27) | 6) -#define MT6589_PIN_27_GPIO27__FUNC_TESTA_OUT20 (MTK_PIN_NO(27) | 7) - -#define MT6589_PIN_28_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT6589_PIN_28_GPIO28__FUNC_NLD10 (MTK_PIN_NO(28) | 1) -#define MT6589_PIN_28_GPIO28__FUNC_EINT156 (MTK_PIN_NO(28) | 2) -#define MT6589_PIN_28_GPIO28__FUNC_DPI1_D_1X_10 (MTK_PIN_NO(28) | 3) -#define MT6589_PIN_28_GPIO28__FUNC_CM2VSYNC_1X (MTK_PIN_NO(28) | 4) -#define MT6589_PIN_28_GPIO28__FUNC_PWM2 (MTK_PIN_NO(28) | 5) -#define MT6589_PIN_28_GPIO28__FUNC_MD_ABB_AFUNC_D_9 (MTK_PIN_NO(28) | 6) -#define MT6589_PIN_28_GPIO28__FUNC_TESTA_OUT21 (MTK_PIN_NO(28) | 7) - -#define MT6589_PIN_29_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT6589_PIN_29_GPIO29__FUNC_NLD11 (MTK_PIN_NO(29) | 1) -#define MT6589_PIN_29_GPIO29__FUNC_EINT157 (MTK_PIN_NO(29) | 2) -#define MT6589_PIN_29_GPIO29__FUNC_DPI1_D_1X_11 (MTK_PIN_NO(29) | 3) -#define MT6589_PIN_29_GPIO29__FUNC_CM2HSYNC_1X (MTK_PIN_NO(29) | 4) -#define MT6589_PIN_29_GPIO29__FUNC_PWM3 (MTK_PIN_NO(29) | 5) -#define MT6589_PIN_29_GPIO29__FUNC_MD_ABB_AFUNC_D_10 (MTK_PIN_NO(29) | 6) -#define MT6589_PIN_29_GPIO29__FUNC_TESTA_OUT22 (MTK_PIN_NO(29) | 7) - -#define MT6589_PIN_30_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT6589_PIN_30_GPIO30__FUNC_NLD12 (MTK_PIN_NO(30) | 1) -#define MT6589_PIN_30_GPIO30__FUNC_EINT158 (MTK_PIN_NO(30) | 2) -#define MT6589_PIN_30_GPIO30__FUNC_I2SIN_CK (MTK_PIN_NO(30) | 3) -#define MT6589_PIN_30_GPIO30__FUNC_DAC_CK (MTK_PIN_NO(30) | 4) -#define MT6589_PIN_30_GPIO30__FUNC_PCM1_CK (MTK_PIN_NO(30) | 5) -#define MT6589_PIN_30_GPIO30__FUNC_MD_ABB_AFUNC_D_11 (MTK_PIN_NO(30) | 6) -#define MT6589_PIN_30_GPIO30__FUNC_TESTA_OUT23 (MTK_PIN_NO(30) | 7) - -#define MT6589_PIN_31_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT6589_PIN_31_GPIO31__FUNC_NLD13 (MTK_PIN_NO(31) | 1) -#define MT6589_PIN_31_GPIO31__FUNC_EINT159 (MTK_PIN_NO(31) | 2) -#define MT6589_PIN_31_GPIO31__FUNC_I2SIN_WS (MTK_PIN_NO(31) | 3) -#define MT6589_PIN_31_GPIO31__FUNC_DAC_WS (MTK_PIN_NO(31) | 4) -#define MT6589_PIN_31_GPIO31__FUNC_PCM1_WS (MTK_PIN_NO(31) | 5) -#define MT6589_PIN_31_GPIO31__FUNC_MD_ABB_AFUNC_D_12 (MTK_PIN_NO(31) | 6) -#define MT6589_PIN_31_GPIO31__FUNC_TESTA_OUT24 (MTK_PIN_NO(31) | 7) - -#define MT6589_PIN_32_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT6589_PIN_32_GPIO32__FUNC_NLD14 (MTK_PIN_NO(32) | 1) -#define MT6589_PIN_32_GPIO32__FUNC_EINT160 (MTK_PIN_NO(32) | 2) -#define MT6589_PIN_32_GPIO32__FUNC_I2SOUT_DAT (MTK_PIN_NO(32) | 3) -#define MT6589_PIN_32_GPIO32__FUNC_DAC_DAT_OUT (MTK_PIN_NO(32) | 4) -#define MT6589_PIN_32_GPIO32__FUNC_PCM1_DO (MTK_PIN_NO(32) | 5) -#define MT6589_PIN_32_GPIO32__FUNC_MD_ABB_AFUNC_D_13 (MTK_PIN_NO(32) | 6) -#define MT6589_PIN_32_GPIO32__FUNC_TESTA_OUT25 (MTK_PIN_NO(32) | 7) - -#define MT6589_PIN_33_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT6589_PIN_33_GPIO33__FUNC_NLD15 (MTK_PIN_NO(33) | 1) -#define MT6589_PIN_33_GPIO33__FUNC_EINT161 (MTK_PIN_NO(33) | 2) -#define MT6589_PIN_33_GPIO33__FUNC_DISP_PWM (MTK_PIN_NO(33) | 3) -#define MT6589_PIN_33_GPIO33__FUNC_PWM4 (MTK_PIN_NO(33) | 4) -#define MT6589_PIN_33_GPIO33__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) -#define MT6589_PIN_33_GPIO33__FUNC_MD_ABB_AFUNC_D_14 (MTK_PIN_NO(33) | 6) -#define MT6589_PIN_33_GPIO33__FUNC_TESTA_OUT26 (MTK_PIN_NO(33) | 7) - -#define MT6589_PIN_34_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT6589_PIN_34_GPIO34__FUNC_EINT0 (MTK_PIN_NO(34) | 1) -#define MT6589_PIN_34_GPIO34__FUNC_PWM1 (MTK_PIN_NO(34) | 2) -#define MT6589_PIN_34_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 3) -#define MT6589_PIN_34_GPIO34__FUNC_MD2_UTXD (MTK_PIN_NO(34) | 5) -#define MT6589_PIN_34_GPIO34__FUNC_MD1_EINT1 (MTK_PIN_NO(34) | 6) -#define MT6589_PIN_34_GPIO34__FUNC_USB_SCL (MTK_PIN_NO(34) | 7) - -#define MT6589_PIN_35_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT6589_PIN_35_GPIO35__FUNC_EINT1 (MTK_PIN_NO(35) | 1) -#define MT6589_PIN_35_GPIO35__FUNC_PWM2 (MTK_PIN_NO(35) | 2) -#define MT6589_PIN_35_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 3) -#define MT6589_PIN_35_GPIO35__FUNC_MD2_URXD (MTK_PIN_NO(35) | 5) -#define MT6589_PIN_35_GPIO35__FUNC_MD1_EINT2 (MTK_PIN_NO(35) | 6) -#define MT6589_PIN_35_GPIO35__FUNC_USB_SDA (MTK_PIN_NO(35) | 7) - -#define MT6589_PIN_36_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT6589_PIN_36_GPIO36__FUNC_EINT2 (MTK_PIN_NO(36) | 1) -#define MT6589_PIN_36_GPIO36__FUNC_PWM3 (MTK_PIN_NO(36) | 2) -#define MT6589_PIN_36_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 3) -#define MT6589_PIN_36_GPIO36__FUNC_SRCLKENAI2 (MTK_PIN_NO(36) | 4) -#define MT6589_PIN_36_GPIO36__FUNC_MD1_EINT3 (MTK_PIN_NO(36) | 6) - -#define MT6589_PIN_37_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT6589_PIN_37_GPIO37__FUNC_EINT3 (MTK_PIN_NO(37) | 1) -#define MT6589_PIN_37_GPIO37__FUNC_MD1_EINT5 (MTK_PIN_NO(37) | 6) -#define MT6589_PIN_37_GPIO37__FUNC_EXT_26M_CK (MTK_PIN_NO(37) | 7) - -#define MT6589_PIN_38_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT6589_PIN_38_GPIO38__FUNC_EINT4 (MTK_PIN_NO(38) | 1) -#define MT6589_PIN_38_GPIO38__FUNC_PWM4 (MTK_PIN_NO(38) | 2) -#define MT6589_PIN_38_GPIO38__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(38) | 3) -#define MT6589_PIN_38_GPIO38__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(38) | 4) -#define MT6589_PIN_38_GPIO38__FUNC_USB_DRVVBUS (MTK_PIN_NO(38) | 5) -#define MT6589_PIN_38_GPIO38__FUNC_MD1_EINT4 (MTK_PIN_NO(38) | 6) - -#define MT6589_PIN_39_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT6589_PIN_39_GPIO39__FUNC_PWRAP_SPIDI (MTK_PIN_NO(39) | 1) -#define MT6589_PIN_39_GPIO39__FUNC_EINT29 (MTK_PIN_NO(39) | 2) - -#define MT6589_PIN_40_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT6589_PIN_40_GPIO40__FUNC_PWRAP_SPIDO (MTK_PIN_NO(40) | 1) -#define MT6589_PIN_40_GPIO40__FUNC_EINT28 (MTK_PIN_NO(40) | 2) - -#define MT6589_PIN_41_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT6589_PIN_41_GPIO41__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(41) | 1) -#define MT6589_PIN_41_GPIO41__FUNC_EINT27 (MTK_PIN_NO(41) | 2) - -#define MT6589_PIN_42_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT6589_PIN_42_GPIO42__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(42) | 1) -#define MT6589_PIN_42_GPIO42__FUNC_EINT26 (MTK_PIN_NO(42) | 2) - -#define MT6589_PIN_43_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT6589_PIN_43_GPIO43__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(43) | 1) -#define MT6589_PIN_43_GPIO43__FUNC_EINT25 (MTK_PIN_NO(43) | 2) - -#define MT6589_PIN_44_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT6589_PIN_44_GPIO44__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(44) | 1) -#define MT6589_PIN_44_GPIO44__FUNC_EINT30 (MTK_PIN_NO(44) | 2) -#define MT6589_PIN_44_GPIO44__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(44) | 3) -#define MT6589_PIN_44_GPIO44__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(44) | 4) -#define MT6589_PIN_44_GPIO44__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(44) | 5) -#define MT6589_PIN_44_GPIO44__FUNC_MD_ABB_AFUNC_D_15 (MTK_PIN_NO(44) | 6) - -#define MT6589_PIN_45_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT6589_PIN_45_GPIO45__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(45) | 1) -#define MT6589_PIN_45_GPIO45__FUNC_EINT31 (MTK_PIN_NO(45) | 2) -#define MT6589_PIN_45_GPIO45__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(45) | 3) -#define MT6589_PIN_45_GPIO45__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(45) | 4) -#define MT6589_PIN_45_GPIO45__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(45) | 5) -#define MT6589_PIN_45_GPIO45__FUNC_MD_ABB_AFUNC_D_16 (MTK_PIN_NO(45) | 6) - -#define MT6589_PIN_46_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT6589_PIN_46_GPIO46__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(46) | 1) -#define MT6589_PIN_46_GPIO46__FUNC_EINT32 (MTK_PIN_NO(46) | 2) -#define MT6589_PIN_46_GPIO46__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(46) | 3) -#define MT6589_PIN_46_GPIO46__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(46) | 4) -#define MT6589_PIN_46_GPIO46__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(46) | 5) -#define MT6589_PIN_46_GPIO46__FUNC_MD_ABB_AFUNC_D_17 (MTK_PIN_NO(46) | 6) - -#define MT6589_PIN_47_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT6589_PIN_47_GPIO47__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(47) | 1) -#define MT6589_PIN_47_GPIO47__FUNC_EINT33 (MTK_PIN_NO(47) | 2) -#define MT6589_PIN_47_GPIO47__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(47) | 3) -#define MT6589_PIN_47_GPIO47__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(47) | 4) -#define MT6589_PIN_47_GPIO47__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(47) | 5) -#define MT6589_PIN_47_GPIO47__FUNC_MD_ABB_AFUNC_D_18 (MTK_PIN_NO(47) | 6) - -#define MT6589_PIN_48_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT6589_PIN_48_GPIO48__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(48) | 1) -#define MT6589_PIN_48_GPIO48__FUNC_EINT34 (MTK_PIN_NO(48) | 2) -#define MT6589_PIN_48_GPIO48__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(48) | 3) -#define MT6589_PIN_48_GPIO48__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(48) | 4) -#define MT6589_PIN_48_GPIO48__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(48) | 5) -#define MT6589_PIN_48_GPIO48__FUNC_MD_ABB_AFUNC_D_19 (MTK_PIN_NO(48) | 6) - -#define MT6589_PIN_49_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT6589_PIN_49_GPIO49__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(49) | 1) -#define MT6589_PIN_49_GPIO49__FUNC_EINT35 (MTK_PIN_NO(49) | 2) -#define MT6589_PIN_49_GPIO49__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(49) | 3) -#define MT6589_PIN_49_GPIO49__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(49) | 4) -#define MT6589_PIN_49_GPIO49__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(49) | 5) -#define MT6589_PIN_49_GPIO49__FUNC_MD_ABB_AFUNC_D_20 (MTK_PIN_NO(49) | 6) - -#define MT6589_PIN_50_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT6589_PIN_50_GPIO50__FUNC_ADC_CK (MTK_PIN_NO(50) | 1) -#define MT6589_PIN_50_GPIO50__FUNC_EINT19 (MTK_PIN_NO(50) | 2) - -#define MT6589_PIN_51_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT6589_PIN_51_GPIO51__FUNC_ADC_WS (MTK_PIN_NO(51) | 1) -#define MT6589_PIN_51_GPIO51__FUNC_EINT21 (MTK_PIN_NO(51) | 2) - -#define MT6589_PIN_52_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT6589_PIN_52_GPIO52__FUNC_ADC_DAT_IN (MTK_PIN_NO(52) | 1) -#define MT6589_PIN_52_GPIO52__FUNC_EINT20 (MTK_PIN_NO(52) | 2) - -#define MT6589_PIN_53_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT6589_PIN_53_GPIO53__FUNC_DAC_CK (MTK_PIN_NO(53) | 1) -#define MT6589_PIN_53_GPIO53__FUNC_EINT22 (MTK_PIN_NO(53) | 2) - -#define MT6589_PIN_54_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT6589_PIN_54_GPIO54__FUNC_DAC_WS (MTK_PIN_NO(54) | 1) -#define MT6589_PIN_54_GPIO54__FUNC_EINT24 (MTK_PIN_NO(54) | 2) - -#define MT6589_PIN_55_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT6589_PIN_55_GPIO55__FUNC_DAC_DAT_OUT (MTK_PIN_NO(55) | 1) -#define MT6589_PIN_55_GPIO55__FUNC_EINT23 (MTK_PIN_NO(55) | 2) - -#define MT6589_PIN_56_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT6589_PIN_56_GPIO56__FUNC_RTC32K_CK (MTK_PIN_NO(56) | 1) - -#define MT6589_PIN_57_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT6589_PIN_57_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 1) -#define MT6589_PIN_57_GPIO57__FUNC_EINT34 (MTK_PIN_NO(57) | 2) - -#define MT6589_PIN_58_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT6589_PIN_58_GPIO58__FUNC_WATCHDOG (MTK_PIN_NO(58) | 1) -#define MT6589_PIN_58_GPIO58__FUNC_EINT36 (MTK_PIN_NO(58) | 2) - -#define MT6589_PIN_59_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT6589_PIN_59_GPIO59__FUNC_SRCLKENA (MTK_PIN_NO(59) | 1) -#define MT6589_PIN_59_GPIO59__FUNC_EINT38 (MTK_PIN_NO(59) | 2) - -#define MT6589_PIN_60_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT6589_PIN_60_GPIO60__FUNC_SRCVOLTEN (MTK_PIN_NO(60) | 1) -#define MT6589_PIN_60_GPIO60__FUNC_EINT37 (MTK_PIN_NO(60) | 2) - -#define MT6589_PIN_61_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT6589_PIN_61_GPIO61__FUNC_JTCK (MTK_PIN_NO(61) | 1) -#define MT6589_PIN_61_GPIO61__FUNC_EINT188 (MTK_PIN_NO(61) | 2) -#define MT6589_PIN_61_GPIO61__FUNC_DSP1_ICK (MTK_PIN_NO(61) | 3) -#define MT6589_PIN_61_GPIO61__FUNC_MD2_TCK_PAD (MTK_PIN_NO(61) | 7) - -#define MT6589_PIN_62_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT6589_PIN_62_GPIO62__FUNC_JTDO (MTK_PIN_NO(62) | 1) -#define MT6589_PIN_62_GPIO62__FUNC_EINT190 (MTK_PIN_NO(62) | 2) -#define MT6589_PIN_62_GPIO62__FUNC_DSP2_IMS (MTK_PIN_NO(62) | 3) -#define MT6589_PIN_62_GPIO62__FUNC_MD2_TDO_PAD (MTK_PIN_NO(62) | 7) - -#define MT6589_PIN_63_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT6589_PIN_63_GPIO63__FUNC_JTRST_B (MTK_PIN_NO(63) | 1) -#define MT6589_PIN_63_GPIO63__FUNC_EINT0 (MTK_PIN_NO(63) | 2) -#define MT6589_PIN_63_GPIO63__FUNC_DSP2_ICK (MTK_PIN_NO(63) | 3) -#define MT6589_PIN_63_GPIO63__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(63) | 7) - -#define MT6589_PIN_64_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT6589_PIN_64_GPIO64__FUNC_JTDI (MTK_PIN_NO(64) | 1) -#define MT6589_PIN_64_GPIO64__FUNC_EINT189 (MTK_PIN_NO(64) | 2) -#define MT6589_PIN_64_GPIO64__FUNC_DSP1_IMS (MTK_PIN_NO(64) | 3) -#define MT6589_PIN_64_GPIO64__FUNC_MD2_TDI_PAD (MTK_PIN_NO(64) | 7) - -#define MT6589_PIN_65_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT6589_PIN_65_GPIO65__FUNC_JRTCK (MTK_PIN_NO(65) | 1) -#define MT6589_PIN_65_GPIO65__FUNC_EINT187 (MTK_PIN_NO(65) | 2) -#define MT6589_PIN_65_GPIO65__FUNC_DSP1_ID (MTK_PIN_NO(65) | 3) -#define MT6589_PIN_65_GPIO65__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(65) | 7) - -#define MT6589_PIN_66_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT6589_PIN_66_GPIO66__FUNC_JTMS (MTK_PIN_NO(66) | 1) -#define MT6589_PIN_66_GPIO66__FUNC_EINT191 (MTK_PIN_NO(66) | 2) -#define MT6589_PIN_66_GPIO66__FUNC_DSP2_ID (MTK_PIN_NO(66) | 3) -#define MT6589_PIN_66_GPIO66__FUNC_MD2_TMS_PAD (MTK_PIN_NO(66) | 7) - -#define MT6589_PIN_67_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT6589_PIN_67_GPIO67__FUNC_SDA3 (MTK_PIN_NO(67) | 1) -#define MT6589_PIN_67_GPIO67__FUNC_EINT97 (MTK_PIN_NO(67) | 2) -#define MT6589_PIN_67_GPIO67__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(67) | 7) - -#define MT6589_PIN_68_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT6589_PIN_68_GPIO68__FUNC_SCL3 (MTK_PIN_NO(68) | 1) -#define MT6589_PIN_68_GPIO68__FUNC_EINT96 (MTK_PIN_NO(68) | 2) -#define MT6589_PIN_68_GPIO68__FUNC_CLKM6 (MTK_PIN_NO(68) | 3) -#define MT6589_PIN_68_GPIO68__FUNC_PWM6 (MTK_PIN_NO(68) | 4) -#define MT6589_PIN_68_GPIO68__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(68) | 7) - -#define MT6589_PIN_69_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT6589_PIN_69_GPIO69__FUNC_URXD2 (MTK_PIN_NO(69) | 1) -#define MT6589_PIN_69_GPIO69__FUNC_EINT83 (MTK_PIN_NO(69) | 2) -#define MT6589_PIN_69_GPIO69__FUNC_BSI2_CLK (MTK_PIN_NO(69) | 3) -#define MT6589_PIN_69_GPIO69__FUNC_MD1_URXD (MTK_PIN_NO(69) | 4) -#define MT6589_PIN_69_GPIO69__FUNC_CLKM3 (MTK_PIN_NO(69) | 5) -#define MT6589_PIN_69_GPIO69__FUNC_UTXD2 (MTK_PIN_NO(69) | 6) -#define MT6589_PIN_69_GPIO69__FUNC_MD1_EINT4 (MTK_PIN_NO(69) | 7) - -#define MT6589_PIN_70_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT6589_PIN_70_GPIO70__FUNC_UTXD2 (MTK_PIN_NO(70) | 1) -#define MT6589_PIN_70_GPIO70__FUNC_EINT82 (MTK_PIN_NO(70) | 2) -#define MT6589_PIN_70_GPIO70__FUNC_BSI2_CS (MTK_PIN_NO(70) | 3) -#define MT6589_PIN_70_GPIO70__FUNC_MD1_UTXD (MTK_PIN_NO(70) | 4) -#define MT6589_PIN_70_GPIO70__FUNC_CLKM2 (MTK_PIN_NO(70) | 5) -#define MT6589_PIN_70_GPIO70__FUNC_URXD2 (MTK_PIN_NO(70) | 6) -#define MT6589_PIN_70_GPIO70__FUNC_MD1_EINT3 (MTK_PIN_NO(70) | 7) - -#define MT6589_PIN_71_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT6589_PIN_71_GPIO71__FUNC_UCTS2 (MTK_PIN_NO(71) | 1) -#define MT6589_PIN_71_GPIO71__FUNC_EINT84 (MTK_PIN_NO(71) | 2) -#define MT6589_PIN_71_GPIO71__FUNC_BSI2_DATA0 (MTK_PIN_NO(71) | 3) -#define MT6589_PIN_71_GPIO71__FUNC_MD2_UTXD (MTK_PIN_NO(71) | 4) -#define MT6589_PIN_71_GPIO71__FUNC_PWM1 (MTK_PIN_NO(71) | 5) -#define MT6589_PIN_71_GPIO71__FUNC_URTS2 (MTK_PIN_NO(71) | 6) -#define MT6589_PIN_71_GPIO71__FUNC_MD2_EINT1 (MTK_PIN_NO(71) | 7) - -#define MT6589_PIN_72_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT6589_PIN_72_GPIO72__FUNC_URTS2 (MTK_PIN_NO(72) | 1) -#define MT6589_PIN_72_GPIO72__FUNC_EINT85 (MTK_PIN_NO(72) | 2) -#define MT6589_PIN_72_GPIO72__FUNC_BSI2_DATA1 (MTK_PIN_NO(72) | 3) -#define MT6589_PIN_72_GPIO72__FUNC_MD2_URXD (MTK_PIN_NO(72) | 4) -#define MT6589_PIN_72_GPIO72__FUNC_PWM2 (MTK_PIN_NO(72) | 5) -#define MT6589_PIN_72_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 6) -#define MT6589_PIN_72_GPIO72__FUNC_MD2_EINT2 (MTK_PIN_NO(72) | 7) - -#define MT6589_PIN_73_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT6589_PIN_73_GPIO73__FUNC_PWM1 (MTK_PIN_NO(73) | 1) -#define MT6589_PIN_73_GPIO73__FUNC_EINT73 (MTK_PIN_NO(73) | 2) -#define MT6589_PIN_73_GPIO73__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(73) | 3) -#define MT6589_PIN_73_GPIO73__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(73) | 4) -#define MT6589_PIN_73_GPIO73__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) -#define MT6589_PIN_73_GPIO73__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) -#define MT6589_PIN_73_GPIO73__FUNC_MD2_TCK_PAD (MTK_PIN_NO(73) | 7) - -#define MT6589_PIN_74_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT6589_PIN_74_GPIO74__FUNC_PWM2 (MTK_PIN_NO(74) | 1) -#define MT6589_PIN_74_GPIO74__FUNC_EINT74 (MTK_PIN_NO(74) | 2) -#define MT6589_PIN_74_GPIO74__FUNC_BPI2_BUS11 (MTK_PIN_NO(74) | 3) -#define MT6589_PIN_74_GPIO74__FUNC_PWM5 (MTK_PIN_NO(74) | 4) -#define MT6589_PIN_74_GPIO74__FUNC_URXD2 (MTK_PIN_NO(74) | 5) -#define MT6589_PIN_74_GPIO74__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) -#define MT6589_PIN_74_GPIO74__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(74) | 7) - -#define MT6589_PIN_75_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT6589_PIN_75_GPIO75__FUNC_PWM3 (MTK_PIN_NO(75) | 1) -#define MT6589_PIN_75_GPIO75__FUNC_EINT75 (MTK_PIN_NO(75) | 2) -#define MT6589_PIN_75_GPIO75__FUNC_BPI2_BUS12 (MTK_PIN_NO(75) | 3) -#define MT6589_PIN_75_GPIO75__FUNC_PWM6 (MTK_PIN_NO(75) | 4) -#define MT6589_PIN_75_GPIO75__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) -#define MT6589_PIN_75_GPIO75__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) -#define MT6589_PIN_75_GPIO75__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(75) | 7) - -#define MT6589_PIN_76_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT6589_PIN_76_GPIO76__FUNC_PWM4 (MTK_PIN_NO(76) | 1) -#define MT6589_PIN_76_GPIO76__FUNC_EINT76 (MTK_PIN_NO(76) | 2) -#define MT6589_PIN_76_GPIO76__FUNC_BPI2_BUS13 (MTK_PIN_NO(76) | 3) -#define MT6589_PIN_76_GPIO76__FUNC_PWM7 (MTK_PIN_NO(76) | 4) -#define MT6589_PIN_76_GPIO76__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) -#define MT6589_PIN_76_GPIO76__FUNC_MD2_TMS_PAD (MTK_PIN_NO(76) | 7) - -#define MT6589_PIN_77_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT6589_PIN_77_GPIO77__FUNC_URXD1 (MTK_PIN_NO(77) | 1) -#define MT6589_PIN_77_GPIO77__FUNC_EINT79 (MTK_PIN_NO(77) | 2) -#define MT6589_PIN_77_GPIO77__FUNC_URXD4 (MTK_PIN_NO(77) | 3) -#define MT6589_PIN_77_GPIO77__FUNC_MD1_URXD (MTK_PIN_NO(77) | 4) -#define MT6589_PIN_77_GPIO77__FUNC_MD2_URXD (MTK_PIN_NO(77) | 5) -#define MT6589_PIN_77_GPIO77__FUNC_UTXD1 (MTK_PIN_NO(77) | 6) -#define MT6589_PIN_77_GPIO77__FUNC_MD2_TDO_PAD (MTK_PIN_NO(77) | 7) - -#define MT6589_PIN_78_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT6589_PIN_78_GPIO78__FUNC_UTXD1 (MTK_PIN_NO(78) | 1) -#define MT6589_PIN_78_GPIO78__FUNC_EINT78 (MTK_PIN_NO(78) | 2) -#define MT6589_PIN_78_GPIO78__FUNC_UTXD4 (MTK_PIN_NO(78) | 3) -#define MT6589_PIN_78_GPIO78__FUNC_MD1_UTXD (MTK_PIN_NO(78) | 4) -#define MT6589_PIN_78_GPIO78__FUNC_MD2_UTXD (MTK_PIN_NO(78) | 5) -#define MT6589_PIN_78_GPIO78__FUNC_URXD1 (MTK_PIN_NO(78) | 6) -#define MT6589_PIN_78_GPIO78__FUNC_MD2_TDI_PAD (MTK_PIN_NO(78) | 7) - -#define MT6589_PIN_79_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT6589_PIN_79_GPIO79__FUNC_UCTS1 (MTK_PIN_NO(79) | 1) -#define MT6589_PIN_79_GPIO79__FUNC_EINT80 (MTK_PIN_NO(79) | 2) -#define MT6589_PIN_79_GPIO79__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(79) | 3) -#define MT6589_PIN_79_GPIO79__FUNC_MD1_UTXD (MTK_PIN_NO(79) | 4) -#define MT6589_PIN_79_GPIO79__FUNC_CLKM0 (MTK_PIN_NO(79) | 5) -#define MT6589_PIN_79_GPIO79__FUNC_URTS1 (MTK_PIN_NO(79) | 6) -#define MT6589_PIN_79_GPIO79__FUNC_MD1_EINT1 (MTK_PIN_NO(79) | 7) - -#define MT6589_PIN_80_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT6589_PIN_80_GPIO80__FUNC_URTS1 (MTK_PIN_NO(80) | 1) -#define MT6589_PIN_80_GPIO80__FUNC_EINT81 (MTK_PIN_NO(80) | 2) -#define MT6589_PIN_80_GPIO80__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(80) | 3) -#define MT6589_PIN_80_GPIO80__FUNC_MD1_URXD (MTK_PIN_NO(80) | 4) -#define MT6589_PIN_80_GPIO80__FUNC_CLKM1 (MTK_PIN_NO(80) | 5) -#define MT6589_PIN_80_GPIO80__FUNC_UCTS1 (MTK_PIN_NO(80) | 6) -#define MT6589_PIN_80_GPIO80__FUNC_MD1_EINT2 (MTK_PIN_NO(80) | 7) - -#define MT6589_PIN_81_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT6589_PIN_81_GPIO81__FUNC_URXD4 (MTK_PIN_NO(81) | 1) -#define MT6589_PIN_81_GPIO81__FUNC_EINT89 (MTK_PIN_NO(81) | 2) -#define MT6589_PIN_81_GPIO81__FUNC_URXD1 (MTK_PIN_NO(81) | 3) -#define MT6589_PIN_81_GPIO81__FUNC_MD1_URXD (MTK_PIN_NO(81) | 4) -#define MT6589_PIN_81_GPIO81__FUNC_MD2_URXD (MTK_PIN_NO(81) | 5) -#define MT6589_PIN_81_GPIO81__FUNC_UTXD4 (MTK_PIN_NO(81) | 6) -#define MT6589_PIN_81_GPIO81__FUNC_MD2_EINT5 (MTK_PIN_NO(81) | 7) - -#define MT6589_PIN_82_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT6589_PIN_82_GPIO82__FUNC_UTXD4 (MTK_PIN_NO(82) | 1) -#define MT6589_PIN_82_GPIO82__FUNC_EINT88 (MTK_PIN_NO(82) | 2) -#define MT6589_PIN_82_GPIO82__FUNC_UTXD1 (MTK_PIN_NO(82) | 3) -#define MT6589_PIN_82_GPIO82__FUNC_MD1_UTXD (MTK_PIN_NO(82) | 4) -#define MT6589_PIN_82_GPIO82__FUNC_MD2_UTXD (MTK_PIN_NO(82) | 5) -#define MT6589_PIN_82_GPIO82__FUNC_URXD4 (MTK_PIN_NO(82) | 6) -#define MT6589_PIN_82_GPIO82__FUNC_MD1_EINT5 (MTK_PIN_NO(82) | 7) - -#define MT6589_PIN_83_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT6589_PIN_83_GPIO83__FUNC_DUAL_BPI1_BUS0 (MTK_PIN_NO(83) | 1) -#define MT6589_PIN_83_GPIO83__FUNC_EINT1 (MTK_PIN_NO(83) | 2) -#define MT6589_PIN_83_GPIO83__FUNC_BPI2_BUS0 (MTK_PIN_NO(83) | 3) -#define MT6589_PIN_83_GPIO83__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(83) | 5) -#define MT6589_PIN_83_GPIO83__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(83) | 7) - -#define MT6589_PIN_84_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT6589_PIN_84_GPIO84__FUNC_DUAL_BPI1_BUS1 (MTK_PIN_NO(84) | 1) -#define MT6589_PIN_84_GPIO84__FUNC_EINT2 (MTK_PIN_NO(84) | 2) -#define MT6589_PIN_84_GPIO84__FUNC_BPI2_BUS1 (MTK_PIN_NO(84) | 3) -#define MT6589_PIN_84_GPIO84__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(84) | 5) -#define MT6589_PIN_84_GPIO84__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(84) | 7) - -#define MT6589_PIN_85_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT6589_PIN_85_GPIO85__FUNC_DUAL_BPI1_BUS2 (MTK_PIN_NO(85) | 1) -#define MT6589_PIN_85_GPIO85__FUNC_EINT3 (MTK_PIN_NO(85) | 2) -#define MT6589_PIN_85_GPIO85__FUNC_BPI2_BUS2 (MTK_PIN_NO(85) | 3) -#define MT6589_PIN_85_GPIO85__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(85) | 5) -#define MT6589_PIN_85_GPIO85__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(85) | 7) - -#define MT6589_PIN_86_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT6589_PIN_86_GPIO86__FUNC_DUAL_BPI1_BUS3 (MTK_PIN_NO(86) | 1) -#define MT6589_PIN_86_GPIO86__FUNC_EINT4 (MTK_PIN_NO(86) | 2) -#define MT6589_PIN_86_GPIO86__FUNC_BPI2_BUS3 (MTK_PIN_NO(86) | 3) -#define MT6589_PIN_86_GPIO86__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(86) | 5) -#define MT6589_PIN_86_GPIO86__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(86) | 7) - -#define MT6589_PIN_87_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT6589_PIN_87_GPIO87__FUNC_DUAL_BPI1_BUS4 (MTK_PIN_NO(87) | 1) -#define MT6589_PIN_87_GPIO87__FUNC_EINT5 (MTK_PIN_NO(87) | 2) -#define MT6589_PIN_87_GPIO87__FUNC_BPI2_BUS4 (MTK_PIN_NO(87) | 3) -#define MT6589_PIN_87_GPIO87__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(87) | 5) -#define MT6589_PIN_87_GPIO87__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(87) | 7) - -#define MT6589_PIN_88_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT6589_PIN_88_GPIO88__FUNC_DUAL_BPI1_BUS5 (MTK_PIN_NO(88) | 1) -#define MT6589_PIN_88_GPIO88__FUNC_EINT6 (MTK_PIN_NO(88) | 2) -#define MT6589_PIN_88_GPIO88__FUNC_BPI2_BUS5 (MTK_PIN_NO(88) | 3) -#define MT6589_PIN_88_GPIO88__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(88) | 5) -#define MT6589_PIN_88_GPIO88__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(88) | 7) - -#define MT6589_PIN_89_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT6589_PIN_89_GPIO89__FUNC_DUAL_BPI1_BUS6 (MTK_PIN_NO(89) | 1) -#define MT6589_PIN_89_GPIO89__FUNC_EINT7 (MTK_PIN_NO(89) | 2) -#define MT6589_PIN_89_GPIO89__FUNC_BPI2_BUS6 (MTK_PIN_NO(89) | 3) -#define MT6589_PIN_89_GPIO89__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(89) | 5) -#define MT6589_PIN_89_GPIO89__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(89) | 7) - -#define MT6589_PIN_90_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT6589_PIN_90_GPIO90__FUNC_DUAL_BPI1_BUS7 (MTK_PIN_NO(90) | 1) -#define MT6589_PIN_90_GPIO90__FUNC_EINT8 (MTK_PIN_NO(90) | 2) -#define MT6589_PIN_90_GPIO90__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(90) | 3) -#define MT6589_PIN_90_GPIO90__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(90) | 4) -#define MT6589_PIN_90_GPIO90__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(90) | 5) -#define MT6589_PIN_90_GPIO90__FUNC_USB_DRVVBUS (MTK_PIN_NO(90) | 6) -#define MT6589_PIN_90_GPIO90__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(90) | 7) - -#define MT6589_PIN_91_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT6589_PIN_91_GPIO91__FUNC_DUAL_BPI1_BUS8 (MTK_PIN_NO(91) | 1) -#define MT6589_PIN_91_GPIO91__FUNC_EINT9 (MTK_PIN_NO(91) | 2) -#define MT6589_PIN_91_GPIO91__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(91) | 3) -#define MT6589_PIN_91_GPIO91__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(91) | 5) -#define MT6589_PIN_91_GPIO91__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(91) | 7) - -#define MT6589_PIN_92_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT6589_PIN_92_GPIO92__FUNC_DUAL_BPI1_BUS9 (MTK_PIN_NO(92) | 1) -#define MT6589_PIN_92_GPIO92__FUNC_EINT10 (MTK_PIN_NO(92) | 2) -#define MT6589_PIN_92_GPIO92__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(92) | 3) -#define MT6589_PIN_92_GPIO92__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(92) | 5) -#define MT6589_PIN_92_GPIO92__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(92) | 7) - -#define MT6589_PIN_93_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT6589_PIN_93_GPIO93__FUNC_DUAL_BPI1_BUS10 (MTK_PIN_NO(93) | 1) -#define MT6589_PIN_93_GPIO93__FUNC_EINT11 (MTK_PIN_NO(93) | 2) -#define MT6589_PIN_93_GPIO93__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(93) | 5) -#define MT6589_PIN_93_GPIO93__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(93) | 7) - -#define MT6589_PIN_94_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT6589_PIN_94_GPIO94__FUNC_DUAL_BPI1_BUS11 (MTK_PIN_NO(94) | 1) -#define MT6589_PIN_94_GPIO94__FUNC_BPI2_BUS11 (MTK_PIN_NO(94) | 3) -#define MT6589_PIN_94_GPIO94__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(94) | 5) -#define MT6589_PIN_94_GPIO94__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(94) | 7) - -#define MT6589_PIN_95_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT6589_PIN_95_GPIO95__FUNC_DUAL_BPI1_BUS12 (MTK_PIN_NO(95) | 1) -#define MT6589_PIN_95_GPIO95__FUNC_BPI2_BUS12 (MTK_PIN_NO(95) | 3) -#define MT6589_PIN_95_GPIO95__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(95) | 5) -#define MT6589_PIN_95_GPIO95__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(95) | 7) - -#define MT6589_PIN_96_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT6589_PIN_96_GPIO96__FUNC_DUAL_BPI1_BUS13 (MTK_PIN_NO(96) | 1) -#define MT6589_PIN_96_GPIO96__FUNC_BPI2_BUS13 (MTK_PIN_NO(96) | 3) -#define MT6589_PIN_96_GPIO96__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(96) | 5) -#define MT6589_PIN_96_GPIO96__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(96) | 7) - -#define MT6589_PIN_97_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT6589_PIN_97_GPIO97__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(97) | 1) -#define MT6589_PIN_97_GPIO97__FUNC_BPI2_BUS16 (MTK_PIN_NO(97) | 3) -#define MT6589_PIN_97_GPIO97__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(97) | 5) -#define MT6589_PIN_97_GPIO97__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(97) | 7) - -#define MT6589_PIN_98_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT6589_PIN_98_GPIO98__FUNC_DUAL_BPI1_BUS17 (MTK_PIN_NO(98) | 1) -#define MT6589_PIN_98_GPIO98__FUNC_EINT16 (MTK_PIN_NO(98) | 2) -#define MT6589_PIN_98_GPIO98__FUNC_BPI2_BUS17 (MTK_PIN_NO(98) | 3) -#define MT6589_PIN_98_GPIO98__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(98) | 5) -#define MT6589_PIN_98_GPIO98__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(98) | 7) - -#define MT6589_PIN_99_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT6589_PIN_99_GPIO99__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(99) | 1) -#define MT6589_PIN_99_GPIO99__FUNC_EINT17 (MTK_PIN_NO(99) | 2) -#define MT6589_PIN_99_GPIO99__FUNC_BPI2_BUS18 (MTK_PIN_NO(99) | 3) -#define MT6589_PIN_99_GPIO99__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(99) | 5) -#define MT6589_PIN_99_GPIO99__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(99) | 7) - -#define MT6589_PIN_100_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT6589_PIN_100_GPIO100__FUNC_VM1 (MTK_PIN_NO(100) | 1) -#define MT6589_PIN_100_GPIO100__FUNC_EINT19 (MTK_PIN_NO(100) | 2) -#define MT6589_PIN_100_GPIO100__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(100) | 5) -#define MT6589_PIN_100_GPIO100__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(100) | 7) - -#define MT6589_PIN_101_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT6589_PIN_101_GPIO101__FUNC_VM0 (MTK_PIN_NO(101) | 1) -#define MT6589_PIN_101_GPIO101__FUNC_EINT18 (MTK_PIN_NO(101) | 2) -#define MT6589_PIN_101_GPIO101__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(101) | 5) -#define MT6589_PIN_101_GPIO101__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(101) | 7) - -#define MT6589_PIN_102_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT6589_PIN_102_GPIO102__FUNC_BSI1B_CS0 (MTK_PIN_NO(102) | 1) -#define MT6589_PIN_102_GPIO102__FUNC_EINT26 (MTK_PIN_NO(102) | 2) -#define MT6589_PIN_102_GPIO102__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(102) | 5) -#define MT6589_PIN_102_GPIO102__FUNC_MD_ABB_AFUNC_D_21 (MTK_PIN_NO(102) | 6) - -#define MT6589_PIN_103_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT6589_PIN_103_GPIO103__FUNC_BSI1B_DATA0 (MTK_PIN_NO(103) | 1) -#define MT6589_PIN_103_GPIO103__FUNC_EINT27 (MTK_PIN_NO(103) | 2) -#define MT6589_PIN_103_GPIO103__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(103) | 5) -#define MT6589_PIN_103_GPIO103__FUNC_MD_ABB_AFUNC_D_22 (MTK_PIN_NO(103) | 6) - -#define MT6589_PIN_104_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT6589_PIN_104_GPIO104__FUNC_BSI1B_CLK (MTK_PIN_NO(104) | 1) -#define MT6589_PIN_104_GPIO104__FUNC_EINT25 (MTK_PIN_NO(104) | 2) -#define MT6589_PIN_104_GPIO104__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(104) | 5) -#define MT6589_PIN_104_GPIO104__FUNC_MD_ABB_AFUNC_D_23 (MTK_PIN_NO(104) | 6) - -#define MT6589_PIN_105_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT6589_PIN_105_GPIO105__FUNC_TXBPI1 (MTK_PIN_NO(105) | 1) -#define MT6589_PIN_105_GPIO105__FUNC_EINT30 (MTK_PIN_NO(105) | 2) - -#define MT6589_PIN_106_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT6589_PIN_106_GPIO106__FUNC_EXT_CLK_EN (MTK_PIN_NO(106) | 1) - -#define MT6589_PIN_107_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT6589_PIN_107_GPIO107__FUNC_SRCLKENA2 (MTK_PIN_NO(107) | 1) -#define MT6589_PIN_107_GPIO107__FUNC_EINT39 (MTK_PIN_NO(107) | 2) - -#define MT6589_PIN_108_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT6589_PIN_108_GPIO108__FUNC_BSI1A_CS0 (MTK_PIN_NO(108) | 1) -#define MT6589_PIN_108_GPIO108__FUNC_EINT21 (MTK_PIN_NO(108) | 2) -#define MT6589_PIN_108_GPIO108__FUNC_BSI2_CS (MTK_PIN_NO(108) | 3) -#define MT6589_PIN_108_GPIO108__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) -#define MT6589_PIN_108_GPIO108__FUNC_MD_ABB_AFUNC_D_24 (MTK_PIN_NO(108) | 6) - -#define MT6589_PIN_109_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT6589_PIN_109_GPIO109__FUNC_BSI1A_DATA2 (MTK_PIN_NO(109) | 1) -#define MT6589_PIN_109_GPIO109__FUNC_EINT24 (MTK_PIN_NO(109) | 2) -#define MT6589_PIN_109_GPIO109__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) -#define MT6589_PIN_109_GPIO109__FUNC_MD_ABB_AFUNC_D_25 (MTK_PIN_NO(109) | 6) - -#define MT6589_PIN_110_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT6589_PIN_110_GPIO110__FUNC_BSI1A_DATA1 (MTK_PIN_NO(110) | 1) -#define MT6589_PIN_110_GPIO110__FUNC_EINT23 (MTK_PIN_NO(110) | 2) -#define MT6589_PIN_110_GPIO110__FUNC_BSI2_DATA1 (MTK_PIN_NO(110) | 3) -#define MT6589_PIN_110_GPIO110__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) -#define MT6589_PIN_110_GPIO110__FUNC_MD_ABB_AFUNC_D_26 (MTK_PIN_NO(110) | 6) - -#define MT6589_PIN_111_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT6589_PIN_111_GPIO111__FUNC_BSI1A_DATA0 (MTK_PIN_NO(111) | 1) -#define MT6589_PIN_111_GPIO111__FUNC_EINT22 (MTK_PIN_NO(111) | 2) -#define MT6589_PIN_111_GPIO111__FUNC_BSI2_DATA0 (MTK_PIN_NO(111) | 3) -#define MT6589_PIN_111_GPIO111__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) -#define MT6589_PIN_111_GPIO111__FUNC_MD_ABB_AFUNC_D_27 (MTK_PIN_NO(111) | 6) - -#define MT6589_PIN_112_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT6589_PIN_112_GPIO112__FUNC_BSI1A_CLK (MTK_PIN_NO(112) | 1) -#define MT6589_PIN_112_GPIO112__FUNC_EINT20 (MTK_PIN_NO(112) | 2) -#define MT6589_PIN_112_GPIO112__FUNC_BSI2_CLK (MTK_PIN_NO(112) | 3) -#define MT6589_PIN_112_GPIO112__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) -#define MT6589_PIN_112_GPIO112__FUNC_MD_ABB_AFUNC_D_28 (MTK_PIN_NO(112) | 6) - -#define MT6589_PIN_113_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT6589_PIN_113_GPIO113__FUNC_BSI1C_DATA (MTK_PIN_NO(113) | 1) -#define MT6589_PIN_113_GPIO113__FUNC_EINT29 (MTK_PIN_NO(113) | 2) -#define MT6589_PIN_113_GPIO113__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(113) | 3) -#define MT6589_PIN_113_GPIO113__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(113) | 4) -#define MT6589_PIN_113_GPIO113__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(113) | 5) -#define MT6589_PIN_113_GPIO113__FUNC_MD_ABB_AFUNC_D_29 (MTK_PIN_NO(113) | 6) -#define MT6589_PIN_113_GPIO113__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 7) - -#define MT6589_PIN_114_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT6589_PIN_114_GPIO114__FUNC_BSI1C_CLK (MTK_PIN_NO(114) | 1) -#define MT6589_PIN_114_GPIO114__FUNC_EINT28 (MTK_PIN_NO(114) | 2) -#define MT6589_PIN_114_GPIO114__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(114) | 5) -#define MT6589_PIN_114_GPIO114__FUNC_MD_ABB_AFUNC_D_30 (MTK_PIN_NO(114) | 6) - -#define MT6589_PIN_115_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT6589_PIN_115_GPIO115__FUNC_EINT10 (MTK_PIN_NO(115) | 1) -#define MT6589_PIN_115_GPIO115__FUNC_MD_ABB_AFUNC_D_31 (MTK_PIN_NO(115) | 6) - -#define MT6589_PIN_116_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT6589_PIN_116_GPIO116__FUNC_EINT11 (MTK_PIN_NO(116) | 1) -#define MT6589_PIN_116_GPIO116__FUNC_MD_ABB_AFUNC_D_32 (MTK_PIN_NO(116) | 6) - -#define MT6589_PIN_117_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT6589_PIN_117_GPIO117__FUNC_EINT16 (MTK_PIN_NO(117) | 1) -#define MT6589_PIN_117_GPIO117__FUNC_MD_ABB_AFUNC_D_33 (MTK_PIN_NO(117) | 6) - -#define MT6589_PIN_118_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT6589_PIN_118_GPIO118__FUNC_SDA0 (MTK_PIN_NO(118) | 1) -#define MT6589_PIN_118_GPIO118__FUNC_EINT91 (MTK_PIN_NO(118) | 2) -#define MT6589_PIN_118_GPIO118__FUNC_CLKM1 (MTK_PIN_NO(118) | 3) -#define MT6589_PIN_118_GPIO118__FUNC_PWM1 (MTK_PIN_NO(118) | 4) -#define MT6589_PIN_118_GPIO118__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(118) | 7) - -#define MT6589_PIN_119_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT6589_PIN_119_GPIO119__FUNC_SCL0 (MTK_PIN_NO(119) | 1) -#define MT6589_PIN_119_GPIO119__FUNC_EINT90 (MTK_PIN_NO(119) | 2) -#define MT6589_PIN_119_GPIO119__FUNC_CLKM0 (MTK_PIN_NO(119) | 3) -#define MT6589_PIN_119_GPIO119__FUNC_DISP_PWM (MTK_PIN_NO(119) | 4) -#define MT6589_PIN_119_GPIO119__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(119) | 7) - -#define MT6589_PIN_120_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT6589_PIN_120_GPIO120__FUNC_I2SIN_CK (MTK_PIN_NO(120) | 1) -#define MT6589_PIN_120_GPIO120__FUNC_EINT10 (MTK_PIN_NO(120) | 2) -#define MT6589_PIN_120_GPIO120__FUNC_DAC_CK (MTK_PIN_NO(120) | 3) -#define MT6589_PIN_120_GPIO120__FUNC_PCM1_CK (MTK_PIN_NO(120) | 4) -#define MT6589_PIN_120_GPIO120__FUNC_DSP1_ICK (MTK_PIN_NO(120) | 5) -#define MT6589_PIN_120_GPIO120__FUNC_MD_ABB_AFUNC_D_34 (MTK_PIN_NO(120) | 6) - -#define MT6589_PIN_121_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT6589_PIN_121_GPIO121__FUNC_I2SIN_WS (MTK_PIN_NO(121) | 1) -#define MT6589_PIN_121_GPIO121__FUNC_DAC_WS (MTK_PIN_NO(121) | 3) -#define MT6589_PIN_121_GPIO121__FUNC_PCM1_WS (MTK_PIN_NO(121) | 4) -#define MT6589_PIN_121_GPIO121__FUNC_DSP1_ID (MTK_PIN_NO(121) | 5) -#define MT6589_PIN_121_GPIO121__FUNC_MD_ABB_AFUNC_D_35 (MTK_PIN_NO(121) | 6) - -#define MT6589_PIN_122_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT6589_PIN_122_GPIO122__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 1) -#define MT6589_PIN_122_GPIO122__FUNC_EINT11 (MTK_PIN_NO(122) | 2) -#define MT6589_PIN_122_GPIO122__FUNC_PCM1_DI (MTK_PIN_NO(122) | 4) -#define MT6589_PIN_122_GPIO122__FUNC_DSP1_IMS (MTK_PIN_NO(122) | 5) -#define MT6589_PIN_122_GPIO122__FUNC_MD_ABB_AFUNC_D_36 (MTK_PIN_NO(122) | 6) - -#define MT6589_PIN_123_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT6589_PIN_123_GPIO123__FUNC_I2SOUT_DAT (MTK_PIN_NO(123) | 1) -#define MT6589_PIN_123_GPIO123__FUNC_DAC_DAT_OUT (MTK_PIN_NO(123) | 3) -#define MT6589_PIN_123_GPIO123__FUNC_PCM1_DO (MTK_PIN_NO(123) | 4) -#define MT6589_PIN_123_GPIO123__FUNC_MD2_EINT5 (MTK_PIN_NO(123) | 5) -#define MT6589_PIN_123_GPIO123__FUNC_MD_ABB_AFUNC_D_37 (MTK_PIN_NO(123) | 6) - -#define MT6589_PIN_124_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT6589_PIN_124_GPIO124__FUNC_EINT5 (MTK_PIN_NO(124) | 1) -#define MT6589_PIN_124_GPIO124__FUNC_PWM5 (MTK_PIN_NO(124) | 2) -#define MT6589_PIN_124_GPIO124__FUNC_CLKM3 (MTK_PIN_NO(124) | 3) -#define MT6589_PIN_124_GPIO124__FUNC_MD1_UTXD (MTK_PIN_NO(124) | 4) -#define MT6589_PIN_124_GPIO124__FUNC_MD2_EINT1 (MTK_PIN_NO(124) | 5) -#define MT6589_PIN_124_GPIO124__FUNC_MD_ABB_AFUNC_D_38 (MTK_PIN_NO(124) | 6) - -#define MT6589_PIN_125_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT6589_PIN_125_GPIO125__FUNC_EINT6 (MTK_PIN_NO(125) | 1) -#define MT6589_PIN_125_GPIO125__FUNC_PWM6 (MTK_PIN_NO(125) | 2) -#define MT6589_PIN_125_GPIO125__FUNC_CLKM4 (MTK_PIN_NO(125) | 3) -#define MT6589_PIN_125_GPIO125__FUNC_MD1_URXD (MTK_PIN_NO(125) | 4) -#define MT6589_PIN_125_GPIO125__FUNC_MD2_EINT2 (MTK_PIN_NO(125) | 5) -#define MT6589_PIN_125_GPIO125__FUNC_MD_ABB_AFUNC_D_39 (MTK_PIN_NO(125) | 6) - -#define MT6589_PIN_126_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT6589_PIN_126_GPIO126__FUNC_EINT7 (MTK_PIN_NO(126) | 1) -#define MT6589_PIN_126_GPIO126__FUNC_PWM7 (MTK_PIN_NO(126) | 2) -#define MT6589_PIN_126_GPIO126__FUNC_CLKM5 (MTK_PIN_NO(126) | 3) -#define MT6589_PIN_126_GPIO126__FUNC_SRCLKENAI2 (MTK_PIN_NO(126) | 4) -#define MT6589_PIN_126_GPIO126__FUNC_MD2_EINT3 (MTK_PIN_NO(126) | 5) -#define MT6589_PIN_126_GPIO126__FUNC_MD_ABB_AFUNC_D_40 (MTK_PIN_NO(126) | 6) - -#define MT6589_PIN_127_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT6589_PIN_127_GPIO127__FUNC_EINT8 (MTK_PIN_NO(127) | 1) -#define MT6589_PIN_127_GPIO127__FUNC_DISP_PWM (MTK_PIN_NO(127) | 2) -#define MT6589_PIN_127_GPIO127__FUNC_CLKM6 (MTK_PIN_NO(127) | 3) -#define MT6589_PIN_127_GPIO127__FUNC_MD2_EINT4 (MTK_PIN_NO(127) | 5) -#define MT6589_PIN_127_GPIO127__FUNC_MD_ABB_AFUNC_D_41 (MTK_PIN_NO(127) | 6) -#define MT6589_PIN_127_GPIO127__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(127) | 7) - -#define MT6589_PIN_128_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT6589_PIN_128_GPIO128__FUNC_EINT9 (MTK_PIN_NO(128) | 1) -#define MT6589_PIN_128_GPIO128__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(128) | 3) -#define MT6589_PIN_128_GPIO128__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(128) | 4) -#define MT6589_PIN_128_GPIO128__FUNC_USB_DRVVBUS (MTK_PIN_NO(128) | 5) -#define MT6589_PIN_128_GPIO128__FUNC_MD_ABB_AFUNC_D_42 (MTK_PIN_NO(128) | 6) - -#define MT6589_PIN_129_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT6589_PIN_129_GPIO129__FUNC_DISP_PWM (MTK_PIN_NO(129) | 1) -#define MT6589_PIN_129_GPIO129__FUNC_EINT77 (MTK_PIN_NO(129) | 2) -#define MT6589_PIN_129_GPIO129__FUNC_LSDI (MTK_PIN_NO(129) | 3) -#define MT6589_PIN_129_GPIO129__FUNC_PWM1 (MTK_PIN_NO(129) | 4) -#define MT6589_PIN_129_GPIO129__FUNC_PWM2 (MTK_PIN_NO(129) | 5) -#define MT6589_PIN_129_GPIO129__FUNC_MD_ABB_AFUNC_D_43 (MTK_PIN_NO(129) | 6) -#define MT6589_PIN_129_GPIO129__FUNC_PWM3 (MTK_PIN_NO(129) | 7) - -#define MT6589_PIN_130_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT6589_PIN_130_GPIO130__FUNC_MSDC4_DAT0 (MTK_PIN_NO(130) | 1) -#define MT6589_PIN_130_GPIO130__FUNC_EINT133 (MTK_PIN_NO(130) | 2) -#define MT6589_PIN_130_GPIO130__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(130) | 4) -#define MT6589_PIN_130_GPIO130__FUNC_USB_DRVVBUS (MTK_PIN_NO(130) | 5) -#define MT6589_PIN_130_GPIO130__FUNC_MD_ABB_AFUNC_D_46 (MTK_PIN_NO(130) | 6) -#define MT6589_PIN_130_GPIO130__FUNC_LPTE (MTK_PIN_NO(130) | 7) - -#define MT6589_PIN_131_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT6589_PIN_131_GPIO131__FUNC_MSDC4_DAT1 (MTK_PIN_NO(131) | 1) -#define MT6589_PIN_131_GPIO131__FUNC_EINT134 (MTK_PIN_NO(131) | 2) -#define MT6589_PIN_131_GPIO131__FUNC_MD_ABB_AFUNC_D_47 (MTK_PIN_NO(131) | 6) -#define MT6589_PIN_131_GPIO131__FUNC_LRSTB_1X (MTK_PIN_NO(131) | 7) - -#define MT6589_PIN_132_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT6589_PIN_132_GPIO132__FUNC_LPCE1B (MTK_PIN_NO(132) | 1) -#define MT6589_PIN_132_GPIO132__FUNC_EINT127 (MTK_PIN_NO(132) | 2) -#define MT6589_PIN_132_GPIO132__FUNC_DPI1_HSYNC_2X (MTK_PIN_NO(132) | 3) -#define MT6589_PIN_132_GPIO132__FUNC_PWM2 (MTK_PIN_NO(132) | 5) -#define MT6589_PIN_132_GPIO132__FUNC_MD_ABB_AFUNC_D_44 (MTK_PIN_NO(132) | 6) - -#define MT6589_PIN_133_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT6589_PIN_133_GPIO133__FUNC_LPCE0B (MTK_PIN_NO(133) | 1) -#define MT6589_PIN_133_GPIO133__FUNC_EINT126 (MTK_PIN_NO(133) | 2) -#define MT6589_PIN_133_GPIO133__FUNC_DPI1_VSYNC_2X (MTK_PIN_NO(133) | 3) -#define MT6589_PIN_133_GPIO133__FUNC_PWM1 (MTK_PIN_NO(133) | 5) -#define MT6589_PIN_133_GPIO133__FUNC_MD_ABB_AFUNC_D_45 (MTK_PIN_NO(133) | 6) - -#define MT6589_PIN_134_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT6589_PIN_134_GPIO134__FUNC_MSDC4_DAT5 (MTK_PIN_NO(134) | 1) -#define MT6589_PIN_134_GPIO134__FUNC_EINT136 (MTK_PIN_NO(134) | 2) -#define MT6589_PIN_134_GPIO134__FUNC_I2SIN_WS (MTK_PIN_NO(134) | 3) -#define MT6589_PIN_134_GPIO134__FUNC_DAC_WS (MTK_PIN_NO(134) | 4) -#define MT6589_PIN_134_GPIO134__FUNC_PCM1_WS (MTK_PIN_NO(134) | 5) -#define MT6589_PIN_134_GPIO134__FUNC_MD_ABB_AFUNC_D_48 (MTK_PIN_NO(134) | 6) -#define MT6589_PIN_134_GPIO134__FUNC_SPI1_CSN (MTK_PIN_NO(134) | 7) - -#define MT6589_PIN_135_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT6589_PIN_135_GPIO135__FUNC_MSDC4_DAT6 (MTK_PIN_NO(135) | 1) -#define MT6589_PIN_135_GPIO135__FUNC_EINT137 (MTK_PIN_NO(135) | 2) -#define MT6589_PIN_135_GPIO135__FUNC_I2SOUT_DAT (MTK_PIN_NO(135) | 3) -#define MT6589_PIN_135_GPIO135__FUNC_DAC_DAT_OUT (MTK_PIN_NO(135) | 4) -#define MT6589_PIN_135_GPIO135__FUNC_PCM1_DO (MTK_PIN_NO(135) | 5) -#define MT6589_PIN_135_GPIO135__FUNC_MD_ABB_AFUNC_D_49 (MTK_PIN_NO(135) | 6) -#define MT6589_PIN_135_GPIO135__FUNC_SPI1_MO (MTK_PIN_NO(135) | 7) - -#define MT6589_PIN_136_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT6589_PIN_136_GPIO136__FUNC_MSDC4_DAT7 (MTK_PIN_NO(136) | 1) -#define MT6589_PIN_136_GPIO136__FUNC_EINT138 (MTK_PIN_NO(136) | 2) -#define MT6589_PIN_136_GPIO136__FUNC_I2SIN_DAT (MTK_PIN_NO(136) | 3) -#define MT6589_PIN_136_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 5) -#define MT6589_PIN_136_GPIO136__FUNC_MD_ABB_AFUNC_D_50 (MTK_PIN_NO(136) | 6) -#define MT6589_PIN_136_GPIO136__FUNC_SPI1_MI (MTK_PIN_NO(136) | 7) - -#define MT6589_PIN_137_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT6589_PIN_137_GPIO137__FUNC_MSDC4_DAT4 (MTK_PIN_NO(137) | 1) -#define MT6589_PIN_137_GPIO137__FUNC_EINT135 (MTK_PIN_NO(137) | 2) -#define MT6589_PIN_137_GPIO137__FUNC_I2SIN_CK (MTK_PIN_NO(137) | 3) -#define MT6589_PIN_137_GPIO137__FUNC_DAC_CK (MTK_PIN_NO(137) | 4) -#define MT6589_PIN_137_GPIO137__FUNC_PCM1_CK (MTK_PIN_NO(137) | 5) -#define MT6589_PIN_137_GPIO137__FUNC_MD_ABB_AFUNC_D_51 (MTK_PIN_NO(137) | 6) -#define MT6589_PIN_137_GPIO137__FUNC_SPI1_CLK (MTK_PIN_NO(137) | 7) - -#define MT6589_PIN_138_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT6589_PIN_138_GPIO138__FUNC_MSDC4_DAT2 (MTK_PIN_NO(138) | 1) -#define MT6589_PIN_138_GPIO138__FUNC_EINT131 (MTK_PIN_NO(138) | 2) -#define MT6589_PIN_138_GPIO138__FUNC_I2SIN_WS (MTK_PIN_NO(138) | 3) -#define MT6589_PIN_138_GPIO138__FUNC_CM2PDN_2X (MTK_PIN_NO(138) | 4) -#define MT6589_PIN_138_GPIO138__FUNC_DAC_WS (MTK_PIN_NO(138) | 5) -#define MT6589_PIN_138_GPIO138__FUNC_PCM1_WS (MTK_PIN_NO(138) | 6) -#define MT6589_PIN_138_GPIO138__FUNC_LSCE0B_1X (MTK_PIN_NO(138) | 7) - -#define MT6589_PIN_139_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT6589_PIN_139_GPIO139__FUNC_MSDC4_CLK (MTK_PIN_NO(139) | 1) -#define MT6589_PIN_139_GPIO139__FUNC_EINT129 (MTK_PIN_NO(139) | 2) -#define MT6589_PIN_139_GPIO139__FUNC_DPI1_CK_2X (MTK_PIN_NO(139) | 3) -#define MT6589_PIN_139_GPIO139__FUNC_CM2PCLK_2X (MTK_PIN_NO(139) | 4) -#define MT6589_PIN_139_GPIO139__FUNC_PWM4 (MTK_PIN_NO(139) | 5) -#define MT6589_PIN_139_GPIO139__FUNC_PCM1_DI (MTK_PIN_NO(139) | 6) -#define MT6589_PIN_139_GPIO139__FUNC_LSCK_1X (MTK_PIN_NO(139) | 7) - -#define MT6589_PIN_140_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT6589_PIN_140_GPIO140__FUNC_MSDC4_DAT3 (MTK_PIN_NO(140) | 1) -#define MT6589_PIN_140_GPIO140__FUNC_EINT132 (MTK_PIN_NO(140) | 2) -#define MT6589_PIN_140_GPIO140__FUNC_I2SOUT_DAT (MTK_PIN_NO(140) | 3) -#define MT6589_PIN_140_GPIO140__FUNC_CM2RST_2X (MTK_PIN_NO(140) | 4) -#define MT6589_PIN_140_GPIO140__FUNC_DAC_DAT_OUT (MTK_PIN_NO(140) | 5) -#define MT6589_PIN_140_GPIO140__FUNC_PCM1_DO (MTK_PIN_NO(140) | 6) -#define MT6589_PIN_140_GPIO140__FUNC_LSCE1B_1X (MTK_PIN_NO(140) | 7) - -#define MT6589_PIN_141_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT6589_PIN_141_GPIO141__FUNC_MSDC4_CMD (MTK_PIN_NO(141) | 1) -#define MT6589_PIN_141_GPIO141__FUNC_EINT128 (MTK_PIN_NO(141) | 2) -#define MT6589_PIN_141_GPIO141__FUNC_DPI1_DE_2X (MTK_PIN_NO(141) | 3) -#define MT6589_PIN_141_GPIO141__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(141) | 4) -#define MT6589_PIN_141_GPIO141__FUNC_PWM3 (MTK_PIN_NO(141) | 5) -#define MT6589_PIN_141_GPIO141__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(141) | 6) -#define MT6589_PIN_141_GPIO141__FUNC_LSDA_1X (MTK_PIN_NO(141) | 7) - -#define MT6589_PIN_142_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT6589_PIN_142_GPIO142__FUNC_MSDC4_RSTB (MTK_PIN_NO(142) | 1) -#define MT6589_PIN_142_GPIO142__FUNC_EINT130 (MTK_PIN_NO(142) | 2) -#define MT6589_PIN_142_GPIO142__FUNC_I2SIN_CK (MTK_PIN_NO(142) | 3) -#define MT6589_PIN_142_GPIO142__FUNC_CM2MCLK_2X (MTK_PIN_NO(142) | 4) -#define MT6589_PIN_142_GPIO142__FUNC_DAC_CK (MTK_PIN_NO(142) | 5) -#define MT6589_PIN_142_GPIO142__FUNC_PCM1_CK (MTK_PIN_NO(142) | 6) -#define MT6589_PIN_142_GPIO142__FUNC_LSA0_1X (MTK_PIN_NO(142) | 7) - -#define MT6589_PIN_143_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT6589_PIN_143_GPIO143__FUNC_DPI0_VSYNC (MTK_PIN_NO(143) | 1) -#define MT6589_PIN_143_GPIO143__FUNC_EINT98 (MTK_PIN_NO(143) | 2) -#define MT6589_PIN_143_GPIO143__FUNC_I2SIN_CK (MTK_PIN_NO(143) | 3) -#define MT6589_PIN_143_GPIO143__FUNC_DAC_CK (MTK_PIN_NO(143) | 4) -#define MT6589_PIN_143_GPIO143__FUNC_PCM1_CK (MTK_PIN_NO(143) | 5) -#define MT6589_PIN_143_GPIO143__FUNC_MD_ABB_AFUNC_D_52 (MTK_PIN_NO(143) | 6) -#define MT6589_PIN_143_GPIO143__FUNC_TESTB_OUT8 (MTK_PIN_NO(143) | 7) - -#define MT6589_PIN_144_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT6589_PIN_144_GPIO144__FUNC_DPI0_HSYNC (MTK_PIN_NO(144) | 1) -#define MT6589_PIN_144_GPIO144__FUNC_EINT99 (MTK_PIN_NO(144) | 2) -#define MT6589_PIN_144_GPIO144__FUNC_I2SIN_WS (MTK_PIN_NO(144) | 3) -#define MT6589_PIN_144_GPIO144__FUNC_DAC_WS (MTK_PIN_NO(144) | 4) -#define MT6589_PIN_144_GPIO144__FUNC_PCM1_WS (MTK_PIN_NO(144) | 5) -#define MT6589_PIN_144_GPIO144__FUNC_IRDA_RXD (MTK_PIN_NO(144) | 6) -#define MT6589_PIN_144_GPIO144__FUNC_TESTB_OUT9 (MTK_PIN_NO(144) | 7) - -#define MT6589_PIN_145_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) -#define MT6589_PIN_145_GPIO145__FUNC_DPI0_DE (MTK_PIN_NO(145) | 1) -#define MT6589_PIN_145_GPIO145__FUNC_EINT100 (MTK_PIN_NO(145) | 2) -#define MT6589_PIN_145_GPIO145__FUNC_I2SOUT_DAT (MTK_PIN_NO(145) | 3) -#define MT6589_PIN_145_GPIO145__FUNC_DAC_DAT_OUT (MTK_PIN_NO(145) | 4) -#define MT6589_PIN_145_GPIO145__FUNC_PCM1_DO (MTK_PIN_NO(145) | 5) -#define MT6589_PIN_145_GPIO145__FUNC_IRDA_TXD (MTK_PIN_NO(145) | 6) -#define MT6589_PIN_145_GPIO145__FUNC_TESTB_OUT10 (MTK_PIN_NO(145) | 7) - -#define MT6589_PIN_146_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) -#define MT6589_PIN_146_GPIO146__FUNC_DPI0_CK (MTK_PIN_NO(146) | 1) -#define MT6589_PIN_146_GPIO146__FUNC_EINT101 (MTK_PIN_NO(146) | 2) -#define MT6589_PIN_146_GPIO146__FUNC_I2SIN_DAT (MTK_PIN_NO(146) | 3) -#define MT6589_PIN_146_GPIO146__FUNC_PCM1_DI (MTK_PIN_NO(146) | 5) -#define MT6589_PIN_146_GPIO146__FUNC_IRDA_PDN (MTK_PIN_NO(146) | 6) -#define MT6589_PIN_146_GPIO146__FUNC_TESTB_OUT11 (MTK_PIN_NO(146) | 7) - -#define MT6589_PIN_147_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) -#define MT6589_PIN_147_GPIO147__FUNC_DPI0_B0 (MTK_PIN_NO(147) | 1) -#define MT6589_PIN_147_GPIO147__FUNC_EINT102 (MTK_PIN_NO(147) | 2) -#define MT6589_PIN_147_GPIO147__FUNC_SCL0 (MTK_PIN_NO(147) | 4) -#define MT6589_PIN_147_GPIO147__FUNC_DISP_PWM (MTK_PIN_NO(147) | 5) -#define MT6589_PIN_147_GPIO147__FUNC_MD_ABB_AFUNC_D_57 (MTK_PIN_NO(147) | 6) -#define MT6589_PIN_147_GPIO147__FUNC_TESTB_OUT12 (MTK_PIN_NO(147) | 7) - -#define MT6589_PIN_148_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) -#define MT6589_PIN_148_GPIO148__FUNC_DPI0_B1 (MTK_PIN_NO(148) | 1) -#define MT6589_PIN_148_GPIO148__FUNC_EINT103 (MTK_PIN_NO(148) | 2) -#define MT6589_PIN_148_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 3) -#define MT6589_PIN_148_GPIO148__FUNC_SDA0 (MTK_PIN_NO(148) | 4) -#define MT6589_PIN_148_GPIO148__FUNC_PWM1 (MTK_PIN_NO(148) | 5) -#define MT6589_PIN_148_GPIO148__FUNC_MD_ABB_AFUNC_D_58 (MTK_PIN_NO(148) | 6) -#define MT6589_PIN_148_GPIO148__FUNC_TESTB_OUT13 (MTK_PIN_NO(148) | 7) - -#define MT6589_PIN_149_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) -#define MT6589_PIN_149_GPIO149__FUNC_DPI0_B2 (MTK_PIN_NO(149) | 1) -#define MT6589_PIN_149_GPIO149__FUNC_EINT104 (MTK_PIN_NO(149) | 2) -#define MT6589_PIN_149_GPIO149__FUNC_CLKM1 (MTK_PIN_NO(149) | 3) -#define MT6589_PIN_149_GPIO149__FUNC_SCL1 (MTK_PIN_NO(149) | 4) -#define MT6589_PIN_149_GPIO149__FUNC_PWM2 (MTK_PIN_NO(149) | 5) -#define MT6589_PIN_149_GPIO149__FUNC_MD_ABB_AFUNC_D_59 (MTK_PIN_NO(149) | 6) -#define MT6589_PIN_149_GPIO149__FUNC_TESTB_OUT14 (MTK_PIN_NO(149) | 7) - -#define MT6589_PIN_150_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) -#define MT6589_PIN_150_GPIO150__FUNC_DPI0_B3 (MTK_PIN_NO(150) | 1) -#define MT6589_PIN_150_GPIO150__FUNC_EINT105 (MTK_PIN_NO(150) | 2) -#define MT6589_PIN_150_GPIO150__FUNC_CLKM2 (MTK_PIN_NO(150) | 3) -#define MT6589_PIN_150_GPIO150__FUNC_SDA1 (MTK_PIN_NO(150) | 4) -#define MT6589_PIN_150_GPIO150__FUNC_PWM3 (MTK_PIN_NO(150) | 5) -#define MT6589_PIN_150_GPIO150__FUNC_MD_ABB_AFUNC_D_60 (MTK_PIN_NO(150) | 6) -#define MT6589_PIN_150_GPIO150__FUNC_TESTB_OUT15 (MTK_PIN_NO(150) | 7) - -#define MT6589_PIN_151_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) -#define MT6589_PIN_151_GPIO151__FUNC_DPI0_B4 (MTK_PIN_NO(151) | 1) -#define MT6589_PIN_151_GPIO151__FUNC_EINT106 (MTK_PIN_NO(151) | 2) -#define MT6589_PIN_151_GPIO151__FUNC_CLKM3 (MTK_PIN_NO(151) | 3) -#define MT6589_PIN_151_GPIO151__FUNC_SCL2 (MTK_PIN_NO(151) | 4) -#define MT6589_PIN_151_GPIO151__FUNC_PWM4 (MTK_PIN_NO(151) | 5) -#define MT6589_PIN_151_GPIO151__FUNC_MD_ABB_AFUNC_D_61 (MTK_PIN_NO(151) | 6) -#define MT6589_PIN_151_GPIO151__FUNC_TESTB_OUT16 (MTK_PIN_NO(151) | 7) - -#define MT6589_PIN_152_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) -#define MT6589_PIN_152_GPIO152__FUNC_DPI0_B5 (MTK_PIN_NO(152) | 1) -#define MT6589_PIN_152_GPIO152__FUNC_EINT107 (MTK_PIN_NO(152) | 2) -#define MT6589_PIN_152_GPIO152__FUNC_CLKM4 (MTK_PIN_NO(152) | 3) -#define MT6589_PIN_152_GPIO152__FUNC_SDA2 (MTK_PIN_NO(152) | 4) -#define MT6589_PIN_152_GPIO152__FUNC_PWM5 (MTK_PIN_NO(152) | 5) -#define MT6589_PIN_152_GPIO152__FUNC_MD_ABB_AFUNC_D_62 (MTK_PIN_NO(152) | 6) -#define MT6589_PIN_152_GPIO152__FUNC_TESTB_OUT17 (MTK_PIN_NO(152) | 7) - -#define MT6589_PIN_153_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) -#define MT6589_PIN_153_GPIO153__FUNC_DPI0_B6 (MTK_PIN_NO(153) | 1) -#define MT6589_PIN_153_GPIO153__FUNC_EINT108 (MTK_PIN_NO(153) | 2) -#define MT6589_PIN_153_GPIO153__FUNC_CLKM5 (MTK_PIN_NO(153) | 3) -#define MT6589_PIN_153_GPIO153__FUNC_SCL3 (MTK_PIN_NO(153) | 4) -#define MT6589_PIN_153_GPIO153__FUNC_PWM6 (MTK_PIN_NO(153) | 5) -#define MT6589_PIN_153_GPIO153__FUNC_MD_ABB_AFUNC_D_63 (MTK_PIN_NO(153) | 6) -#define MT6589_PIN_153_GPIO153__FUNC_TESTB_OUT18 (MTK_PIN_NO(153) | 7) - -#define MT6589_PIN_154_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) -#define MT6589_PIN_154_GPIO154__FUNC_DPI0_B7 (MTK_PIN_NO(154) | 1) -#define MT6589_PIN_154_GPIO154__FUNC_EINT109 (MTK_PIN_NO(154) | 2) -#define MT6589_PIN_154_GPIO154__FUNC_CLKM6 (MTK_PIN_NO(154) | 3) -#define MT6589_PIN_154_GPIO154__FUNC_SDA3 (MTK_PIN_NO(154) | 4) -#define MT6589_PIN_154_GPIO154__FUNC_PWM7 (MTK_PIN_NO(154) | 5) -#define MT6589_PIN_154_GPIO154__FUNC_MD1_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(154) | 6) -#define MT6589_PIN_154_GPIO154__FUNC_TESTB_OUT19 (MTK_PIN_NO(154) | 7) - -#define MT6589_PIN_155_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) -#define MT6589_PIN_155_GPIO155__FUNC_DPI0_G0 (MTK_PIN_NO(155) | 1) -#define MT6589_PIN_155_GPIO155__FUNC_EINT110 (MTK_PIN_NO(155) | 2) -#define MT6589_PIN_155_GPIO155__FUNC_DSP1_ID (MTK_PIN_NO(155) | 5) -#define MT6589_PIN_155_GPIO155__FUNC_MD1_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(155) | 6) -#define MT6589_PIN_155_GPIO155__FUNC_TESTB_OUT20 (MTK_PIN_NO(155) | 7) - -#define MT6589_PIN_156_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) -#define MT6589_PIN_156_GPIO156__FUNC_DPI0_G1 (MTK_PIN_NO(156) | 1) -#define MT6589_PIN_156_GPIO156__FUNC_EINT111 (MTK_PIN_NO(156) | 2) -#define MT6589_PIN_156_GPIO156__FUNC_DSP1_ICK (MTK_PIN_NO(156) | 5) -#define MT6589_PIN_156_GPIO156__FUNC_MD_ABB_AFUNC_D_56 (MTK_PIN_NO(156) | 6) -#define MT6589_PIN_156_GPIO156__FUNC_TESTB_OUT21 (MTK_PIN_NO(156) | 7) - -#define MT6589_PIN_157_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) -#define MT6589_PIN_157_GPIO157__FUNC_DPI0_G2 (MTK_PIN_NO(157) | 1) -#define MT6589_PIN_157_GPIO157__FUNC_EINT112 (MTK_PIN_NO(157) | 2) -#define MT6589_PIN_157_GPIO157__FUNC_DSP1_IMS (MTK_PIN_NO(157) | 5) -#define MT6589_PIN_157_GPIO157__FUNC_MD1_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(157) | 6) -#define MT6589_PIN_157_GPIO157__FUNC_TESTB_OUT22 (MTK_PIN_NO(157) | 7) - -#define MT6589_PIN_158_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) -#define MT6589_PIN_158_GPIO158__FUNC_DPI0_G3 (MTK_PIN_NO(158) | 1) -#define MT6589_PIN_158_GPIO158__FUNC_EINT113 (MTK_PIN_NO(158) | 2) -#define MT6589_PIN_158_GPIO158__FUNC_DSP2_IMS (MTK_PIN_NO(158) | 5) -#define MT6589_PIN_158_GPIO158__FUNC_MD1_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(158) | 6) -#define MT6589_PIN_158_GPIO158__FUNC_TESTB_OUT23 (MTK_PIN_NO(158) | 7) - -#define MT6589_PIN_159_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) -#define MT6589_PIN_159_GPIO159__FUNC_DPI0_G4 (MTK_PIN_NO(159) | 1) -#define MT6589_PIN_159_GPIO159__FUNC_EINT114 (MTK_PIN_NO(159) | 2) -#define MT6589_PIN_159_GPIO159__FUNC_DPI1_D_2X_0 (MTK_PIN_NO(159) | 3) -#define MT6589_PIN_159_GPIO159__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(159) | 4) -#define MT6589_PIN_159_GPIO159__FUNC_DSP2_ID (MTK_PIN_NO(159) | 5) -#define MT6589_PIN_159_GPIO159__FUNC_MD_ABB_AFUNC_D_53 (MTK_PIN_NO(159) | 6) -#define MT6589_PIN_159_GPIO159__FUNC_TESTB_OUT24 (MTK_PIN_NO(159) | 7) - -#define MT6589_PIN_160_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) -#define MT6589_PIN_160_GPIO160__FUNC_DPI0_G5 (MTK_PIN_NO(160) | 1) -#define MT6589_PIN_160_GPIO160__FUNC_EINT115 (MTK_PIN_NO(160) | 2) -#define MT6589_PIN_160_GPIO160__FUNC_DPI1_D_2X_1 (MTK_PIN_NO(160) | 3) -#define MT6589_PIN_160_GPIO160__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(160) | 4) -#define MT6589_PIN_160_GPIO160__FUNC_DSP2_ICK (MTK_PIN_NO(160) | 5) -#define MT6589_PIN_160_GPIO160__FUNC_MD_ABB_AFUNC_D_54 (MTK_PIN_NO(160) | 6) -#define MT6589_PIN_160_GPIO160__FUNC_TESTB_OUT25 (MTK_PIN_NO(160) | 7) - -#define MT6589_PIN_161_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) -#define MT6589_PIN_161_GPIO161__FUNC_DPI0_G6 (MTK_PIN_NO(161) | 1) -#define MT6589_PIN_161_GPIO161__FUNC_EINT116 (MTK_PIN_NO(161) | 2) -#define MT6589_PIN_161_GPIO161__FUNC_DPI1_D_2X_2 (MTK_PIN_NO(161) | 3) -#define MT6589_PIN_161_GPIO161__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(161) | 4) -#define MT6589_PIN_161_GPIO161__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(161) | 5) -#define MT6589_PIN_161_GPIO161__FUNC_MD1_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(161) | 6) -#define MT6589_PIN_161_GPIO161__FUNC_TESTB_OUT26 (MTK_PIN_NO(161) | 7) - -#define MT6589_PIN_162_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) -#define MT6589_PIN_162_GPIO162__FUNC_DPI0_G7 (MTK_PIN_NO(162) | 1) -#define MT6589_PIN_162_GPIO162__FUNC_EINT117 (MTK_PIN_NO(162) | 2) -#define MT6589_PIN_162_GPIO162__FUNC_DPI1_D_2X_3 (MTK_PIN_NO(162) | 3) -#define MT6589_PIN_162_GPIO162__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(162) | 4) -#define MT6589_PIN_162_GPIO162__FUNC_MD2_TCK_PAD (MTK_PIN_NO(162) | 5) -#define MT6589_PIN_162_GPIO162__FUNC_MD1_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(162) | 6) -#define MT6589_PIN_162_GPIO162__FUNC_TESTB_OUT27 (MTK_PIN_NO(162) | 7) - -#define MT6589_PIN_163_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) -#define MT6589_PIN_163_GPIO163__FUNC_DPI0_R0 (MTK_PIN_NO(163) | 1) -#define MT6589_PIN_163_GPIO163__FUNC_EINT118 (MTK_PIN_NO(163) | 2) -#define MT6589_PIN_163_GPIO163__FUNC_DPI1_D_2X_4 (MTK_PIN_NO(163) | 3) -#define MT6589_PIN_163_GPIO163__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(163) | 4) -#define MT6589_PIN_163_GPIO163__FUNC_MD2_TDI_PAD (MTK_PIN_NO(163) | 5) -#define MT6589_PIN_163_GPIO163__FUNC_MD1_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(163) | 6) -#define MT6589_PIN_163_GPIO163__FUNC_TESTB_OUT28 (MTK_PIN_NO(163) | 7) - -#define MT6589_PIN_164_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) -#define MT6589_PIN_164_GPIO164__FUNC_DPI0_R1 (MTK_PIN_NO(164) | 1) -#define MT6589_PIN_164_GPIO164__FUNC_EINT119 (MTK_PIN_NO(164) | 2) -#define MT6589_PIN_164_GPIO164__FUNC_DPI1_D_2X_5 (MTK_PIN_NO(164) | 3) -#define MT6589_PIN_164_GPIO164__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(164) | 4) -#define MT6589_PIN_164_GPIO164__FUNC_MD2_TDO_PAD (MTK_PIN_NO(164) | 5) -#define MT6589_PIN_164_GPIO164__FUNC_MD1_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(164) | 6) -#define MT6589_PIN_164_GPIO164__FUNC_TESTB_OUT29 (MTK_PIN_NO(164) | 7) - -#define MT6589_PIN_165_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) -#define MT6589_PIN_165_GPIO165__FUNC_DPI0_R2 (MTK_PIN_NO(165) | 1) -#define MT6589_PIN_165_GPIO165__FUNC_EINT120 (MTK_PIN_NO(165) | 2) -#define MT6589_PIN_165_GPIO165__FUNC_DPI1_D_2X_6 (MTK_PIN_NO(165) | 3) -#define MT6589_PIN_165_GPIO165__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(165) | 4) -#define MT6589_PIN_165_GPIO165__FUNC_MD2_TMS_PAD (MTK_PIN_NO(165) | 5) -#define MT6589_PIN_165_GPIO165__FUNC_TESTB_OUT30 (MTK_PIN_NO(165) | 7) - -#define MT6589_PIN_166_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) -#define MT6589_PIN_166_GPIO166__FUNC_DPI0_R3 (MTK_PIN_NO(166) | 1) -#define MT6589_PIN_166_GPIO166__FUNC_EINT121 (MTK_PIN_NO(166) | 2) -#define MT6589_PIN_166_GPIO166__FUNC_DPI1_D_2X_7 (MTK_PIN_NO(166) | 3) -#define MT6589_PIN_166_GPIO166__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(166) | 4) -#define MT6589_PIN_166_GPIO166__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(166) | 5) -#define MT6589_PIN_166_GPIO166__FUNC_MD_ABB_AFUNC_D_55 (MTK_PIN_NO(166) | 6) -#define MT6589_PIN_166_GPIO166__FUNC_TESTB_OUT31 (MTK_PIN_NO(166) | 7) - -#define MT6589_PIN_167_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) -#define MT6589_PIN_167_GPIO167__FUNC_DPI0_R4 (MTK_PIN_NO(167) | 1) -#define MT6589_PIN_167_GPIO167__FUNC_EINT122 (MTK_PIN_NO(167) | 2) -#define MT6589_PIN_167_GPIO167__FUNC_DPI1_D_2X_8 (MTK_PIN_NO(167) | 3) -#define MT6589_PIN_167_GPIO167__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(167) | 4) -#define MT6589_PIN_167_GPIO167__FUNC_TESTA_OUT0 (MTK_PIN_NO(167) | 7) - -#define MT6589_PIN_168_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) -#define MT6589_PIN_168_GPIO168__FUNC_DPI0_R5 (MTK_PIN_NO(168) | 1) -#define MT6589_PIN_168_GPIO168__FUNC_EINT123 (MTK_PIN_NO(168) | 2) -#define MT6589_PIN_168_GPIO168__FUNC_DPI1_D_2X_9 (MTK_PIN_NO(168) | 3) -#define MT6589_PIN_168_GPIO168__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(168) | 4) -#define MT6589_PIN_168_GPIO168__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(168) | 5) -#define MT6589_PIN_168_GPIO168__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(168) | 6) -#define MT6589_PIN_168_GPIO168__FUNC_TESTA_OUT1 (MTK_PIN_NO(168) | 7) - -#define MT6589_PIN_169_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) -#define MT6589_PIN_169_GPIO169__FUNC_DPI0_R6 (MTK_PIN_NO(169) | 1) -#define MT6589_PIN_169_GPIO169__FUNC_EINT124 (MTK_PIN_NO(169) | 2) -#define MT6589_PIN_169_GPIO169__FUNC_DPI1_D_2X_10 (MTK_PIN_NO(169) | 3) -#define MT6589_PIN_169_GPIO169__FUNC_CM2VSYNC_2X (MTK_PIN_NO(169) | 4) -#define MT6589_PIN_169_GPIO169__FUNC_TESTA_OUT2 (MTK_PIN_NO(169) | 7) - -#define MT6589_PIN_170_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) -#define MT6589_PIN_170_GPIO170__FUNC_DPI0_R7 (MTK_PIN_NO(170) | 1) -#define MT6589_PIN_170_GPIO170__FUNC_EINT125 (MTK_PIN_NO(170) | 2) -#define MT6589_PIN_170_GPIO170__FUNC_DPI1_D_2X_11 (MTK_PIN_NO(170) | 3) -#define MT6589_PIN_170_GPIO170__FUNC_CM2HSYNC_2X (MTK_PIN_NO(170) | 4) -#define MT6589_PIN_170_GPIO170__FUNC_TESTA_OUT3 (MTK_PIN_NO(170) | 7) - -#define MT6589_PIN_171_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) -#define MT6589_PIN_171_GPIO171__FUNC_MSDC1_INSI (MTK_PIN_NO(171) | 1) -#define MT6589_PIN_171_GPIO171__FUNC_EINT57 (MTK_PIN_NO(171) | 2) -#define MT6589_PIN_171_GPIO171__FUNC_SCL5 (MTK_PIN_NO(171) | 3) -#define MT6589_PIN_171_GPIO171__FUNC_PWM6 (MTK_PIN_NO(171) | 4) -#define MT6589_PIN_171_GPIO171__FUNC_CLKM5 (MTK_PIN_NO(171) | 5) -#define MT6589_PIN_171_GPIO171__FUNC_MD2_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(171) | 6) -#define MT6589_PIN_171_GPIO171__FUNC_TESTB_OUT6 (MTK_PIN_NO(171) | 7) - -#define MT6589_PIN_172_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) -#define MT6589_PIN_172_GPIO172__FUNC_MSDC2_INSI (MTK_PIN_NO(172) | 1) -#define MT6589_PIN_172_GPIO172__FUNC_EINT65 (MTK_PIN_NO(172) | 2) -#define MT6589_PIN_172_GPIO172__FUNC_BPI2_BUS6 (MTK_PIN_NO(172) | 3) -#define MT6589_PIN_172_GPIO172__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(172) | 7) - -#define MT6589_PIN_173_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) -#define MT6589_PIN_173_GPIO173__FUNC_MSDC2_SDWPI (MTK_PIN_NO(173) | 1) -#define MT6589_PIN_173_GPIO173__FUNC_EINT66 (MTK_PIN_NO(173) | 2) -#define MT6589_PIN_173_GPIO173__FUNC_BPI2_BUS17 (MTK_PIN_NO(173) | 3) -#define MT6589_PIN_173_GPIO173__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(173) | 4) -#define MT6589_PIN_173_GPIO173__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(173) | 5) -#define MT6589_PIN_173_GPIO173__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(173) | 7) - -#define MT6589_PIN_174_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) -#define MT6589_PIN_174_GPIO174__FUNC_MSDC2_DAT2 (MTK_PIN_NO(174) | 1) -#define MT6589_PIN_174_GPIO174__FUNC_EINT63 (MTK_PIN_NO(174) | 2) -#define MT6589_PIN_174_GPIO174__FUNC_BPI2_BUS4 (MTK_PIN_NO(174) | 3) -#define MT6589_PIN_174_GPIO174__FUNC_DSP2_IMS (MTK_PIN_NO(174) | 4) -#define MT6589_PIN_174_GPIO174__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(174) | 7) - -#define MT6589_PIN_175_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) -#define MT6589_PIN_175_GPIO175__FUNC_MSDC2_DAT3 (MTK_PIN_NO(175) | 1) -#define MT6589_PIN_175_GPIO175__FUNC_EINT64 (MTK_PIN_NO(175) | 2) -#define MT6589_PIN_175_GPIO175__FUNC_BPI2_BUS5 (MTK_PIN_NO(175) | 3) -#define MT6589_PIN_175_GPIO175__FUNC_DSP2_ID (MTK_PIN_NO(175) | 4) -#define MT6589_PIN_175_GPIO175__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(175) | 7) - -#define MT6589_PIN_176_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) -#define MT6589_PIN_176_GPIO176__FUNC_MSDC2_CMD (MTK_PIN_NO(176) | 1) -#define MT6589_PIN_176_GPIO176__FUNC_EINT60 (MTK_PIN_NO(176) | 2) -#define MT6589_PIN_176_GPIO176__FUNC_BPI2_BUS1 (MTK_PIN_NO(176) | 3) -#define MT6589_PIN_176_GPIO176__FUNC_DSP1_IMS (MTK_PIN_NO(176) | 4) -#define MT6589_PIN_176_GPIO176__FUNC_PCM1_WS (MTK_PIN_NO(176) | 5) -#define MT6589_PIN_176_GPIO176__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(176) | 7) - -#define MT6589_PIN_177_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) -#define MT6589_PIN_177_GPIO177__FUNC_MSDC2_CLK (MTK_PIN_NO(177) | 1) -#define MT6589_PIN_177_GPIO177__FUNC_EINT59 (MTK_PIN_NO(177) | 2) -#define MT6589_PIN_177_GPIO177__FUNC_BPI2_BUS0 (MTK_PIN_NO(177) | 3) -#define MT6589_PIN_177_GPIO177__FUNC_DSP1_ICK (MTK_PIN_NO(177) | 4) -#define MT6589_PIN_177_GPIO177__FUNC_PCM1_CK (MTK_PIN_NO(177) | 5) -#define MT6589_PIN_177_GPIO177__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(177) | 7) - -#define MT6589_PIN_178_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) -#define MT6589_PIN_178_GPIO178__FUNC_MSDC2_DAT1 (MTK_PIN_NO(178) | 1) -#define MT6589_PIN_178_GPIO178__FUNC_EINT62 (MTK_PIN_NO(178) | 2) -#define MT6589_PIN_178_GPIO178__FUNC_BPI2_BUS3 (MTK_PIN_NO(178) | 3) -#define MT6589_PIN_178_GPIO178__FUNC_DSP2_ICK (MTK_PIN_NO(178) | 4) -#define MT6589_PIN_178_GPIO178__FUNC_PCM1_DO (MTK_PIN_NO(178) | 5) -#define MT6589_PIN_178_GPIO178__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(178) | 7) - -#define MT6589_PIN_179_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) -#define MT6589_PIN_179_GPIO179__FUNC_MSDC2_DAT0 (MTK_PIN_NO(179) | 1) -#define MT6589_PIN_179_GPIO179__FUNC_EINT61 (MTK_PIN_NO(179) | 2) -#define MT6589_PIN_179_GPIO179__FUNC_BPI2_BUS2 (MTK_PIN_NO(179) | 3) -#define MT6589_PIN_179_GPIO179__FUNC_DSP1_ID (MTK_PIN_NO(179) | 4) -#define MT6589_PIN_179_GPIO179__FUNC_PCM1_DI (MTK_PIN_NO(179) | 5) -#define MT6589_PIN_179_GPIO179__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(179) | 7) - -#define MT6589_PIN_180_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) -#define MT6589_PIN_180_GPIO180__FUNC_MSDC1_DAT0 (MTK_PIN_NO(180) | 1) -#define MT6589_PIN_180_GPIO180__FUNC_EINT53 (MTK_PIN_NO(180) | 2) -#define MT6589_PIN_180_GPIO180__FUNC_SCL1 (MTK_PIN_NO(180) | 3) -#define MT6589_PIN_180_GPIO180__FUNC_PWM2 (MTK_PIN_NO(180) | 4) -#define MT6589_PIN_180_GPIO180__FUNC_CLKM1 (MTK_PIN_NO(180) | 5) -#define MT6589_PIN_180_GPIO180__FUNC_MD2_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(180) | 6) -#define MT6589_PIN_180_GPIO180__FUNC_TESTB_OUT2 (MTK_PIN_NO(180) | 7) - -#define MT6589_PIN_181_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) -#define MT6589_PIN_181_GPIO181__FUNC_MSDC1_DAT1 (MTK_PIN_NO(181) | 1) -#define MT6589_PIN_181_GPIO181__FUNC_EINT54 (MTK_PIN_NO(181) | 2) -#define MT6589_PIN_181_GPIO181__FUNC_SDA1 (MTK_PIN_NO(181) | 3) -#define MT6589_PIN_181_GPIO181__FUNC_PWM3 (MTK_PIN_NO(181) | 4) -#define MT6589_PIN_181_GPIO181__FUNC_CLKM2 (MTK_PIN_NO(181) | 5) -#define MT6589_PIN_181_GPIO181__FUNC_MD2_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(181) | 6) -#define MT6589_PIN_181_GPIO181__FUNC_TESTB_OUT3 (MTK_PIN_NO(181) | 7) - -#define MT6589_PIN_182_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) -#define MT6589_PIN_182_GPIO182__FUNC_MSDC1_SDWPI (MTK_PIN_NO(182) | 1) -#define MT6589_PIN_182_GPIO182__FUNC_EINT58 (MTK_PIN_NO(182) | 2) -#define MT6589_PIN_182_GPIO182__FUNC_SDA5 (MTK_PIN_NO(182) | 3) -#define MT6589_PIN_182_GPIO182__FUNC_PWM7 (MTK_PIN_NO(182) | 4) -#define MT6589_PIN_182_GPIO182__FUNC_CLKM6 (MTK_PIN_NO(182) | 5) -#define MT6589_PIN_182_GPIO182__FUNC_MD2_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(182) | 6) -#define MT6589_PIN_182_GPIO182__FUNC_TESTB_OUT7 (MTK_PIN_NO(182) | 7) - -#define MT6589_PIN_183_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) -#define MT6589_PIN_183_GPIO183__FUNC_MSDC1_CMD (MTK_PIN_NO(183) | 1) -#define MT6589_PIN_183_GPIO183__FUNC_EINT52 (MTK_PIN_NO(183) | 2) -#define MT6589_PIN_183_GPIO183__FUNC_SDA0 (MTK_PIN_NO(183) | 3) -#define MT6589_PIN_183_GPIO183__FUNC_PWM1 (MTK_PIN_NO(183) | 4) -#define MT6589_PIN_183_GPIO183__FUNC_CLKM0 (MTK_PIN_NO(183) | 5) -#define MT6589_PIN_183_GPIO183__FUNC_MD2_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(183) | 6) -#define MT6589_PIN_183_GPIO183__FUNC_TESTB_OUT1 (MTK_PIN_NO(183) | 7) - -#define MT6589_PIN_184_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) -#define MT6589_PIN_184_GPIO184__FUNC_MSDC1_CLK (MTK_PIN_NO(184) | 1) -#define MT6589_PIN_184_GPIO184__FUNC_EINT51 (MTK_PIN_NO(184) | 2) -#define MT6589_PIN_184_GPIO184__FUNC_SCL0 (MTK_PIN_NO(184) | 3) -#define MT6589_PIN_184_GPIO184__FUNC_DISP_PWM (MTK_PIN_NO(184) | 4) -#define MT6589_PIN_184_GPIO184__FUNC_MD2_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(184) | 6) -#define MT6589_PIN_184_GPIO184__FUNC_TESTB_OUT0 (MTK_PIN_NO(184) | 7) - -#define MT6589_PIN_185_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) -#define MT6589_PIN_185_GPIO185__FUNC_MSDC1_DAT2 (MTK_PIN_NO(185) | 1) -#define MT6589_PIN_185_GPIO185__FUNC_EINT55 (MTK_PIN_NO(185) | 2) -#define MT6589_PIN_185_GPIO185__FUNC_SCL4 (MTK_PIN_NO(185) | 3) -#define MT6589_PIN_185_GPIO185__FUNC_PWM4 (MTK_PIN_NO(185) | 4) -#define MT6589_PIN_185_GPIO185__FUNC_CLKM3 (MTK_PIN_NO(185) | 5) -#define MT6589_PIN_185_GPIO185__FUNC_MD2_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(185) | 6) -#define MT6589_PIN_185_GPIO185__FUNC_TESTB_OUT4 (MTK_PIN_NO(185) | 7) - -#define MT6589_PIN_186_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) -#define MT6589_PIN_186_GPIO186__FUNC_MSDC1_DAT3 (MTK_PIN_NO(186) | 1) -#define MT6589_PIN_186_GPIO186__FUNC_EINT56 (MTK_PIN_NO(186) | 2) -#define MT6589_PIN_186_GPIO186__FUNC_SDA4 (MTK_PIN_NO(186) | 3) -#define MT6589_PIN_186_GPIO186__FUNC_PWM5 (MTK_PIN_NO(186) | 4) -#define MT6589_PIN_186_GPIO186__FUNC_CLKM4 (MTK_PIN_NO(186) | 5) -#define MT6589_PIN_186_GPIO186__FUNC_MD2_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(186) | 6) -#define MT6589_PIN_186_GPIO186__FUNC_TESTB_OUT5 (MTK_PIN_NO(186) | 7) - -#define MT6589_PIN_187_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) -#define MT6589_PIN_187_GPIO187__FUNC_EINT36 (MTK_PIN_NO(187) | 2) - -#define MT6589_PIN_188_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) -#define MT6589_PIN_188_GPIO188__FUNC_EINT35 (MTK_PIN_NO(188) | 2) - -#define MT6589_PIN_189_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) -#define MT6589_PIN_189_GPIO189__FUNC_EINT169 (MTK_PIN_NO(189) | 2) - -#define MT6589_PIN_190_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) -#define MT6589_PIN_190_GPIO190__FUNC_EINT168 (MTK_PIN_NO(190) | 2) - -#define MT6589_PIN_191_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) -#define MT6589_PIN_191_GPIO191__FUNC_EINT163 (MTK_PIN_NO(191) | 2) - -#define MT6589_PIN_192_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) -#define MT6589_PIN_192_GPIO192__FUNC_EINT162 (MTK_PIN_NO(192) | 2) - -#define MT6589_PIN_193_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) -#define MT6589_PIN_193_GPIO193__FUNC_EINT167 (MTK_PIN_NO(193) | 2) - -#define MT6589_PIN_194_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) -#define MT6589_PIN_194_GPIO194__FUNC_EINT166 (MTK_PIN_NO(194) | 2) - -#define MT6589_PIN_195_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) -#define MT6589_PIN_195_GPIO195__FUNC_EINT165 (MTK_PIN_NO(195) | 2) - -#define MT6589_PIN_196_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) -#define MT6589_PIN_196_GPIO196__FUNC_EINT164 (MTK_PIN_NO(196) | 2) - -#define MT6589_PIN_197_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) -#define MT6589_PIN_197_GPIO197__FUNC_CMDAT6 (MTK_PIN_NO(197) | 1) -#define MT6589_PIN_197_GPIO197__FUNC_EINT175 (MTK_PIN_NO(197) | 2) - -#define MT6589_PIN_198_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) -#define MT6589_PIN_198_GPIO198__FUNC_CMDAT7 (MTK_PIN_NO(198) | 1) -#define MT6589_PIN_198_GPIO198__FUNC_EINT174 (MTK_PIN_NO(198) | 2) - -#define MT6589_PIN_199_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) -#define MT6589_PIN_199_GPIO199__FUNC_CMDAT8 (MTK_PIN_NO(199) | 1) -#define MT6589_PIN_199_GPIO199__FUNC_EINT171 (MTK_PIN_NO(199) | 2) - -#define MT6589_PIN_200_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) -#define MT6589_PIN_200_GPIO200__FUNC_CMDAT9 (MTK_PIN_NO(200) | 1) -#define MT6589_PIN_200_GPIO200__FUNC_EINT170 (MTK_PIN_NO(200) | 2) - -#define MT6589_PIN_201_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) -#define MT6589_PIN_201_GPIO201__FUNC_CMHSYNC (MTK_PIN_NO(201) | 1) -#define MT6589_PIN_201_GPIO201__FUNC_EINT173 (MTK_PIN_NO(201) | 2) - -#define MT6589_PIN_202_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) -#define MT6589_PIN_202_GPIO202__FUNC_CMVSYNC (MTK_PIN_NO(202) | 1) -#define MT6589_PIN_202_GPIO202__FUNC_EINT172 (MTK_PIN_NO(202) | 2) - -#define MT6589_PIN_203_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) -#define MT6589_PIN_203_GPIO203__FUNC_CMDAT2 (MTK_PIN_NO(203) | 1) -#define MT6589_PIN_203_GPIO203__FUNC_EINT181 (MTK_PIN_NO(203) | 2) -#define MT6589_PIN_203_GPIO203__FUNC_CMCSD2 (MTK_PIN_NO(203) | 3) - -#define MT6589_PIN_204_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) -#define MT6589_PIN_204_GPIO204__FUNC_CMDAT3 (MTK_PIN_NO(204) | 1) -#define MT6589_PIN_204_GPIO204__FUNC_EINT180 (MTK_PIN_NO(204) | 2) -#define MT6589_PIN_204_GPIO204__FUNC_CMCSD3 (MTK_PIN_NO(204) | 3) - -#define MT6589_PIN_205_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) -#define MT6589_PIN_205_GPIO205__FUNC_CMDAT4 (MTK_PIN_NO(205) | 1) -#define MT6589_PIN_205_GPIO205__FUNC_EINT177 (MTK_PIN_NO(205) | 2) - -#define MT6589_PIN_206_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) -#define MT6589_PIN_206_GPIO206__FUNC_CMDAT5 (MTK_PIN_NO(206) | 1) -#define MT6589_PIN_206_GPIO206__FUNC_EINT176 (MTK_PIN_NO(206) | 2) - -#define MT6589_PIN_207_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) -#define MT6589_PIN_207_GPIO207__FUNC_CMDAT0 (MTK_PIN_NO(207) | 1) -#define MT6589_PIN_207_GPIO207__FUNC_EINT179 (MTK_PIN_NO(207) | 2) -#define MT6589_PIN_207_GPIO207__FUNC_CMCSD0 (MTK_PIN_NO(207) | 3) - -#define MT6589_PIN_208_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) -#define MT6589_PIN_208_GPIO208__FUNC_CMDAT1 (MTK_PIN_NO(208) | 1) -#define MT6589_PIN_208_GPIO208__FUNC_EINT178 (MTK_PIN_NO(208) | 2) -#define MT6589_PIN_208_GPIO208__FUNC_CMCSD1 (MTK_PIN_NO(208) | 3) - -#define MT6589_PIN_209_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) -#define MT6589_PIN_209_GPIO209__FUNC_CMPCLK (MTK_PIN_NO(209) | 1) -#define MT6589_PIN_209_GPIO209__FUNC_EINT182 (MTK_PIN_NO(209) | 2) -#define MT6589_PIN_209_GPIO209__FUNC_CMCSK (MTK_PIN_NO(209) | 3) -#define MT6589_PIN_209_GPIO209__FUNC_CM2MCLK_4X (MTK_PIN_NO(209) | 4) -#define MT6589_PIN_209_GPIO209__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(209) | 5) -#define MT6589_PIN_209_GPIO209__FUNC_TESTA_OUT27 (MTK_PIN_NO(209) | 7) - -#define MT6589_PIN_210_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) -#define MT6589_PIN_210_GPIO210__FUNC_CMMCLK (MTK_PIN_NO(210) | 1) -#define MT6589_PIN_210_GPIO210__FUNC_EINT183 (MTK_PIN_NO(210) | 2) -#define MT6589_PIN_210_GPIO210__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(210) | 5) -#define MT6589_PIN_210_GPIO210__FUNC_TESTA_OUT28 (MTK_PIN_NO(210) | 7) - -#define MT6589_PIN_211_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) -#define MT6589_PIN_211_GPIO211__FUNC_CMRST (MTK_PIN_NO(211) | 1) -#define MT6589_PIN_211_GPIO211__FUNC_EINT185 (MTK_PIN_NO(211) | 2) -#define MT6589_PIN_211_GPIO211__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(211) | 5) -#define MT6589_PIN_211_GPIO211__FUNC_TESTA_OUT30 (MTK_PIN_NO(211) | 7) - -#define MT6589_PIN_212_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) -#define MT6589_PIN_212_GPIO212__FUNC_CMPDN (MTK_PIN_NO(212) | 1) -#define MT6589_PIN_212_GPIO212__FUNC_EINT184 (MTK_PIN_NO(212) | 2) -#define MT6589_PIN_212_GPIO212__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(212) | 5) -#define MT6589_PIN_212_GPIO212__FUNC_TESTA_OUT29 (MTK_PIN_NO(212) | 7) - -#define MT6589_PIN_213_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) -#define MT6589_PIN_213_GPIO213__FUNC_CMFLASH (MTK_PIN_NO(213) | 1) -#define MT6589_PIN_213_GPIO213__FUNC_EINT186 (MTK_PIN_NO(213) | 2) -#define MT6589_PIN_213_GPIO213__FUNC_CM2MCLK_3X (MTK_PIN_NO(213) | 3) -#define MT6589_PIN_213_GPIO213__FUNC_TESTA_OUT31 (MTK_PIN_NO(213) | 7) - -#define MT6589_PIN_214_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) -#define MT6589_PIN_214_GPIO214__FUNC_SDA1 (MTK_PIN_NO(214) | 1) -#define MT6589_PIN_214_GPIO214__FUNC_EINT93 (MTK_PIN_NO(214) | 2) -#define MT6589_PIN_214_GPIO214__FUNC_CLKM3 (MTK_PIN_NO(214) | 3) -#define MT6589_PIN_214_GPIO214__FUNC_PWM3 (MTK_PIN_NO(214) | 4) -#define MT6589_PIN_214_GPIO214__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(214) | 5) -#define MT6589_PIN_214_GPIO214__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(214) | 7) - -#define MT6589_PIN_215_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) -#define MT6589_PIN_215_GPIO215__FUNC_SCL1 (MTK_PIN_NO(215) | 1) -#define MT6589_PIN_215_GPIO215__FUNC_EINT92 (MTK_PIN_NO(215) | 2) -#define MT6589_PIN_215_GPIO215__FUNC_CLKM2 (MTK_PIN_NO(215) | 3) -#define MT6589_PIN_215_GPIO215__FUNC_PWM2 (MTK_PIN_NO(215) | 4) -#define MT6589_PIN_215_GPIO215__FUNC_TS_AUX_DIN (MTK_PIN_NO(215) | 5) -#define MT6589_PIN_215_GPIO215__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(215) | 7) - -#define MT6589_PIN_216_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) -#define MT6589_PIN_216_GPIO216__FUNC_SDA2 (MTK_PIN_NO(216) | 1) -#define MT6589_PIN_216_GPIO216__FUNC_EINT95 (MTK_PIN_NO(216) | 2) -#define MT6589_PIN_216_GPIO216__FUNC_CLKM5 (MTK_PIN_NO(216) | 3) -#define MT6589_PIN_216_GPIO216__FUNC_PWM5 (MTK_PIN_NO(216) | 4) -#define MT6589_PIN_216_GPIO216__FUNC_TS_AUX_PWDB (MTK_PIN_NO(216) | 5) -#define MT6589_PIN_216_GPIO216__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(216) | 7) - -#define MT6589_PIN_217_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) -#define MT6589_PIN_217_GPIO217__FUNC_SCL2 (MTK_PIN_NO(217) | 1) -#define MT6589_PIN_217_GPIO217__FUNC_EINT94 (MTK_PIN_NO(217) | 2) -#define MT6589_PIN_217_GPIO217__FUNC_CLKM4 (MTK_PIN_NO(217) | 3) -#define MT6589_PIN_217_GPIO217__FUNC_PWM4 (MTK_PIN_NO(217) | 4) -#define MT6589_PIN_217_GPIO217__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(217) | 5) -#define MT6589_PIN_217_GPIO217__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(217) | 7) - -#define MT6589_PIN_218_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) -#define MT6589_PIN_218_GPIO218__FUNC_SRCLKENAI (MTK_PIN_NO(218) | 1) - -#define MT6589_PIN_219_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) -#define MT6589_PIN_219_GPIO219__FUNC_URXD3 (MTK_PIN_NO(219) | 1) -#define MT6589_PIN_219_GPIO219__FUNC_EINT87 (MTK_PIN_NO(219) | 2) -#define MT6589_PIN_219_GPIO219__FUNC_UTXD3 (MTK_PIN_NO(219) | 3) -#define MT6589_PIN_219_GPIO219__FUNC_MD2_URXD (MTK_PIN_NO(219) | 4) -#define MT6589_PIN_219_GPIO219__FUNC_TS_AUX_ST (MTK_PIN_NO(219) | 5) -#define MT6589_PIN_219_GPIO219__FUNC_PWM4 (MTK_PIN_NO(219) | 6) -#define MT6589_PIN_219_GPIO219__FUNC_MD2_EINT4 (MTK_PIN_NO(219) | 7) - -#define MT6589_PIN_220_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) -#define MT6589_PIN_220_GPIO220__FUNC_UTXD3 (MTK_PIN_NO(220) | 1) -#define MT6589_PIN_220_GPIO220__FUNC_EINT86 (MTK_PIN_NO(220) | 2) -#define MT6589_PIN_220_GPIO220__FUNC_URXD3 (MTK_PIN_NO(220) | 3) -#define MT6589_PIN_220_GPIO220__FUNC_MD2_UTXD (MTK_PIN_NO(220) | 4) -#define MT6589_PIN_220_GPIO220__FUNC_TS_AUX_CS_B (MTK_PIN_NO(220) | 5) -#define MT6589_PIN_220_GPIO220__FUNC_PWM3 (MTK_PIN_NO(220) | 6) -#define MT6589_PIN_220_GPIO220__FUNC_MD2_EINT3 (MTK_PIN_NO(220) | 7) - -#define MT6589_PIN_221_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) -#define MT6589_PIN_221_GPIO221__FUNC_MRG_I2S_PCM_CLK (MTK_PIN_NO(221) | 1) -#define MT6589_PIN_221_GPIO221__FUNC_I2SIN_CK (MTK_PIN_NO(221) | 3) -#define MT6589_PIN_221_GPIO221__FUNC_PCM0_CK (MTK_PIN_NO(221) | 4) -#define MT6589_PIN_221_GPIO221__FUNC_DSP2_ICK (MTK_PIN_NO(221) | 5) -#define MT6589_PIN_221_GPIO221__FUNC_IMG_TEST_CK (MTK_PIN_NO(221) | 6) -#define MT6589_PIN_221_GPIO221__FUNC_USB_SCL (MTK_PIN_NO(221) | 7) - -#define MT6589_PIN_222_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) -#define MT6589_PIN_222_GPIO222__FUNC_MRG_I2S_PCM_SYNC (MTK_PIN_NO(222) | 1) -#define MT6589_PIN_222_GPIO222__FUNC_EINT16 (MTK_PIN_NO(222) | 2) -#define MT6589_PIN_222_GPIO222__FUNC_I2SIN_WS (MTK_PIN_NO(222) | 3) -#define MT6589_PIN_222_GPIO222__FUNC_PCM0_WS (MTK_PIN_NO(222) | 4) -#define MT6589_PIN_222_GPIO222__FUNC_DISP_TEST_CK (MTK_PIN_NO(222) | 6) - -#define MT6589_PIN_223_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) -#define MT6589_PIN_223_GPIO223__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(223) | 1) -#define MT6589_PIN_223_GPIO223__FUNC_I2SIN_DAT (MTK_PIN_NO(223) | 3) -#define MT6589_PIN_223_GPIO223__FUNC_PCM0_DI (MTK_PIN_NO(223) | 4) -#define MT6589_PIN_223_GPIO223__FUNC_DSP2_ID (MTK_PIN_NO(223) | 5) -#define MT6589_PIN_223_GPIO223__FUNC_MFG_TEST_CK (MTK_PIN_NO(223) | 6) -#define MT6589_PIN_223_GPIO223__FUNC_USB_SDA (MTK_PIN_NO(223) | 7) - -#define MT6589_PIN_224_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) -#define MT6589_PIN_224_GPIO224__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(224) | 1) -#define MT6589_PIN_224_GPIO224__FUNC_EINT17 (MTK_PIN_NO(224) | 2) -#define MT6589_PIN_224_GPIO224__FUNC_I2SOUT_DAT (MTK_PIN_NO(224) | 3) -#define MT6589_PIN_224_GPIO224__FUNC_PCM0_DO (MTK_PIN_NO(224) | 4) -#define MT6589_PIN_224_GPIO224__FUNC_VDEC_TEST_CK (MTK_PIN_NO(224) | 6) - -#define MT6589_PIN_225_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) -#define MT6589_PIN_225_GPIO225__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(225) | 1) -#define MT6589_PIN_225_GPIO225__FUNC_EINT18 (MTK_PIN_NO(225) | 2) -#define MT6589_PIN_225_GPIO225__FUNC_BT_SYNC (MTK_PIN_NO(225) | 3) -#define MT6589_PIN_225_GPIO225__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(225) | 4) -#define MT6589_PIN_225_GPIO225__FUNC_DSP2_IMS (MTK_PIN_NO(225) | 5) -#define MT6589_PIN_225_GPIO225__FUNC_VENC_TEST_CK (MTK_PIN_NO(225) | 6) - -#define MT6589_PIN_226_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) -#define MT6589_PIN_226_GPIO226__FUNC_MSDC3_DAT2 (MTK_PIN_NO(226) | 1) -#define MT6589_PIN_226_GPIO226__FUNC_EINT71 (MTK_PIN_NO(226) | 2) -#define MT6589_PIN_226_GPIO226__FUNC_SCL6 (MTK_PIN_NO(226) | 3) -#define MT6589_PIN_226_GPIO226__FUNC_PWM5 (MTK_PIN_NO(226) | 4) -#define MT6589_PIN_226_GPIO226__FUNC_CLKM4 (MTK_PIN_NO(226) | 5) -#define MT6589_PIN_226_GPIO226__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(226) | 7) - -#define MT6589_PIN_227_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) -#define MT6589_PIN_227_GPIO227__FUNC_MSDC3_DAT3 (MTK_PIN_NO(227) | 1) -#define MT6589_PIN_227_GPIO227__FUNC_EINT72 (MTK_PIN_NO(227) | 2) -#define MT6589_PIN_227_GPIO227__FUNC_SDA6 (MTK_PIN_NO(227) | 3) -#define MT6589_PIN_227_GPIO227__FUNC_PWM6 (MTK_PIN_NO(227) | 4) -#define MT6589_PIN_227_GPIO227__FUNC_CLKM5 (MTK_PIN_NO(227) | 5) -#define MT6589_PIN_227_GPIO227__FUNC_A_FUNC_CK (MTK_PIN_NO(227) | 7) - -#define MT6589_PIN_228_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) -#define MT6589_PIN_228_GPIO228__FUNC_MSDC3_CMD (MTK_PIN_NO(228) | 1) -#define MT6589_PIN_228_GPIO228__FUNC_EINT68 (MTK_PIN_NO(228) | 2) -#define MT6589_PIN_228_GPIO228__FUNC_SDA2 (MTK_PIN_NO(228) | 3) -#define MT6589_PIN_228_GPIO228__FUNC_PWM2 (MTK_PIN_NO(228) | 4) -#define MT6589_PIN_228_GPIO228__FUNC_CLKM1 (MTK_PIN_NO(228) | 5) -#define MT6589_PIN_228_GPIO228__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(228) | 7) - -#define MT6589_PIN_229_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) -#define MT6589_PIN_229_GPIO229__FUNC_MSDC3_CLK (MTK_PIN_NO(229) | 1) -#define MT6589_PIN_229_GPIO229__FUNC_EINT67 (MTK_PIN_NO(229) | 2) -#define MT6589_PIN_229_GPIO229__FUNC_SCL2 (MTK_PIN_NO(229) | 3) -#define MT6589_PIN_229_GPIO229__FUNC_PWM1 (MTK_PIN_NO(229) | 4) -#define MT6589_PIN_229_GPIO229__FUNC_CLKM0 (MTK_PIN_NO(229) | 5) -#define MT6589_PIN_229_GPIO229__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(229) | 7) - -#define MT6589_PIN_230_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) -#define MT6589_PIN_230_GPIO230__FUNC_MSDC3_DAT1 (MTK_PIN_NO(230) | 1) -#define MT6589_PIN_230_GPIO230__FUNC_EINT70 (MTK_PIN_NO(230) | 2) -#define MT6589_PIN_230_GPIO230__FUNC_SDA3 (MTK_PIN_NO(230) | 3) -#define MT6589_PIN_230_GPIO230__FUNC_PWM4 (MTK_PIN_NO(230) | 4) -#define MT6589_PIN_230_GPIO230__FUNC_CLKM3 (MTK_PIN_NO(230) | 5) -#define MT6589_PIN_230_GPIO230__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(230) | 7) - -#define MT6589_PIN_231_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) -#define MT6589_PIN_231_GPIO231__FUNC_MSDC3_DAT0 (MTK_PIN_NO(231) | 1) -#define MT6589_PIN_231_GPIO231__FUNC_EINT69 (MTK_PIN_NO(231) | 2) -#define MT6589_PIN_231_GPIO231__FUNC_SCL3 (MTK_PIN_NO(231) | 3) -#define MT6589_PIN_231_GPIO231__FUNC_PWM3 (MTK_PIN_NO(231) | 4) -#define MT6589_PIN_231_GPIO231__FUNC_CLKM2 (MTK_PIN_NO(231) | 5) -#define MT6589_PIN_231_GPIO231__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(231) | 7) +#define MT6589_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6589_GPIO0__FUNC_MSDC0_DAT7 (MTK_PIN_NO(0) | 1) +#define MT6589_GPIO0__FUNC_EINT49 (MTK_PIN_NO(0) | 2) +#define MT6589_GPIO0__FUNC_I2SOUT_DAT (MTK_PIN_NO(0) | 3) +#define MT6589_GPIO0__FUNC_DAC_DAT_OUT (MTK_PIN_NO(0) | 4) +#define MT6589_GPIO0__FUNC_PCM1_DO (MTK_PIN_NO(0) | 5) +#define MT6589_GPIO0__FUNC_SPI1_MO (MTK_PIN_NO(0) | 6) +#define MT6589_GPIO0__FUNC_NALE (MTK_PIN_NO(0) | 7) + +#define MT6589_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6589_GPIO1__FUNC_MSDC0_DAT6 (MTK_PIN_NO(1) | 1) +#define MT6589_GPIO1__FUNC_EINT48 (MTK_PIN_NO(1) | 2) +#define MT6589_GPIO1__FUNC_I2SIN_WS (MTK_PIN_NO(1) | 3) +#define MT6589_GPIO1__FUNC_DAC_WS (MTK_PIN_NO(1) | 4) +#define MT6589_GPIO1__FUNC_PCM1_WS (MTK_PIN_NO(1) | 5) +#define MT6589_GPIO1__FUNC_SPI1_CSN (MTK_PIN_NO(1) | 6) +#define MT6589_GPIO1__FUNC_NCLE (MTK_PIN_NO(1) | 7) + +#define MT6589_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6589_GPIO2__FUNC_MSDC0_DAT5 (MTK_PIN_NO(2) | 1) +#define MT6589_GPIO2__FUNC_EINT47 (MTK_PIN_NO(2) | 2) +#define MT6589_GPIO2__FUNC_I2SIN_CK (MTK_PIN_NO(2) | 3) +#define MT6589_GPIO2__FUNC_DAC_CK (MTK_PIN_NO(2) | 4) +#define MT6589_GPIO2__FUNC_PCM1_CK (MTK_PIN_NO(2) | 5) +#define MT6589_GPIO2__FUNC_SPI1_CLK (MTK_PIN_NO(2) | 6) +#define MT6589_GPIO2__FUNC_NLD4 (MTK_PIN_NO(2) | 7) + +#define MT6589_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6589_GPIO3__FUNC_MSDC0_DAT4 (MTK_PIN_NO(3) | 1) +#define MT6589_GPIO3__FUNC_EINT46 (MTK_PIN_NO(3) | 2) +#define MT6589_GPIO3__FUNC_LSCE1B_2X (MTK_PIN_NO(3) | 6) +#define MT6589_GPIO3__FUNC_NLD5 (MTK_PIN_NO(3) | 7) + +#define MT6589_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6589_GPIO4__FUNC_MSDC0_RSTB (MTK_PIN_NO(4) | 1) +#define MT6589_GPIO4__FUNC_EINT50 (MTK_PIN_NO(4) | 2) +#define MT6589_GPIO4__FUNC_I2SIN_DAT (MTK_PIN_NO(4) | 3) +#define MT6589_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 5) +#define MT6589_GPIO4__FUNC_SPI1_MI (MTK_PIN_NO(4) | 6) +#define MT6589_GPIO4__FUNC_NLD10 (MTK_PIN_NO(4) | 7) + +#define MT6589_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6589_GPIO5__FUNC_MSDC0_CMD (MTK_PIN_NO(5) | 1) +#define MT6589_GPIO5__FUNC_EINT41 (MTK_PIN_NO(5) | 2) +#define MT6589_GPIO5__FUNC_LRSTB_2X (MTK_PIN_NO(5) | 6) +#define MT6589_GPIO5__FUNC_NRNB (MTK_PIN_NO(5) | 7) + +#define MT6589_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6589_GPIO6__FUNC_MSDC0_CLK (MTK_PIN_NO(6) | 1) +#define MT6589_GPIO6__FUNC_EINT40 (MTK_PIN_NO(6) | 2) +#define MT6589_GPIO6__FUNC_LPTE (MTK_PIN_NO(6) | 6) +#define MT6589_GPIO6__FUNC_NREB (MTK_PIN_NO(6) | 7) + +#define MT6589_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6589_GPIO7__FUNC_MSDC0_DAT3 (MTK_PIN_NO(7) | 1) +#define MT6589_GPIO7__FUNC_EINT45 (MTK_PIN_NO(7) | 2) +#define MT6589_GPIO7__FUNC_LSCE0B_2X (MTK_PIN_NO(7) | 6) +#define MT6589_GPIO7__FUNC_NLD7 (MTK_PIN_NO(7) | 7) + +#define MT6589_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6589_GPIO8__FUNC_MSDC0_DAT2 (MTK_PIN_NO(8) | 1) +#define MT6589_GPIO8__FUNC_EINT44 (MTK_PIN_NO(8) | 2) +#define MT6589_GPIO8__FUNC_LSA0_2X (MTK_PIN_NO(8) | 6) +#define MT6589_GPIO8__FUNC_NLD14 (MTK_PIN_NO(8) | 7) + +#define MT6589_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6589_GPIO9__FUNC_MSDC0_DAT1 (MTK_PIN_NO(9) | 1) +#define MT6589_GPIO9__FUNC_EINT43 (MTK_PIN_NO(9) | 2) +#define MT6589_GPIO9__FUNC_LSCK_2X (MTK_PIN_NO(9) | 6) +#define MT6589_GPIO9__FUNC_NLD11 (MTK_PIN_NO(9) | 7) + +#define MT6589_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6589_GPIO10__FUNC_MSDC0_DAT0 (MTK_PIN_NO(10) | 1) +#define MT6589_GPIO10__FUNC_EINT42 (MTK_PIN_NO(10) | 2) +#define MT6589_GPIO10__FUNC_LSDA_2X (MTK_PIN_NO(10) | 6) + +#define MT6589_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6589_GPIO11__FUNC_NCEB0 (MTK_PIN_NO(11) | 1) +#define MT6589_GPIO11__FUNC_EINT139 (MTK_PIN_NO(11) | 2) +#define MT6589_GPIO11__FUNC_TESTA_OUT4 (MTK_PIN_NO(11) | 7) + +#define MT6589_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6589_GPIO12__FUNC_NCEB1 (MTK_PIN_NO(12) | 1) +#define MT6589_GPIO12__FUNC_EINT140 (MTK_PIN_NO(12) | 2) +#define MT6589_GPIO12__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(12) | 4) +#define MT6589_GPIO12__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(12) | 5) +#define MT6589_GPIO12__FUNC_USB_DRVVBUS (MTK_PIN_NO(12) | 6) +#define MT6589_GPIO12__FUNC_TESTA_OUT5 (MTK_PIN_NO(12) | 7) + +#define MT6589_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6589_GPIO13__FUNC_NRNB (MTK_PIN_NO(13) | 1) +#define MT6589_GPIO13__FUNC_EINT141 (MTK_PIN_NO(13) | 2) +#define MT6589_GPIO13__FUNC_MD_ABB_AFUNC_D_0 (MTK_PIN_NO(13) | 6) +#define MT6589_GPIO13__FUNC_TESTA_OUT6 (MTK_PIN_NO(13) | 7) + +#define MT6589_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6589_GPIO14__FUNC_NCLE (MTK_PIN_NO(14) | 1) +#define MT6589_GPIO14__FUNC_EINT142 (MTK_PIN_NO(14) | 2) +#define MT6589_GPIO14__FUNC_DPI1_CK_1X (MTK_PIN_NO(14) | 3) +#define MT6589_GPIO14__FUNC_CM2PDN_1X (MTK_PIN_NO(14) | 4) +#define MT6589_GPIO14__FUNC_NALE (MTK_PIN_NO(14) | 6) +#define MT6589_GPIO14__FUNC_TESTA_OUT7 (MTK_PIN_NO(14) | 7) + +#define MT6589_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6589_GPIO15__FUNC_NALE (MTK_PIN_NO(15) | 1) +#define MT6589_GPIO15__FUNC_EINT143 (MTK_PIN_NO(15) | 2) +#define MT6589_GPIO15__FUNC_DPI1_DE_1X (MTK_PIN_NO(15) | 3) +#define MT6589_GPIO15__FUNC_CM2MCLK_1X (MTK_PIN_NO(15) | 4) +#define MT6589_GPIO15__FUNC_IRDA_RXD (MTK_PIN_NO(15) | 5) +#define MT6589_GPIO15__FUNC_NCLE (MTK_PIN_NO(15) | 6) +#define MT6589_GPIO15__FUNC_TESTA_OUT8 (MTK_PIN_NO(15) | 7) + +#define MT6589_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6589_GPIO16__FUNC_NREB (MTK_PIN_NO(16) | 1) +#define MT6589_GPIO16__FUNC_EINT144 (MTK_PIN_NO(16) | 2) +#define MT6589_GPIO16__FUNC_DPI1_HSYNC_1X (MTK_PIN_NO(16) | 3) +#define MT6589_GPIO16__FUNC_CM2RST_1X (MTK_PIN_NO(16) | 4) +#define MT6589_GPIO16__FUNC_IRDA_TXD (MTK_PIN_NO(16) | 5) +#define MT6589_GPIO16__FUNC_MD_ABB_AFUNC_D_1 (MTK_PIN_NO(16) | 6) +#define MT6589_GPIO16__FUNC_TESTA_OUT9 (MTK_PIN_NO(16) | 7) + +#define MT6589_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6589_GPIO17__FUNC_NWEB (MTK_PIN_NO(17) | 1) +#define MT6589_GPIO17__FUNC_EINT145 (MTK_PIN_NO(17) | 2) +#define MT6589_GPIO17__FUNC_DPI1_VSYNC_1X (MTK_PIN_NO(17) | 3) +#define MT6589_GPIO17__FUNC_CM2PCLK_1X (MTK_PIN_NO(17) | 4) +#define MT6589_GPIO17__FUNC_IRDA_PDN (MTK_PIN_NO(17) | 5) +#define MT6589_GPIO17__FUNC_MD_ABB_AFUNC_D_2 (MTK_PIN_NO(17) | 6) +#define MT6589_GPIO17__FUNC_TESTA_OUT10 (MTK_PIN_NO(17) | 7) + +#define MT6589_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6589_GPIO18__FUNC_NLD0 (MTK_PIN_NO(18) | 1) +#define MT6589_GPIO18__FUNC_EINT146 (MTK_PIN_NO(18) | 2) +#define MT6589_GPIO18__FUNC_DPI1_D_1X_0 (MTK_PIN_NO(18) | 3) +#define MT6589_GPIO18__FUNC_CM2DAT_1X_0 (MTK_PIN_NO(18) | 4) +#define MT6589_GPIO18__FUNC_I2SIN_CK (MTK_PIN_NO(18) | 5) +#define MT6589_GPIO18__FUNC_DAC_CK (MTK_PIN_NO(18) | 6) +#define MT6589_GPIO18__FUNC_TESTA_OUT11 (MTK_PIN_NO(18) | 7) + +#define MT6589_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6589_GPIO19__FUNC_NLD1 (MTK_PIN_NO(19) | 1) +#define MT6589_GPIO19__FUNC_EINT147 (MTK_PIN_NO(19) | 2) +#define MT6589_GPIO19__FUNC_DPI1_D_1X_1 (MTK_PIN_NO(19) | 3) +#define MT6589_GPIO19__FUNC_CM2DAT_1X_1 (MTK_PIN_NO(19) | 4) +#define MT6589_GPIO19__FUNC_I2SIN_WS (MTK_PIN_NO(19) | 5) +#define MT6589_GPIO19__FUNC_DAC_WS (MTK_PIN_NO(19) | 6) +#define MT6589_GPIO19__FUNC_TESTA_OUT12 (MTK_PIN_NO(19) | 7) + +#define MT6589_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6589_GPIO20__FUNC_NLD2 (MTK_PIN_NO(20) | 1) +#define MT6589_GPIO20__FUNC_EINT148 (MTK_PIN_NO(20) | 2) +#define MT6589_GPIO20__FUNC_DPI1_D_1X_2 (MTK_PIN_NO(20) | 3) +#define MT6589_GPIO20__FUNC_CM2DAT_1X_2 (MTK_PIN_NO(20) | 4) +#define MT6589_GPIO20__FUNC_I2SOUT_DAT (MTK_PIN_NO(20) | 5) +#define MT6589_GPIO20__FUNC_DAC_DAT_OUT (MTK_PIN_NO(20) | 6) +#define MT6589_GPIO20__FUNC_TESTA_OUT13 (MTK_PIN_NO(20) | 7) + +#define MT6589_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6589_GPIO21__FUNC_NLD3 (MTK_PIN_NO(21) | 1) +#define MT6589_GPIO21__FUNC_EINT149 (MTK_PIN_NO(21) | 2) +#define MT6589_GPIO21__FUNC_DPI1_D_1X_3 (MTK_PIN_NO(21) | 3) +#define MT6589_GPIO21__FUNC_CM2DAT_1X_3 (MTK_PIN_NO(21) | 4) +#define MT6589_GPIO21__FUNC_MD_ABB_AFUNC_D_3 (MTK_PIN_NO(21) | 6) +#define MT6589_GPIO21__FUNC_TESTA_OUT14 (MTK_PIN_NO(21) | 7) + +#define MT6589_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6589_GPIO22__FUNC_NLD4 (MTK_PIN_NO(22) | 1) +#define MT6589_GPIO22__FUNC_EINT150 (MTK_PIN_NO(22) | 2) +#define MT6589_GPIO22__FUNC_DPI1_D_1X_4 (MTK_PIN_NO(22) | 3) +#define MT6589_GPIO22__FUNC_CM2DAT_1X_4 (MTK_PIN_NO(22) | 4) +#define MT6589_GPIO22__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(22) | 5) +#define MT6589_GPIO22__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(22) | 6) +#define MT6589_GPIO22__FUNC_TESTA_OUT15 (MTK_PIN_NO(22) | 7) + +#define MT6589_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6589_GPIO23__FUNC_NLD5 (MTK_PIN_NO(23) | 1) +#define MT6589_GPIO23__FUNC_EINT151 (MTK_PIN_NO(23) | 2) +#define MT6589_GPIO23__FUNC_DPI1_D_1X_5 (MTK_PIN_NO(23) | 3) +#define MT6589_GPIO23__FUNC_CM2DAT_1X_5 (MTK_PIN_NO(23) | 4) +#define MT6589_GPIO23__FUNC_MD_ABB_AFUNC_D_4 (MTK_PIN_NO(23) | 6) +#define MT6589_GPIO23__FUNC_TESTA_OUT16 (MTK_PIN_NO(23) | 7) + +#define MT6589_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6589_GPIO24__FUNC_NLD6 (MTK_PIN_NO(24) | 1) +#define MT6589_GPIO24__FUNC_EINT152 (MTK_PIN_NO(24) | 2) +#define MT6589_GPIO24__FUNC_DPI1_D_1X_6 (MTK_PIN_NO(24) | 3) +#define MT6589_GPIO24__FUNC_CM2DAT_1X_6 (MTK_PIN_NO(24) | 4) +#define MT6589_GPIO24__FUNC_MD_ABB_AFUNC_D_5 (MTK_PIN_NO(24) | 6) +#define MT6589_GPIO24__FUNC_TESTA_OUT17 (MTK_PIN_NO(24) | 7) + +#define MT6589_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6589_GPIO25__FUNC_NLD7 (MTK_PIN_NO(25) | 1) +#define MT6589_GPIO25__FUNC_EINT153 (MTK_PIN_NO(25) | 2) +#define MT6589_GPIO25__FUNC_DPI1_D_1X_7 (MTK_PIN_NO(25) | 3) +#define MT6589_GPIO25__FUNC_CM2DAT_1X_7 (MTK_PIN_NO(25) | 4) +#define MT6589_GPIO25__FUNC_MD_ABB_AFUNC_D_6 (MTK_PIN_NO(25) | 6) +#define MT6589_GPIO25__FUNC_TESTA_OUT18 (MTK_PIN_NO(25) | 7) + +#define MT6589_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6589_GPIO26__FUNC_NLD8 (MTK_PIN_NO(26) | 1) +#define MT6589_GPIO26__FUNC_EINT154 (MTK_PIN_NO(26) | 2) +#define MT6589_GPIO26__FUNC_DPI1_D_1X_8 (MTK_PIN_NO(26) | 3) +#define MT6589_GPIO26__FUNC_CM2DAT_1X_8 (MTK_PIN_NO(26) | 4) +#define MT6589_GPIO26__FUNC_MD_ABB_AFUNC_D_7 (MTK_PIN_NO(26) | 6) +#define MT6589_GPIO26__FUNC_TESTA_OUT19 (MTK_PIN_NO(26) | 7) + +#define MT6589_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6589_GPIO27__FUNC_NLD9 (MTK_PIN_NO(27) | 1) +#define MT6589_GPIO27__FUNC_EINT155 (MTK_PIN_NO(27) | 2) +#define MT6589_GPIO27__FUNC_DPI1_D_1X_9 (MTK_PIN_NO(27) | 3) +#define MT6589_GPIO27__FUNC_CM2DAT_1X_9 (MTK_PIN_NO(27) | 4) +#define MT6589_GPIO27__FUNC_PWM1 (MTK_PIN_NO(27) | 5) +#define MT6589_GPIO27__FUNC_MD_ABB_AFUNC_D_8 (MTK_PIN_NO(27) | 6) +#define MT6589_GPIO27__FUNC_TESTA_OUT20 (MTK_PIN_NO(27) | 7) + +#define MT6589_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6589_GPIO28__FUNC_NLD10 (MTK_PIN_NO(28) | 1) +#define MT6589_GPIO28__FUNC_EINT156 (MTK_PIN_NO(28) | 2) +#define MT6589_GPIO28__FUNC_DPI1_D_1X_10 (MTK_PIN_NO(28) | 3) +#define MT6589_GPIO28__FUNC_CM2VSYNC_1X (MTK_PIN_NO(28) | 4) +#define MT6589_GPIO28__FUNC_PWM2 (MTK_PIN_NO(28) | 5) +#define MT6589_GPIO28__FUNC_MD_ABB_AFUNC_D_9 (MTK_PIN_NO(28) | 6) +#define MT6589_GPIO28__FUNC_TESTA_OUT21 (MTK_PIN_NO(28) | 7) + +#define MT6589_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6589_GPIO29__FUNC_NLD11 (MTK_PIN_NO(29) | 1) +#define MT6589_GPIO29__FUNC_EINT157 (MTK_PIN_NO(29) | 2) +#define MT6589_GPIO29__FUNC_DPI1_D_1X_11 (MTK_PIN_NO(29) | 3) +#define MT6589_GPIO29__FUNC_CM2HSYNC_1X (MTK_PIN_NO(29) | 4) +#define MT6589_GPIO29__FUNC_PWM3 (MTK_PIN_NO(29) | 5) +#define MT6589_GPIO29__FUNC_MD_ABB_AFUNC_D_10 (MTK_PIN_NO(29) | 6) +#define MT6589_GPIO29__FUNC_TESTA_OUT22 (MTK_PIN_NO(29) | 7) + +#define MT6589_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6589_GPIO30__FUNC_NLD12 (MTK_PIN_NO(30) | 1) +#define MT6589_GPIO30__FUNC_EINT158 (MTK_PIN_NO(30) | 2) +#define MT6589_GPIO30__FUNC_I2SIN_CK (MTK_PIN_NO(30) | 3) +#define MT6589_GPIO30__FUNC_DAC_CK (MTK_PIN_NO(30) | 4) +#define MT6589_GPIO30__FUNC_PCM1_CK (MTK_PIN_NO(30) | 5) +#define MT6589_GPIO30__FUNC_MD_ABB_AFUNC_D_11 (MTK_PIN_NO(30) | 6) +#define MT6589_GPIO30__FUNC_TESTA_OUT23 (MTK_PIN_NO(30) | 7) + +#define MT6589_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6589_GPIO31__FUNC_NLD13 (MTK_PIN_NO(31) | 1) +#define MT6589_GPIO31__FUNC_EINT159 (MTK_PIN_NO(31) | 2) +#define MT6589_GPIO31__FUNC_I2SIN_WS (MTK_PIN_NO(31) | 3) +#define MT6589_GPIO31__FUNC_DAC_WS (MTK_PIN_NO(31) | 4) +#define MT6589_GPIO31__FUNC_PCM1_WS (MTK_PIN_NO(31) | 5) +#define MT6589_GPIO31__FUNC_MD_ABB_AFUNC_D_12 (MTK_PIN_NO(31) | 6) +#define MT6589_GPIO31__FUNC_TESTA_OUT24 (MTK_PIN_NO(31) | 7) + +#define MT6589_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6589_GPIO32__FUNC_NLD14 (MTK_PIN_NO(32) | 1) +#define MT6589_GPIO32__FUNC_EINT160 (MTK_PIN_NO(32) | 2) +#define MT6589_GPIO32__FUNC_I2SOUT_DAT (MTK_PIN_NO(32) | 3) +#define MT6589_GPIO32__FUNC_DAC_DAT_OUT (MTK_PIN_NO(32) | 4) +#define MT6589_GPIO32__FUNC_PCM1_DO (MTK_PIN_NO(32) | 5) +#define MT6589_GPIO32__FUNC_MD_ABB_AFUNC_D_13 (MTK_PIN_NO(32) | 6) +#define MT6589_GPIO32__FUNC_TESTA_OUT25 (MTK_PIN_NO(32) | 7) + +#define MT6589_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6589_GPIO33__FUNC_NLD15 (MTK_PIN_NO(33) | 1) +#define MT6589_GPIO33__FUNC_EINT161 (MTK_PIN_NO(33) | 2) +#define MT6589_GPIO33__FUNC_DISP_PWM (MTK_PIN_NO(33) | 3) +#define MT6589_GPIO33__FUNC_PWM4 (MTK_PIN_NO(33) | 4) +#define MT6589_GPIO33__FUNC_PCM1_DI (MTK_PIN_NO(33) | 5) +#define MT6589_GPIO33__FUNC_MD_ABB_AFUNC_D_14 (MTK_PIN_NO(33) | 6) +#define MT6589_GPIO33__FUNC_TESTA_OUT26 (MTK_PIN_NO(33) | 7) + +#define MT6589_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6589_GPIO34__FUNC_EINT0 (MTK_PIN_NO(34) | 1) +#define MT6589_GPIO34__FUNC_PWM1 (MTK_PIN_NO(34) | 2) +#define MT6589_GPIO34__FUNC_CLKM0 (MTK_PIN_NO(34) | 3) +#define MT6589_GPIO34__FUNC_MD2_UTXD (MTK_PIN_NO(34) | 5) +#define MT6589_GPIO34__FUNC_MD1_EINT1 (MTK_PIN_NO(34) | 6) +#define MT6589_GPIO34__FUNC_USB_SCL (MTK_PIN_NO(34) | 7) + +#define MT6589_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6589_GPIO35__FUNC_EINT1 (MTK_PIN_NO(35) | 1) +#define MT6589_GPIO35__FUNC_PWM2 (MTK_PIN_NO(35) | 2) +#define MT6589_GPIO35__FUNC_CLKM1 (MTK_PIN_NO(35) | 3) +#define MT6589_GPIO35__FUNC_MD2_URXD (MTK_PIN_NO(35) | 5) +#define MT6589_GPIO35__FUNC_MD1_EINT2 (MTK_PIN_NO(35) | 6) +#define MT6589_GPIO35__FUNC_USB_SDA (MTK_PIN_NO(35) | 7) + +#define MT6589_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6589_GPIO36__FUNC_EINT2 (MTK_PIN_NO(36) | 1) +#define MT6589_GPIO36__FUNC_PWM3 (MTK_PIN_NO(36) | 2) +#define MT6589_GPIO36__FUNC_CLKM2 (MTK_PIN_NO(36) | 3) +#define MT6589_GPIO36__FUNC_SRCLKENAI2 (MTK_PIN_NO(36) | 4) +#define MT6589_GPIO36__FUNC_MD1_EINT3 (MTK_PIN_NO(36) | 6) + +#define MT6589_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6589_GPIO37__FUNC_EINT3 (MTK_PIN_NO(37) | 1) +#define MT6589_GPIO37__FUNC_MD1_EINT5 (MTK_PIN_NO(37) | 6) +#define MT6589_GPIO37__FUNC_EXT_26M_CK (MTK_PIN_NO(37) | 7) + +#define MT6589_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6589_GPIO38__FUNC_EINT4 (MTK_PIN_NO(38) | 1) +#define MT6589_GPIO38__FUNC_PWM4 (MTK_PIN_NO(38) | 2) +#define MT6589_GPIO38__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(38) | 3) +#define MT6589_GPIO38__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(38) | 4) +#define MT6589_GPIO38__FUNC_USB_DRVVBUS (MTK_PIN_NO(38) | 5) +#define MT6589_GPIO38__FUNC_MD1_EINT4 (MTK_PIN_NO(38) | 6) + +#define MT6589_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6589_GPIO39__FUNC_PWRAP_SPIDI (MTK_PIN_NO(39) | 1) +#define MT6589_GPIO39__FUNC_EINT29 (MTK_PIN_NO(39) | 2) + +#define MT6589_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6589_GPIO40__FUNC_PWRAP_SPIDO (MTK_PIN_NO(40) | 1) +#define MT6589_GPIO40__FUNC_EINT28 (MTK_PIN_NO(40) | 2) + +#define MT6589_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6589_GPIO41__FUNC_PWRAP_SPICS_B_I (MTK_PIN_NO(41) | 1) +#define MT6589_GPIO41__FUNC_EINT27 (MTK_PIN_NO(41) | 2) + +#define MT6589_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6589_GPIO42__FUNC_PWRAP_SPICK_I (MTK_PIN_NO(42) | 1) +#define MT6589_GPIO42__FUNC_EINT26 (MTK_PIN_NO(42) | 2) + +#define MT6589_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6589_GPIO43__FUNC_PWRAP_EVENT_IN (MTK_PIN_NO(43) | 1) +#define MT6589_GPIO43__FUNC_EINT25 (MTK_PIN_NO(43) | 2) + +#define MT6589_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6589_GPIO44__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(44) | 1) +#define MT6589_GPIO44__FUNC_EINT30 (MTK_PIN_NO(44) | 2) +#define MT6589_GPIO44__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(44) | 3) +#define MT6589_GPIO44__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(44) | 4) +#define MT6589_GPIO44__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(44) | 5) +#define MT6589_GPIO44__FUNC_MD_ABB_AFUNC_D_15 (MTK_PIN_NO(44) | 6) + +#define MT6589_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6589_GPIO45__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(45) | 1) +#define MT6589_GPIO45__FUNC_EINT31 (MTK_PIN_NO(45) | 2) +#define MT6589_GPIO45__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(45) | 3) +#define MT6589_GPIO45__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(45) | 4) +#define MT6589_GPIO45__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(45) | 5) +#define MT6589_GPIO45__FUNC_MD_ABB_AFUNC_D_16 (MTK_PIN_NO(45) | 6) + +#define MT6589_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6589_GPIO46__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(46) | 1) +#define MT6589_GPIO46__FUNC_EINT32 (MTK_PIN_NO(46) | 2) +#define MT6589_GPIO46__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(46) | 3) +#define MT6589_GPIO46__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(46) | 4) +#define MT6589_GPIO46__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(46) | 5) +#define MT6589_GPIO46__FUNC_MD_ABB_AFUNC_D_17 (MTK_PIN_NO(46) | 6) + +#define MT6589_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6589_GPIO47__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(47) | 1) +#define MT6589_GPIO47__FUNC_EINT33 (MTK_PIN_NO(47) | 2) +#define MT6589_GPIO47__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(47) | 3) +#define MT6589_GPIO47__FUNC_MD2_SIM2_SCLK (MTK_PIN_NO(47) | 4) +#define MT6589_GPIO47__FUNC_MD2_SIM1_SCLK (MTK_PIN_NO(47) | 5) +#define MT6589_GPIO47__FUNC_MD_ABB_AFUNC_D_18 (MTK_PIN_NO(47) | 6) + +#define MT6589_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6589_GPIO48__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(48) | 1) +#define MT6589_GPIO48__FUNC_EINT34 (MTK_PIN_NO(48) | 2) +#define MT6589_GPIO48__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(48) | 3) +#define MT6589_GPIO48__FUNC_MD2_SIM2_SRST (MTK_PIN_NO(48) | 4) +#define MT6589_GPIO48__FUNC_MD2_SIM1_SRST (MTK_PIN_NO(48) | 5) +#define MT6589_GPIO48__FUNC_MD_ABB_AFUNC_D_19 (MTK_PIN_NO(48) | 6) + +#define MT6589_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT6589_GPIO49__FUNC_MD1_SIM2_SDAT (MTK_PIN_NO(49) | 1) +#define MT6589_GPIO49__FUNC_EINT35 (MTK_PIN_NO(49) | 2) +#define MT6589_GPIO49__FUNC_MD1_SIM1_SDAT (MTK_PIN_NO(49) | 3) +#define MT6589_GPIO49__FUNC_MD2_SIM2_SDAT (MTK_PIN_NO(49) | 4) +#define MT6589_GPIO49__FUNC_MD2_SIM1_SDAT (MTK_PIN_NO(49) | 5) +#define MT6589_GPIO49__FUNC_MD_ABB_AFUNC_D_20 (MTK_PIN_NO(49) | 6) + +#define MT6589_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT6589_GPIO50__FUNC_ADC_CK (MTK_PIN_NO(50) | 1) +#define MT6589_GPIO50__FUNC_EINT19 (MTK_PIN_NO(50) | 2) + +#define MT6589_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT6589_GPIO51__FUNC_ADC_WS (MTK_PIN_NO(51) | 1) +#define MT6589_GPIO51__FUNC_EINT21 (MTK_PIN_NO(51) | 2) + +#define MT6589_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT6589_GPIO52__FUNC_ADC_DAT_IN (MTK_PIN_NO(52) | 1) +#define MT6589_GPIO52__FUNC_EINT20 (MTK_PIN_NO(52) | 2) + +#define MT6589_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT6589_GPIO53__FUNC_DAC_CK (MTK_PIN_NO(53) | 1) +#define MT6589_GPIO53__FUNC_EINT22 (MTK_PIN_NO(53) | 2) + +#define MT6589_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT6589_GPIO54__FUNC_DAC_WS (MTK_PIN_NO(54) | 1) +#define MT6589_GPIO54__FUNC_EINT24 (MTK_PIN_NO(54) | 2) + +#define MT6589_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT6589_GPIO55__FUNC_DAC_DAT_OUT (MTK_PIN_NO(55) | 1) +#define MT6589_GPIO55__FUNC_EINT23 (MTK_PIN_NO(55) | 2) + +#define MT6589_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT6589_GPIO56__FUNC_RTC32K_CK (MTK_PIN_NO(56) | 1) + +#define MT6589_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT6589_GPIO57__FUNC_IDDIG (MTK_PIN_NO(57) | 1) +#define MT6589_GPIO57__FUNC_EINT34 (MTK_PIN_NO(57) | 2) + +#define MT6589_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT6589_GPIO58__FUNC_WATCHDOG (MTK_PIN_NO(58) | 1) +#define MT6589_GPIO58__FUNC_EINT36 (MTK_PIN_NO(58) | 2) + +#define MT6589_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT6589_GPIO59__FUNC_SRCLKENA (MTK_PIN_NO(59) | 1) +#define MT6589_GPIO59__FUNC_EINT38 (MTK_PIN_NO(59) | 2) + +#define MT6589_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT6589_GPIO60__FUNC_SRCVOLTEN (MTK_PIN_NO(60) | 1) +#define MT6589_GPIO60__FUNC_EINT37 (MTK_PIN_NO(60) | 2) + +#define MT6589_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT6589_GPIO61__FUNC_JTCK (MTK_PIN_NO(61) | 1) +#define MT6589_GPIO61__FUNC_EINT188 (MTK_PIN_NO(61) | 2) +#define MT6589_GPIO61__FUNC_DSP1_ICK (MTK_PIN_NO(61) | 3) +#define MT6589_GPIO61__FUNC_MD2_TCK_PAD (MTK_PIN_NO(61) | 7) + +#define MT6589_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT6589_GPIO62__FUNC_JTDO (MTK_PIN_NO(62) | 1) +#define MT6589_GPIO62__FUNC_EINT190 (MTK_PIN_NO(62) | 2) +#define MT6589_GPIO62__FUNC_DSP2_IMS (MTK_PIN_NO(62) | 3) +#define MT6589_GPIO62__FUNC_MD2_TDO_PAD (MTK_PIN_NO(62) | 7) + +#define MT6589_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT6589_GPIO63__FUNC_JTRST_B (MTK_PIN_NO(63) | 1) +#define MT6589_GPIO63__FUNC_EINT0 (MTK_PIN_NO(63) | 2) +#define MT6589_GPIO63__FUNC_DSP2_ICK (MTK_PIN_NO(63) | 3) +#define MT6589_GPIO63__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(63) | 7) + +#define MT6589_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT6589_GPIO64__FUNC_JTDI (MTK_PIN_NO(64) | 1) +#define MT6589_GPIO64__FUNC_EINT189 (MTK_PIN_NO(64) | 2) +#define MT6589_GPIO64__FUNC_DSP1_IMS (MTK_PIN_NO(64) | 3) +#define MT6589_GPIO64__FUNC_MD2_TDI_PAD (MTK_PIN_NO(64) | 7) + +#define MT6589_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT6589_GPIO65__FUNC_JRTCK (MTK_PIN_NO(65) | 1) +#define MT6589_GPIO65__FUNC_EINT187 (MTK_PIN_NO(65) | 2) +#define MT6589_GPIO65__FUNC_DSP1_ID (MTK_PIN_NO(65) | 3) +#define MT6589_GPIO65__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(65) | 7) + +#define MT6589_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT6589_GPIO66__FUNC_JTMS (MTK_PIN_NO(66) | 1) +#define MT6589_GPIO66__FUNC_EINT191 (MTK_PIN_NO(66) | 2) +#define MT6589_GPIO66__FUNC_DSP2_ID (MTK_PIN_NO(66) | 3) +#define MT6589_GPIO66__FUNC_MD2_TMS_PAD (MTK_PIN_NO(66) | 7) + +#define MT6589_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT6589_GPIO67__FUNC_SDA3 (MTK_PIN_NO(67) | 1) +#define MT6589_GPIO67__FUNC_EINT97 (MTK_PIN_NO(67) | 2) +#define MT6589_GPIO67__FUNC_A_FUNC_DIN_13 (MTK_PIN_NO(67) | 7) + +#define MT6589_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT6589_GPIO68__FUNC_SCL3 (MTK_PIN_NO(68) | 1) +#define MT6589_GPIO68__FUNC_EINT96 (MTK_PIN_NO(68) | 2) +#define MT6589_GPIO68__FUNC_CLKM6 (MTK_PIN_NO(68) | 3) +#define MT6589_GPIO68__FUNC_PWM6 (MTK_PIN_NO(68) | 4) +#define MT6589_GPIO68__FUNC_A_FUNC_DIN_14 (MTK_PIN_NO(68) | 7) + +#define MT6589_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT6589_GPIO69__FUNC_URXD2 (MTK_PIN_NO(69) | 1) +#define MT6589_GPIO69__FUNC_EINT83 (MTK_PIN_NO(69) | 2) +#define MT6589_GPIO69__FUNC_BSI2_CLK (MTK_PIN_NO(69) | 3) +#define MT6589_GPIO69__FUNC_MD1_URXD (MTK_PIN_NO(69) | 4) +#define MT6589_GPIO69__FUNC_CLKM3 (MTK_PIN_NO(69) | 5) +#define MT6589_GPIO69__FUNC_UTXD2 (MTK_PIN_NO(69) | 6) +#define MT6589_GPIO69__FUNC_MD1_EINT4 (MTK_PIN_NO(69) | 7) + +#define MT6589_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT6589_GPIO70__FUNC_UTXD2 (MTK_PIN_NO(70) | 1) +#define MT6589_GPIO70__FUNC_EINT82 (MTK_PIN_NO(70) | 2) +#define MT6589_GPIO70__FUNC_BSI2_CS (MTK_PIN_NO(70) | 3) +#define MT6589_GPIO70__FUNC_MD1_UTXD (MTK_PIN_NO(70) | 4) +#define MT6589_GPIO70__FUNC_CLKM2 (MTK_PIN_NO(70) | 5) +#define MT6589_GPIO70__FUNC_URXD2 (MTK_PIN_NO(70) | 6) +#define MT6589_GPIO70__FUNC_MD1_EINT3 (MTK_PIN_NO(70) | 7) + +#define MT6589_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT6589_GPIO71__FUNC_UCTS2 (MTK_PIN_NO(71) | 1) +#define MT6589_GPIO71__FUNC_EINT84 (MTK_PIN_NO(71) | 2) +#define MT6589_GPIO71__FUNC_BSI2_DATA0 (MTK_PIN_NO(71) | 3) +#define MT6589_GPIO71__FUNC_MD2_UTXD (MTK_PIN_NO(71) | 4) +#define MT6589_GPIO71__FUNC_PWM1 (MTK_PIN_NO(71) | 5) +#define MT6589_GPIO71__FUNC_URTS2 (MTK_PIN_NO(71) | 6) +#define MT6589_GPIO71__FUNC_MD2_EINT1 (MTK_PIN_NO(71) | 7) + +#define MT6589_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT6589_GPIO72__FUNC_URTS2 (MTK_PIN_NO(72) | 1) +#define MT6589_GPIO72__FUNC_EINT85 (MTK_PIN_NO(72) | 2) +#define MT6589_GPIO72__FUNC_BSI2_DATA1 (MTK_PIN_NO(72) | 3) +#define MT6589_GPIO72__FUNC_MD2_URXD (MTK_PIN_NO(72) | 4) +#define MT6589_GPIO72__FUNC_PWM2 (MTK_PIN_NO(72) | 5) +#define MT6589_GPIO72__FUNC_UCTS2 (MTK_PIN_NO(72) | 6) +#define MT6589_GPIO72__FUNC_MD2_EINT2 (MTK_PIN_NO(72) | 7) + +#define MT6589_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT6589_GPIO73__FUNC_PWM1 (MTK_PIN_NO(73) | 1) +#define MT6589_GPIO73__FUNC_EINT73 (MTK_PIN_NO(73) | 2) +#define MT6589_GPIO73__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(73) | 3) +#define MT6589_GPIO73__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(73) | 4) +#define MT6589_GPIO73__FUNC_USB_DRVVBUS (MTK_PIN_NO(73) | 5) +#define MT6589_GPIO73__FUNC_DISP_PWM (MTK_PIN_NO(73) | 6) +#define MT6589_GPIO73__FUNC_MD2_TCK_PAD (MTK_PIN_NO(73) | 7) + +#define MT6589_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT6589_GPIO74__FUNC_PWM2 (MTK_PIN_NO(74) | 1) +#define MT6589_GPIO74__FUNC_EINT74 (MTK_PIN_NO(74) | 2) +#define MT6589_GPIO74__FUNC_BPI2_BUS11 (MTK_PIN_NO(74) | 3) +#define MT6589_GPIO74__FUNC_PWM5 (MTK_PIN_NO(74) | 4) +#define MT6589_GPIO74__FUNC_URXD2 (MTK_PIN_NO(74) | 5) +#define MT6589_GPIO74__FUNC_DISP_PWM (MTK_PIN_NO(74) | 6) +#define MT6589_GPIO74__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(74) | 7) + +#define MT6589_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT6589_GPIO75__FUNC_PWM3 (MTK_PIN_NO(75) | 1) +#define MT6589_GPIO75__FUNC_EINT75 (MTK_PIN_NO(75) | 2) +#define MT6589_GPIO75__FUNC_BPI2_BUS12 (MTK_PIN_NO(75) | 3) +#define MT6589_GPIO75__FUNC_PWM6 (MTK_PIN_NO(75) | 4) +#define MT6589_GPIO75__FUNC_UTXD2 (MTK_PIN_NO(75) | 5) +#define MT6589_GPIO75__FUNC_DISP_PWM (MTK_PIN_NO(75) | 6) +#define MT6589_GPIO75__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(75) | 7) + +#define MT6589_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT6589_GPIO76__FUNC_PWM4 (MTK_PIN_NO(76) | 1) +#define MT6589_GPIO76__FUNC_EINT76 (MTK_PIN_NO(76) | 2) +#define MT6589_GPIO76__FUNC_BPI2_BUS13 (MTK_PIN_NO(76) | 3) +#define MT6589_GPIO76__FUNC_PWM7 (MTK_PIN_NO(76) | 4) +#define MT6589_GPIO76__FUNC_DISP_PWM (MTK_PIN_NO(76) | 6) +#define MT6589_GPIO76__FUNC_MD2_TMS_PAD (MTK_PIN_NO(76) | 7) + +#define MT6589_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT6589_GPIO77__FUNC_URXD1 (MTK_PIN_NO(77) | 1) +#define MT6589_GPIO77__FUNC_EINT79 (MTK_PIN_NO(77) | 2) +#define MT6589_GPIO77__FUNC_URXD4 (MTK_PIN_NO(77) | 3) +#define MT6589_GPIO77__FUNC_MD1_URXD (MTK_PIN_NO(77) | 4) +#define MT6589_GPIO77__FUNC_MD2_URXD (MTK_PIN_NO(77) | 5) +#define MT6589_GPIO77__FUNC_UTXD1 (MTK_PIN_NO(77) | 6) +#define MT6589_GPIO77__FUNC_MD2_TDO_PAD (MTK_PIN_NO(77) | 7) + +#define MT6589_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT6589_GPIO78__FUNC_UTXD1 (MTK_PIN_NO(78) | 1) +#define MT6589_GPIO78__FUNC_EINT78 (MTK_PIN_NO(78) | 2) +#define MT6589_GPIO78__FUNC_UTXD4 (MTK_PIN_NO(78) | 3) +#define MT6589_GPIO78__FUNC_MD1_UTXD (MTK_PIN_NO(78) | 4) +#define MT6589_GPIO78__FUNC_MD2_UTXD (MTK_PIN_NO(78) | 5) +#define MT6589_GPIO78__FUNC_URXD1 (MTK_PIN_NO(78) | 6) +#define MT6589_GPIO78__FUNC_MD2_TDI_PAD (MTK_PIN_NO(78) | 7) + +#define MT6589_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT6589_GPIO79__FUNC_UCTS1 (MTK_PIN_NO(79) | 1) +#define MT6589_GPIO79__FUNC_EINT80 (MTK_PIN_NO(79) | 2) +#define MT6589_GPIO79__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(79) | 3) +#define MT6589_GPIO79__FUNC_MD1_UTXD (MTK_PIN_NO(79) | 4) +#define MT6589_GPIO79__FUNC_CLKM0 (MTK_PIN_NO(79) | 5) +#define MT6589_GPIO79__FUNC_URTS1 (MTK_PIN_NO(79) | 6) +#define MT6589_GPIO79__FUNC_MD1_EINT1 (MTK_PIN_NO(79) | 7) + +#define MT6589_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT6589_GPIO80__FUNC_URTS1 (MTK_PIN_NO(80) | 1) +#define MT6589_GPIO80__FUNC_EINT81 (MTK_PIN_NO(80) | 2) +#define MT6589_GPIO80__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(80) | 3) +#define MT6589_GPIO80__FUNC_MD1_URXD (MTK_PIN_NO(80) | 4) +#define MT6589_GPIO80__FUNC_CLKM1 (MTK_PIN_NO(80) | 5) +#define MT6589_GPIO80__FUNC_UCTS1 (MTK_PIN_NO(80) | 6) +#define MT6589_GPIO80__FUNC_MD1_EINT2 (MTK_PIN_NO(80) | 7) + +#define MT6589_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT6589_GPIO81__FUNC_URXD4 (MTK_PIN_NO(81) | 1) +#define MT6589_GPIO81__FUNC_EINT89 (MTK_PIN_NO(81) | 2) +#define MT6589_GPIO81__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT6589_GPIO81__FUNC_MD1_URXD (MTK_PIN_NO(81) | 4) +#define MT6589_GPIO81__FUNC_MD2_URXD (MTK_PIN_NO(81) | 5) +#define MT6589_GPIO81__FUNC_UTXD4 (MTK_PIN_NO(81) | 6) +#define MT6589_GPIO81__FUNC_MD2_EINT5 (MTK_PIN_NO(81) | 7) + +#define MT6589_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT6589_GPIO82__FUNC_UTXD4 (MTK_PIN_NO(82) | 1) +#define MT6589_GPIO82__FUNC_EINT88 (MTK_PIN_NO(82) | 2) +#define MT6589_GPIO82__FUNC_UTXD1 (MTK_PIN_NO(82) | 3) +#define MT6589_GPIO82__FUNC_MD1_UTXD (MTK_PIN_NO(82) | 4) +#define MT6589_GPIO82__FUNC_MD2_UTXD (MTK_PIN_NO(82) | 5) +#define MT6589_GPIO82__FUNC_URXD4 (MTK_PIN_NO(82) | 6) +#define MT6589_GPIO82__FUNC_MD1_EINT5 (MTK_PIN_NO(82) | 7) + +#define MT6589_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT6589_GPIO83__FUNC_DUAL_BPI1_BUS0 (MTK_PIN_NO(83) | 1) +#define MT6589_GPIO83__FUNC_EINT1 (MTK_PIN_NO(83) | 2) +#define MT6589_GPIO83__FUNC_BPI2_BUS0 (MTK_PIN_NO(83) | 3) +#define MT6589_GPIO83__FUNC_USB_TEST_IO_0 (MTK_PIN_NO(83) | 5) +#define MT6589_GPIO83__FUNC_A_FUNC_DIN_31 (MTK_PIN_NO(83) | 7) + +#define MT6589_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT6589_GPIO84__FUNC_DUAL_BPI1_BUS1 (MTK_PIN_NO(84) | 1) +#define MT6589_GPIO84__FUNC_EINT2 (MTK_PIN_NO(84) | 2) +#define MT6589_GPIO84__FUNC_BPI2_BUS1 (MTK_PIN_NO(84) | 3) +#define MT6589_GPIO84__FUNC_USB_TEST_IO_1 (MTK_PIN_NO(84) | 5) +#define MT6589_GPIO84__FUNC_A_FUNC_DIN_30 (MTK_PIN_NO(84) | 7) + +#define MT6589_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT6589_GPIO85__FUNC_DUAL_BPI1_BUS2 (MTK_PIN_NO(85) | 1) +#define MT6589_GPIO85__FUNC_EINT3 (MTK_PIN_NO(85) | 2) +#define MT6589_GPIO85__FUNC_BPI2_BUS2 (MTK_PIN_NO(85) | 3) +#define MT6589_GPIO85__FUNC_USB_TEST_IO_2 (MTK_PIN_NO(85) | 5) +#define MT6589_GPIO85__FUNC_A_FUNC_DIN_29 (MTK_PIN_NO(85) | 7) + +#define MT6589_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT6589_GPIO86__FUNC_DUAL_BPI1_BUS3 (MTK_PIN_NO(86) | 1) +#define MT6589_GPIO86__FUNC_EINT4 (MTK_PIN_NO(86) | 2) +#define MT6589_GPIO86__FUNC_BPI2_BUS3 (MTK_PIN_NO(86) | 3) +#define MT6589_GPIO86__FUNC_USB_TEST_IO_3 (MTK_PIN_NO(86) | 5) +#define MT6589_GPIO86__FUNC_A_FUNC_DIN_28 (MTK_PIN_NO(86) | 7) + +#define MT6589_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT6589_GPIO87__FUNC_DUAL_BPI1_BUS4 (MTK_PIN_NO(87) | 1) +#define MT6589_GPIO87__FUNC_EINT5 (MTK_PIN_NO(87) | 2) +#define MT6589_GPIO87__FUNC_BPI2_BUS4 (MTK_PIN_NO(87) | 3) +#define MT6589_GPIO87__FUNC_USB_TEST_IO_4 (MTK_PIN_NO(87) | 5) +#define MT6589_GPIO87__FUNC_A_FUNC_DIN_27 (MTK_PIN_NO(87) | 7) + +#define MT6589_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT6589_GPIO88__FUNC_DUAL_BPI1_BUS5 (MTK_PIN_NO(88) | 1) +#define MT6589_GPIO88__FUNC_EINT6 (MTK_PIN_NO(88) | 2) +#define MT6589_GPIO88__FUNC_BPI2_BUS5 (MTK_PIN_NO(88) | 3) +#define MT6589_GPIO88__FUNC_USB_TEST_IO_5 (MTK_PIN_NO(88) | 5) +#define MT6589_GPIO88__FUNC_A_FUNC_DIN_26 (MTK_PIN_NO(88) | 7) + +#define MT6589_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT6589_GPIO89__FUNC_DUAL_BPI1_BUS6 (MTK_PIN_NO(89) | 1) +#define MT6589_GPIO89__FUNC_EINT7 (MTK_PIN_NO(89) | 2) +#define MT6589_GPIO89__FUNC_BPI2_BUS6 (MTK_PIN_NO(89) | 3) +#define MT6589_GPIO89__FUNC_USB_TEST_IO_6 (MTK_PIN_NO(89) | 5) +#define MT6589_GPIO89__FUNC_A_FUNC_DIN_25 (MTK_PIN_NO(89) | 7) + +#define MT6589_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT6589_GPIO90__FUNC_DUAL_BPI1_BUS7 (MTK_PIN_NO(90) | 1) +#define MT6589_GPIO90__FUNC_EINT8 (MTK_PIN_NO(90) | 2) +#define MT6589_GPIO90__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(90) | 3) +#define MT6589_GPIO90__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(90) | 4) +#define MT6589_GPIO90__FUNC_USB_TEST_IO_7 (MTK_PIN_NO(90) | 5) +#define MT6589_GPIO90__FUNC_USB_DRVVBUS (MTK_PIN_NO(90) | 6) +#define MT6589_GPIO90__FUNC_A_FUNC_DIN_24 (MTK_PIN_NO(90) | 7) + +#define MT6589_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT6589_GPIO91__FUNC_DUAL_BPI1_BUS8 (MTK_PIN_NO(91) | 1) +#define MT6589_GPIO91__FUNC_EINT9 (MTK_PIN_NO(91) | 2) +#define MT6589_GPIO91__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(91) | 3) +#define MT6589_GPIO91__FUNC_USB_TEST_IO_8 (MTK_PIN_NO(91) | 5) +#define MT6589_GPIO91__FUNC_A_FUNC_DIN_23 (MTK_PIN_NO(91) | 7) + +#define MT6589_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT6589_GPIO92__FUNC_DUAL_BPI1_BUS9 (MTK_PIN_NO(92) | 1) +#define MT6589_GPIO92__FUNC_EINT10 (MTK_PIN_NO(92) | 2) +#define MT6589_GPIO92__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(92) | 3) +#define MT6589_GPIO92__FUNC_USB_TEST_IO_9 (MTK_PIN_NO(92) | 5) +#define MT6589_GPIO92__FUNC_A_FUNC_DIN_22 (MTK_PIN_NO(92) | 7) + +#define MT6589_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT6589_GPIO93__FUNC_DUAL_BPI1_BUS10 (MTK_PIN_NO(93) | 1) +#define MT6589_GPIO93__FUNC_EINT11 (MTK_PIN_NO(93) | 2) +#define MT6589_GPIO93__FUNC_USB_TEST_IO_10 (MTK_PIN_NO(93) | 5) +#define MT6589_GPIO93__FUNC_A_FUNC_DIN_21 (MTK_PIN_NO(93) | 7) + +#define MT6589_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT6589_GPIO94__FUNC_DUAL_BPI1_BUS11 (MTK_PIN_NO(94) | 1) +#define MT6589_GPIO94__FUNC_BPI2_BUS11 (MTK_PIN_NO(94) | 3) +#define MT6589_GPIO94__FUNC_USB_TEST_IO_11 (MTK_PIN_NO(94) | 5) +#define MT6589_GPIO94__FUNC_A_FUNC_DOUT_7 (MTK_PIN_NO(94) | 7) + +#define MT6589_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT6589_GPIO95__FUNC_DUAL_BPI1_BUS12 (MTK_PIN_NO(95) | 1) +#define MT6589_GPIO95__FUNC_BPI2_BUS12 (MTK_PIN_NO(95) | 3) +#define MT6589_GPIO95__FUNC_USB_TEST_IO_12 (MTK_PIN_NO(95) | 5) +#define MT6589_GPIO95__FUNC_A_FUNC_DOUT_6 (MTK_PIN_NO(95) | 7) + +#define MT6589_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT6589_GPIO96__FUNC_DUAL_BPI1_BUS13 (MTK_PIN_NO(96) | 1) +#define MT6589_GPIO96__FUNC_BPI2_BUS13 (MTK_PIN_NO(96) | 3) +#define MT6589_GPIO96__FUNC_USB_TEST_IO_13 (MTK_PIN_NO(96) | 5) +#define MT6589_GPIO96__FUNC_A_FUNC_DOUT_5 (MTK_PIN_NO(96) | 7) + +#define MT6589_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT6589_GPIO97__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(97) | 1) +#define MT6589_GPIO97__FUNC_BPI2_BUS16 (MTK_PIN_NO(97) | 3) +#define MT6589_GPIO97__FUNC_USB_TEST_IO_14 (MTK_PIN_NO(97) | 5) +#define MT6589_GPIO97__FUNC_A_FUNC_DOUT_4 (MTK_PIN_NO(97) | 7) + +#define MT6589_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT6589_GPIO98__FUNC_DUAL_BPI1_BUS17 (MTK_PIN_NO(98) | 1) +#define MT6589_GPIO98__FUNC_EINT16 (MTK_PIN_NO(98) | 2) +#define MT6589_GPIO98__FUNC_BPI2_BUS17 (MTK_PIN_NO(98) | 3) +#define MT6589_GPIO98__FUNC_USB_TEST_IO_15 (MTK_PIN_NO(98) | 5) +#define MT6589_GPIO98__FUNC_A_FUNC_DOUT_3 (MTK_PIN_NO(98) | 7) + +#define MT6589_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT6589_GPIO99__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(99) | 1) +#define MT6589_GPIO99__FUNC_EINT17 (MTK_PIN_NO(99) | 2) +#define MT6589_GPIO99__FUNC_BPI2_BUS18 (MTK_PIN_NO(99) | 3) +#define MT6589_GPIO99__FUNC_USB_TEST_IO_16 (MTK_PIN_NO(99) | 5) +#define MT6589_GPIO99__FUNC_A_FUNC_DOUT_2 (MTK_PIN_NO(99) | 7) + +#define MT6589_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT6589_GPIO100__FUNC_VM1 (MTK_PIN_NO(100) | 1) +#define MT6589_GPIO100__FUNC_EINT19 (MTK_PIN_NO(100) | 2) +#define MT6589_GPIO100__FUNC_USB_TEST_IO_17 (MTK_PIN_NO(100) | 5) +#define MT6589_GPIO100__FUNC_A_FUNC_DOUT_0 (MTK_PIN_NO(100) | 7) + +#define MT6589_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT6589_GPIO101__FUNC_VM0 (MTK_PIN_NO(101) | 1) +#define MT6589_GPIO101__FUNC_EINT18 (MTK_PIN_NO(101) | 2) +#define MT6589_GPIO101__FUNC_USB_TEST_IO_18 (MTK_PIN_NO(101) | 5) +#define MT6589_GPIO101__FUNC_A_FUNC_DOUT_1 (MTK_PIN_NO(101) | 7) + +#define MT6589_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT6589_GPIO102__FUNC_BSI1B_CS0 (MTK_PIN_NO(102) | 1) +#define MT6589_GPIO102__FUNC_EINT26 (MTK_PIN_NO(102) | 2) +#define MT6589_GPIO102__FUNC_USB_TEST_IO_19 (MTK_PIN_NO(102) | 5) +#define MT6589_GPIO102__FUNC_MD_ABB_AFUNC_D_21 (MTK_PIN_NO(102) | 6) + +#define MT6589_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT6589_GPIO103__FUNC_BSI1B_DATA0 (MTK_PIN_NO(103) | 1) +#define MT6589_GPIO103__FUNC_EINT27 (MTK_PIN_NO(103) | 2) +#define MT6589_GPIO103__FUNC_USB_TEST_IO_20 (MTK_PIN_NO(103) | 5) +#define MT6589_GPIO103__FUNC_MD_ABB_AFUNC_D_22 (MTK_PIN_NO(103) | 6) + +#define MT6589_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT6589_GPIO104__FUNC_BSI1B_CLK (MTK_PIN_NO(104) | 1) +#define MT6589_GPIO104__FUNC_EINT25 (MTK_PIN_NO(104) | 2) +#define MT6589_GPIO104__FUNC_USB_TEST_IO_21 (MTK_PIN_NO(104) | 5) +#define MT6589_GPIO104__FUNC_MD_ABB_AFUNC_D_23 (MTK_PIN_NO(104) | 6) + +#define MT6589_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT6589_GPIO105__FUNC_TXBPI1 (MTK_PIN_NO(105) | 1) +#define MT6589_GPIO105__FUNC_EINT30 (MTK_PIN_NO(105) | 2) + +#define MT6589_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT6589_GPIO106__FUNC_EXT_CLK_EN (MTK_PIN_NO(106) | 1) + +#define MT6589_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT6589_GPIO107__FUNC_SRCLKENA2 (MTK_PIN_NO(107) | 1) +#define MT6589_GPIO107__FUNC_EINT39 (MTK_PIN_NO(107) | 2) + +#define MT6589_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT6589_GPIO108__FUNC_BSI1A_CS0 (MTK_PIN_NO(108) | 1) +#define MT6589_GPIO108__FUNC_EINT21 (MTK_PIN_NO(108) | 2) +#define MT6589_GPIO108__FUNC_BSI2_CS (MTK_PIN_NO(108) | 3) +#define MT6589_GPIO108__FUNC_USB_TEST_IO_22 (MTK_PIN_NO(108) | 5) +#define MT6589_GPIO108__FUNC_MD_ABB_AFUNC_D_24 (MTK_PIN_NO(108) | 6) + +#define MT6589_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT6589_GPIO109__FUNC_BSI1A_DATA2 (MTK_PIN_NO(109) | 1) +#define MT6589_GPIO109__FUNC_EINT24 (MTK_PIN_NO(109) | 2) +#define MT6589_GPIO109__FUNC_USB_TEST_IO_23 (MTK_PIN_NO(109) | 5) +#define MT6589_GPIO109__FUNC_MD_ABB_AFUNC_D_25 (MTK_PIN_NO(109) | 6) + +#define MT6589_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT6589_GPIO110__FUNC_BSI1A_DATA1 (MTK_PIN_NO(110) | 1) +#define MT6589_GPIO110__FUNC_EINT23 (MTK_PIN_NO(110) | 2) +#define MT6589_GPIO110__FUNC_BSI2_DATA1 (MTK_PIN_NO(110) | 3) +#define MT6589_GPIO110__FUNC_USB_TEST_IO_24 (MTK_PIN_NO(110) | 5) +#define MT6589_GPIO110__FUNC_MD_ABB_AFUNC_D_26 (MTK_PIN_NO(110) | 6) + +#define MT6589_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT6589_GPIO111__FUNC_BSI1A_DATA0 (MTK_PIN_NO(111) | 1) +#define MT6589_GPIO111__FUNC_EINT22 (MTK_PIN_NO(111) | 2) +#define MT6589_GPIO111__FUNC_BSI2_DATA0 (MTK_PIN_NO(111) | 3) +#define MT6589_GPIO111__FUNC_USB_TEST_IO_25 (MTK_PIN_NO(111) | 5) +#define MT6589_GPIO111__FUNC_MD_ABB_AFUNC_D_27 (MTK_PIN_NO(111) | 6) + +#define MT6589_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT6589_GPIO112__FUNC_BSI1A_CLK (MTK_PIN_NO(112) | 1) +#define MT6589_GPIO112__FUNC_EINT20 (MTK_PIN_NO(112) | 2) +#define MT6589_GPIO112__FUNC_BSI2_CLK (MTK_PIN_NO(112) | 3) +#define MT6589_GPIO112__FUNC_USB_TEST_IO_26 (MTK_PIN_NO(112) | 5) +#define MT6589_GPIO112__FUNC_MD_ABB_AFUNC_D_28 (MTK_PIN_NO(112) | 6) + +#define MT6589_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT6589_GPIO113__FUNC_BSI1C_DATA (MTK_PIN_NO(113) | 1) +#define MT6589_GPIO113__FUNC_EINT29 (MTK_PIN_NO(113) | 2) +#define MT6589_GPIO113__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(113) | 3) +#define MT6589_GPIO113__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(113) | 4) +#define MT6589_GPIO113__FUNC_USB_TEST_IO_27 (MTK_PIN_NO(113) | 5) +#define MT6589_GPIO113__FUNC_MD_ABB_AFUNC_D_29 (MTK_PIN_NO(113) | 6) +#define MT6589_GPIO113__FUNC_USB_DRVVBUS (MTK_PIN_NO(113) | 7) + +#define MT6589_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT6589_GPIO114__FUNC_BSI1C_CLK (MTK_PIN_NO(114) | 1) +#define MT6589_GPIO114__FUNC_EINT28 (MTK_PIN_NO(114) | 2) +#define MT6589_GPIO114__FUNC_USB_TEST_IO_28 (MTK_PIN_NO(114) | 5) +#define MT6589_GPIO114__FUNC_MD_ABB_AFUNC_D_30 (MTK_PIN_NO(114) | 6) + +#define MT6589_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT6589_GPIO115__FUNC_EINT10 (MTK_PIN_NO(115) | 1) +#define MT6589_GPIO115__FUNC_MD_ABB_AFUNC_D_31 (MTK_PIN_NO(115) | 6) + +#define MT6589_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT6589_GPIO116__FUNC_EINT11 (MTK_PIN_NO(116) | 1) +#define MT6589_GPIO116__FUNC_MD_ABB_AFUNC_D_32 (MTK_PIN_NO(116) | 6) + +#define MT6589_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT6589_GPIO117__FUNC_EINT16 (MTK_PIN_NO(117) | 1) +#define MT6589_GPIO117__FUNC_MD_ABB_AFUNC_D_33 (MTK_PIN_NO(117) | 6) + +#define MT6589_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT6589_GPIO118__FUNC_SDA0 (MTK_PIN_NO(118) | 1) +#define MT6589_GPIO118__FUNC_EINT91 (MTK_PIN_NO(118) | 2) +#define MT6589_GPIO118__FUNC_CLKM1 (MTK_PIN_NO(118) | 3) +#define MT6589_GPIO118__FUNC_PWM1 (MTK_PIN_NO(118) | 4) +#define MT6589_GPIO118__FUNC_A_FUNC_DIN_19 (MTK_PIN_NO(118) | 7) + +#define MT6589_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT6589_GPIO119__FUNC_SCL0 (MTK_PIN_NO(119) | 1) +#define MT6589_GPIO119__FUNC_EINT90 (MTK_PIN_NO(119) | 2) +#define MT6589_GPIO119__FUNC_CLKM0 (MTK_PIN_NO(119) | 3) +#define MT6589_GPIO119__FUNC_DISP_PWM (MTK_PIN_NO(119) | 4) +#define MT6589_GPIO119__FUNC_A_FUNC_DIN_20 (MTK_PIN_NO(119) | 7) + +#define MT6589_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT6589_GPIO120__FUNC_I2SIN_CK (MTK_PIN_NO(120) | 1) +#define MT6589_GPIO120__FUNC_EINT10 (MTK_PIN_NO(120) | 2) +#define MT6589_GPIO120__FUNC_DAC_CK (MTK_PIN_NO(120) | 3) +#define MT6589_GPIO120__FUNC_PCM1_CK (MTK_PIN_NO(120) | 4) +#define MT6589_GPIO120__FUNC_DSP1_ICK (MTK_PIN_NO(120) | 5) +#define MT6589_GPIO120__FUNC_MD_ABB_AFUNC_D_34 (MTK_PIN_NO(120) | 6) + +#define MT6589_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT6589_GPIO121__FUNC_I2SIN_WS (MTK_PIN_NO(121) | 1) +#define MT6589_GPIO121__FUNC_DAC_WS (MTK_PIN_NO(121) | 3) +#define MT6589_GPIO121__FUNC_PCM1_WS (MTK_PIN_NO(121) | 4) +#define MT6589_GPIO121__FUNC_DSP1_ID (MTK_PIN_NO(121) | 5) +#define MT6589_GPIO121__FUNC_MD_ABB_AFUNC_D_35 (MTK_PIN_NO(121) | 6) + +#define MT6589_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT6589_GPIO122__FUNC_I2SIN_DAT (MTK_PIN_NO(122) | 1) +#define MT6589_GPIO122__FUNC_EINT11 (MTK_PIN_NO(122) | 2) +#define MT6589_GPIO122__FUNC_PCM1_DI (MTK_PIN_NO(122) | 4) +#define MT6589_GPIO122__FUNC_DSP1_IMS (MTK_PIN_NO(122) | 5) +#define MT6589_GPIO122__FUNC_MD_ABB_AFUNC_D_36 (MTK_PIN_NO(122) | 6) + +#define MT6589_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT6589_GPIO123__FUNC_I2SOUT_DAT (MTK_PIN_NO(123) | 1) +#define MT6589_GPIO123__FUNC_DAC_DAT_OUT (MTK_PIN_NO(123) | 3) +#define MT6589_GPIO123__FUNC_PCM1_DO (MTK_PIN_NO(123) | 4) +#define MT6589_GPIO123__FUNC_MD2_EINT5 (MTK_PIN_NO(123) | 5) +#define MT6589_GPIO123__FUNC_MD_ABB_AFUNC_D_37 (MTK_PIN_NO(123) | 6) + +#define MT6589_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT6589_GPIO124__FUNC_EINT5 (MTK_PIN_NO(124) | 1) +#define MT6589_GPIO124__FUNC_PWM5 (MTK_PIN_NO(124) | 2) +#define MT6589_GPIO124__FUNC_CLKM3 (MTK_PIN_NO(124) | 3) +#define MT6589_GPIO124__FUNC_MD1_UTXD (MTK_PIN_NO(124) | 4) +#define MT6589_GPIO124__FUNC_MD2_EINT1 (MTK_PIN_NO(124) | 5) +#define MT6589_GPIO124__FUNC_MD_ABB_AFUNC_D_38 (MTK_PIN_NO(124) | 6) + +#define MT6589_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT6589_GPIO125__FUNC_EINT6 (MTK_PIN_NO(125) | 1) +#define MT6589_GPIO125__FUNC_PWM6 (MTK_PIN_NO(125) | 2) +#define MT6589_GPIO125__FUNC_CLKM4 (MTK_PIN_NO(125) | 3) +#define MT6589_GPIO125__FUNC_MD1_URXD (MTK_PIN_NO(125) | 4) +#define MT6589_GPIO125__FUNC_MD2_EINT2 (MTK_PIN_NO(125) | 5) +#define MT6589_GPIO125__FUNC_MD_ABB_AFUNC_D_39 (MTK_PIN_NO(125) | 6) + +#define MT6589_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT6589_GPIO126__FUNC_EINT7 (MTK_PIN_NO(126) | 1) +#define MT6589_GPIO126__FUNC_PWM7 (MTK_PIN_NO(126) | 2) +#define MT6589_GPIO126__FUNC_CLKM5 (MTK_PIN_NO(126) | 3) +#define MT6589_GPIO126__FUNC_SRCLKENAI2 (MTK_PIN_NO(126) | 4) +#define MT6589_GPIO126__FUNC_MD2_EINT3 (MTK_PIN_NO(126) | 5) +#define MT6589_GPIO126__FUNC_MD_ABB_AFUNC_D_40 (MTK_PIN_NO(126) | 6) + +#define MT6589_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT6589_GPIO127__FUNC_EINT8 (MTK_PIN_NO(127) | 1) +#define MT6589_GPIO127__FUNC_DISP_PWM (MTK_PIN_NO(127) | 2) +#define MT6589_GPIO127__FUNC_CLKM6 (MTK_PIN_NO(127) | 3) +#define MT6589_GPIO127__FUNC_MD2_EINT4 (MTK_PIN_NO(127) | 5) +#define MT6589_GPIO127__FUNC_MD_ABB_AFUNC_D_41 (MTK_PIN_NO(127) | 6) +#define MT6589_GPIO127__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(127) | 7) + +#define MT6589_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT6589_GPIO128__FUNC_EINT9 (MTK_PIN_NO(128) | 1) +#define MT6589_GPIO128__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(128) | 3) +#define MT6589_GPIO128__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(128) | 4) +#define MT6589_GPIO128__FUNC_USB_DRVVBUS (MTK_PIN_NO(128) | 5) +#define MT6589_GPIO128__FUNC_MD_ABB_AFUNC_D_42 (MTK_PIN_NO(128) | 6) + +#define MT6589_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT6589_GPIO129__FUNC_DISP_PWM (MTK_PIN_NO(129) | 1) +#define MT6589_GPIO129__FUNC_EINT77 (MTK_PIN_NO(129) | 2) +#define MT6589_GPIO129__FUNC_LSDI (MTK_PIN_NO(129) | 3) +#define MT6589_GPIO129__FUNC_PWM1 (MTK_PIN_NO(129) | 4) +#define MT6589_GPIO129__FUNC_PWM2 (MTK_PIN_NO(129) | 5) +#define MT6589_GPIO129__FUNC_MD_ABB_AFUNC_D_43 (MTK_PIN_NO(129) | 6) +#define MT6589_GPIO129__FUNC_PWM3 (MTK_PIN_NO(129) | 7) + +#define MT6589_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT6589_GPIO130__FUNC_MSDC4_DAT0 (MTK_PIN_NO(130) | 1) +#define MT6589_GPIO130__FUNC_EINT133 (MTK_PIN_NO(130) | 2) +#define MT6589_GPIO130__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(130) | 4) +#define MT6589_GPIO130__FUNC_USB_DRVVBUS (MTK_PIN_NO(130) | 5) +#define MT6589_GPIO130__FUNC_MD_ABB_AFUNC_D_46 (MTK_PIN_NO(130) | 6) +#define MT6589_GPIO130__FUNC_LPTE (MTK_PIN_NO(130) | 7) + +#define MT6589_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT6589_GPIO131__FUNC_MSDC4_DAT1 (MTK_PIN_NO(131) | 1) +#define MT6589_GPIO131__FUNC_EINT134 (MTK_PIN_NO(131) | 2) +#define MT6589_GPIO131__FUNC_MD_ABB_AFUNC_D_47 (MTK_PIN_NO(131) | 6) +#define MT6589_GPIO131__FUNC_LRSTB_1X (MTK_PIN_NO(131) | 7) + +#define MT6589_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT6589_GPIO132__FUNC_LPCE1B (MTK_PIN_NO(132) | 1) +#define MT6589_GPIO132__FUNC_EINT127 (MTK_PIN_NO(132) | 2) +#define MT6589_GPIO132__FUNC_DPI1_HSYNC_2X (MTK_PIN_NO(132) | 3) +#define MT6589_GPIO132__FUNC_PWM2 (MTK_PIN_NO(132) | 5) +#define MT6589_GPIO132__FUNC_MD_ABB_AFUNC_D_44 (MTK_PIN_NO(132) | 6) + +#define MT6589_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT6589_GPIO133__FUNC_LPCE0B (MTK_PIN_NO(133) | 1) +#define MT6589_GPIO133__FUNC_EINT126 (MTK_PIN_NO(133) | 2) +#define MT6589_GPIO133__FUNC_DPI1_VSYNC_2X (MTK_PIN_NO(133) | 3) +#define MT6589_GPIO133__FUNC_PWM1 (MTK_PIN_NO(133) | 5) +#define MT6589_GPIO133__FUNC_MD_ABB_AFUNC_D_45 (MTK_PIN_NO(133) | 6) + +#define MT6589_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT6589_GPIO134__FUNC_MSDC4_DAT5 (MTK_PIN_NO(134) | 1) +#define MT6589_GPIO134__FUNC_EINT136 (MTK_PIN_NO(134) | 2) +#define MT6589_GPIO134__FUNC_I2SIN_WS (MTK_PIN_NO(134) | 3) +#define MT6589_GPIO134__FUNC_DAC_WS (MTK_PIN_NO(134) | 4) +#define MT6589_GPIO134__FUNC_PCM1_WS (MTK_PIN_NO(134) | 5) +#define MT6589_GPIO134__FUNC_MD_ABB_AFUNC_D_48 (MTK_PIN_NO(134) | 6) +#define MT6589_GPIO134__FUNC_SPI1_CSN (MTK_PIN_NO(134) | 7) + +#define MT6589_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT6589_GPIO135__FUNC_MSDC4_DAT6 (MTK_PIN_NO(135) | 1) +#define MT6589_GPIO135__FUNC_EINT137 (MTK_PIN_NO(135) | 2) +#define MT6589_GPIO135__FUNC_I2SOUT_DAT (MTK_PIN_NO(135) | 3) +#define MT6589_GPIO135__FUNC_DAC_DAT_OUT (MTK_PIN_NO(135) | 4) +#define MT6589_GPIO135__FUNC_PCM1_DO (MTK_PIN_NO(135) | 5) +#define MT6589_GPIO135__FUNC_MD_ABB_AFUNC_D_49 (MTK_PIN_NO(135) | 6) +#define MT6589_GPIO135__FUNC_SPI1_MO (MTK_PIN_NO(135) | 7) + +#define MT6589_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT6589_GPIO136__FUNC_MSDC4_DAT7 (MTK_PIN_NO(136) | 1) +#define MT6589_GPIO136__FUNC_EINT138 (MTK_PIN_NO(136) | 2) +#define MT6589_GPIO136__FUNC_I2SIN_DAT (MTK_PIN_NO(136) | 3) +#define MT6589_GPIO136__FUNC_PCM1_DI (MTK_PIN_NO(136) | 5) +#define MT6589_GPIO136__FUNC_MD_ABB_AFUNC_D_50 (MTK_PIN_NO(136) | 6) +#define MT6589_GPIO136__FUNC_SPI1_MI (MTK_PIN_NO(136) | 7) + +#define MT6589_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT6589_GPIO137__FUNC_MSDC4_DAT4 (MTK_PIN_NO(137) | 1) +#define MT6589_GPIO137__FUNC_EINT135 (MTK_PIN_NO(137) | 2) +#define MT6589_GPIO137__FUNC_I2SIN_CK (MTK_PIN_NO(137) | 3) +#define MT6589_GPIO137__FUNC_DAC_CK (MTK_PIN_NO(137) | 4) +#define MT6589_GPIO137__FUNC_PCM1_CK (MTK_PIN_NO(137) | 5) +#define MT6589_GPIO137__FUNC_MD_ABB_AFUNC_D_51 (MTK_PIN_NO(137) | 6) +#define MT6589_GPIO137__FUNC_SPI1_CLK (MTK_PIN_NO(137) | 7) + +#define MT6589_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT6589_GPIO138__FUNC_MSDC4_DAT2 (MTK_PIN_NO(138) | 1) +#define MT6589_GPIO138__FUNC_EINT131 (MTK_PIN_NO(138) | 2) +#define MT6589_GPIO138__FUNC_I2SIN_WS (MTK_PIN_NO(138) | 3) +#define MT6589_GPIO138__FUNC_CM2PDN_2X (MTK_PIN_NO(138) | 4) +#define MT6589_GPIO138__FUNC_DAC_WS (MTK_PIN_NO(138) | 5) +#define MT6589_GPIO138__FUNC_PCM1_WS (MTK_PIN_NO(138) | 6) +#define MT6589_GPIO138__FUNC_LSCE0B_1X (MTK_PIN_NO(138) | 7) + +#define MT6589_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT6589_GPIO139__FUNC_MSDC4_CLK (MTK_PIN_NO(139) | 1) +#define MT6589_GPIO139__FUNC_EINT129 (MTK_PIN_NO(139) | 2) +#define MT6589_GPIO139__FUNC_DPI1_CK_2X (MTK_PIN_NO(139) | 3) +#define MT6589_GPIO139__FUNC_CM2PCLK_2X (MTK_PIN_NO(139) | 4) +#define MT6589_GPIO139__FUNC_PWM4 (MTK_PIN_NO(139) | 5) +#define MT6589_GPIO139__FUNC_PCM1_DI (MTK_PIN_NO(139) | 6) +#define MT6589_GPIO139__FUNC_LSCK_1X (MTK_PIN_NO(139) | 7) + +#define MT6589_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT6589_GPIO140__FUNC_MSDC4_DAT3 (MTK_PIN_NO(140) | 1) +#define MT6589_GPIO140__FUNC_EINT132 (MTK_PIN_NO(140) | 2) +#define MT6589_GPIO140__FUNC_I2SOUT_DAT (MTK_PIN_NO(140) | 3) +#define MT6589_GPIO140__FUNC_CM2RST_2X (MTK_PIN_NO(140) | 4) +#define MT6589_GPIO140__FUNC_DAC_DAT_OUT (MTK_PIN_NO(140) | 5) +#define MT6589_GPIO140__FUNC_PCM1_DO (MTK_PIN_NO(140) | 6) +#define MT6589_GPIO140__FUNC_LSCE1B_1X (MTK_PIN_NO(140) | 7) + +#define MT6589_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT6589_GPIO141__FUNC_MSDC4_CMD (MTK_PIN_NO(141) | 1) +#define MT6589_GPIO141__FUNC_EINT128 (MTK_PIN_NO(141) | 2) +#define MT6589_GPIO141__FUNC_DPI1_DE_2X (MTK_PIN_NO(141) | 3) +#define MT6589_GPIO141__FUNC_MD1_GPS_SYNC (MTK_PIN_NO(141) | 4) +#define MT6589_GPIO141__FUNC_PWM3 (MTK_PIN_NO(141) | 5) +#define MT6589_GPIO141__FUNC_MD2_GPS_SYNC (MTK_PIN_NO(141) | 6) +#define MT6589_GPIO141__FUNC_LSDA_1X (MTK_PIN_NO(141) | 7) + +#define MT6589_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT6589_GPIO142__FUNC_MSDC4_RSTB (MTK_PIN_NO(142) | 1) +#define MT6589_GPIO142__FUNC_EINT130 (MTK_PIN_NO(142) | 2) +#define MT6589_GPIO142__FUNC_I2SIN_CK (MTK_PIN_NO(142) | 3) +#define MT6589_GPIO142__FUNC_CM2MCLK_2X (MTK_PIN_NO(142) | 4) +#define MT6589_GPIO142__FUNC_DAC_CK (MTK_PIN_NO(142) | 5) +#define MT6589_GPIO142__FUNC_PCM1_CK (MTK_PIN_NO(142) | 6) +#define MT6589_GPIO142__FUNC_LSA0_1X (MTK_PIN_NO(142) | 7) + +#define MT6589_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT6589_GPIO143__FUNC_DPI0_VSYNC (MTK_PIN_NO(143) | 1) +#define MT6589_GPIO143__FUNC_EINT98 (MTK_PIN_NO(143) | 2) +#define MT6589_GPIO143__FUNC_I2SIN_CK (MTK_PIN_NO(143) | 3) +#define MT6589_GPIO143__FUNC_DAC_CK (MTK_PIN_NO(143) | 4) +#define MT6589_GPIO143__FUNC_PCM1_CK (MTK_PIN_NO(143) | 5) +#define MT6589_GPIO143__FUNC_MD_ABB_AFUNC_D_52 (MTK_PIN_NO(143) | 6) +#define MT6589_GPIO143__FUNC_TESTB_OUT8 (MTK_PIN_NO(143) | 7) + +#define MT6589_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT6589_GPIO144__FUNC_DPI0_HSYNC (MTK_PIN_NO(144) | 1) +#define MT6589_GPIO144__FUNC_EINT99 (MTK_PIN_NO(144) | 2) +#define MT6589_GPIO144__FUNC_I2SIN_WS (MTK_PIN_NO(144) | 3) +#define MT6589_GPIO144__FUNC_DAC_WS (MTK_PIN_NO(144) | 4) +#define MT6589_GPIO144__FUNC_PCM1_WS (MTK_PIN_NO(144) | 5) +#define MT6589_GPIO144__FUNC_IRDA_RXD (MTK_PIN_NO(144) | 6) +#define MT6589_GPIO144__FUNC_TESTB_OUT9 (MTK_PIN_NO(144) | 7) + +#define MT6589_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define MT6589_GPIO145__FUNC_DPI0_DE (MTK_PIN_NO(145) | 1) +#define MT6589_GPIO145__FUNC_EINT100 (MTK_PIN_NO(145) | 2) +#define MT6589_GPIO145__FUNC_I2SOUT_DAT (MTK_PIN_NO(145) | 3) +#define MT6589_GPIO145__FUNC_DAC_DAT_OUT (MTK_PIN_NO(145) | 4) +#define MT6589_GPIO145__FUNC_PCM1_DO (MTK_PIN_NO(145) | 5) +#define MT6589_GPIO145__FUNC_IRDA_TXD (MTK_PIN_NO(145) | 6) +#define MT6589_GPIO145__FUNC_TESTB_OUT10 (MTK_PIN_NO(145) | 7) + +#define MT6589_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define MT6589_GPIO146__FUNC_DPI0_CK (MTK_PIN_NO(146) | 1) +#define MT6589_GPIO146__FUNC_EINT101 (MTK_PIN_NO(146) | 2) +#define MT6589_GPIO146__FUNC_I2SIN_DAT (MTK_PIN_NO(146) | 3) +#define MT6589_GPIO146__FUNC_PCM1_DI (MTK_PIN_NO(146) | 5) +#define MT6589_GPIO146__FUNC_IRDA_PDN (MTK_PIN_NO(146) | 6) +#define MT6589_GPIO146__FUNC_TESTB_OUT11 (MTK_PIN_NO(146) | 7) + +#define MT6589_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define MT6589_GPIO147__FUNC_DPI0_B0 (MTK_PIN_NO(147) | 1) +#define MT6589_GPIO147__FUNC_EINT102 (MTK_PIN_NO(147) | 2) +#define MT6589_GPIO147__FUNC_SCL0 (MTK_PIN_NO(147) | 4) +#define MT6589_GPIO147__FUNC_DISP_PWM (MTK_PIN_NO(147) | 5) +#define MT6589_GPIO147__FUNC_MD_ABB_AFUNC_D_57 (MTK_PIN_NO(147) | 6) +#define MT6589_GPIO147__FUNC_TESTB_OUT12 (MTK_PIN_NO(147) | 7) + +#define MT6589_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define MT6589_GPIO148__FUNC_DPI0_B1 (MTK_PIN_NO(148) | 1) +#define MT6589_GPIO148__FUNC_EINT103 (MTK_PIN_NO(148) | 2) +#define MT6589_GPIO148__FUNC_CLKM0 (MTK_PIN_NO(148) | 3) +#define MT6589_GPIO148__FUNC_SDA0 (MTK_PIN_NO(148) | 4) +#define MT6589_GPIO148__FUNC_PWM1 (MTK_PIN_NO(148) | 5) +#define MT6589_GPIO148__FUNC_MD_ABB_AFUNC_D_58 (MTK_PIN_NO(148) | 6) +#define MT6589_GPIO148__FUNC_TESTB_OUT13 (MTK_PIN_NO(148) | 7) + +#define MT6589_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define MT6589_GPIO149__FUNC_DPI0_B2 (MTK_PIN_NO(149) | 1) +#define MT6589_GPIO149__FUNC_EINT104 (MTK_PIN_NO(149) | 2) +#define MT6589_GPIO149__FUNC_CLKM1 (MTK_PIN_NO(149) | 3) +#define MT6589_GPIO149__FUNC_SCL1 (MTK_PIN_NO(149) | 4) +#define MT6589_GPIO149__FUNC_PWM2 (MTK_PIN_NO(149) | 5) +#define MT6589_GPIO149__FUNC_MD_ABB_AFUNC_D_59 (MTK_PIN_NO(149) | 6) +#define MT6589_GPIO149__FUNC_TESTB_OUT14 (MTK_PIN_NO(149) | 7) + +#define MT6589_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define MT6589_GPIO150__FUNC_DPI0_B3 (MTK_PIN_NO(150) | 1) +#define MT6589_GPIO150__FUNC_EINT105 (MTK_PIN_NO(150) | 2) +#define MT6589_GPIO150__FUNC_CLKM2 (MTK_PIN_NO(150) | 3) +#define MT6589_GPIO150__FUNC_SDA1 (MTK_PIN_NO(150) | 4) +#define MT6589_GPIO150__FUNC_PWM3 (MTK_PIN_NO(150) | 5) +#define MT6589_GPIO150__FUNC_MD_ABB_AFUNC_D_60 (MTK_PIN_NO(150) | 6) +#define MT6589_GPIO150__FUNC_TESTB_OUT15 (MTK_PIN_NO(150) | 7) + +#define MT6589_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define MT6589_GPIO151__FUNC_DPI0_B4 (MTK_PIN_NO(151) | 1) +#define MT6589_GPIO151__FUNC_EINT106 (MTK_PIN_NO(151) | 2) +#define MT6589_GPIO151__FUNC_CLKM3 (MTK_PIN_NO(151) | 3) +#define MT6589_GPIO151__FUNC_SCL2 (MTK_PIN_NO(151) | 4) +#define MT6589_GPIO151__FUNC_PWM4 (MTK_PIN_NO(151) | 5) +#define MT6589_GPIO151__FUNC_MD_ABB_AFUNC_D_61 (MTK_PIN_NO(151) | 6) +#define MT6589_GPIO151__FUNC_TESTB_OUT16 (MTK_PIN_NO(151) | 7) + +#define MT6589_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define MT6589_GPIO152__FUNC_DPI0_B5 (MTK_PIN_NO(152) | 1) +#define MT6589_GPIO152__FUNC_EINT107 (MTK_PIN_NO(152) | 2) +#define MT6589_GPIO152__FUNC_CLKM4 (MTK_PIN_NO(152) | 3) +#define MT6589_GPIO152__FUNC_SDA2 (MTK_PIN_NO(152) | 4) +#define MT6589_GPIO152__FUNC_PWM5 (MTK_PIN_NO(152) | 5) +#define MT6589_GPIO152__FUNC_MD_ABB_AFUNC_D_62 (MTK_PIN_NO(152) | 6) +#define MT6589_GPIO152__FUNC_TESTB_OUT17 (MTK_PIN_NO(152) | 7) + +#define MT6589_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define MT6589_GPIO153__FUNC_DPI0_B6 (MTK_PIN_NO(153) | 1) +#define MT6589_GPIO153__FUNC_EINT108 (MTK_PIN_NO(153) | 2) +#define MT6589_GPIO153__FUNC_CLKM5 (MTK_PIN_NO(153) | 3) +#define MT6589_GPIO153__FUNC_SCL3 (MTK_PIN_NO(153) | 4) +#define MT6589_GPIO153__FUNC_PWM6 (MTK_PIN_NO(153) | 5) +#define MT6589_GPIO153__FUNC_MD_ABB_AFUNC_D_63 (MTK_PIN_NO(153) | 6) +#define MT6589_GPIO153__FUNC_TESTB_OUT18 (MTK_PIN_NO(153) | 7) + +#define MT6589_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define MT6589_GPIO154__FUNC_DPI0_B7 (MTK_PIN_NO(154) | 1) +#define MT6589_GPIO154__FUNC_EINT109 (MTK_PIN_NO(154) | 2) +#define MT6589_GPIO154__FUNC_CLKM6 (MTK_PIN_NO(154) | 3) +#define MT6589_GPIO154__FUNC_SDA3 (MTK_PIN_NO(154) | 4) +#define MT6589_GPIO154__FUNC_PWM7 (MTK_PIN_NO(154) | 5) +#define MT6589_GPIO154__FUNC_MD1_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(154) | 6) +#define MT6589_GPIO154__FUNC_TESTB_OUT19 (MTK_PIN_NO(154) | 7) + +#define MT6589_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define MT6589_GPIO155__FUNC_DPI0_G0 (MTK_PIN_NO(155) | 1) +#define MT6589_GPIO155__FUNC_EINT110 (MTK_PIN_NO(155) | 2) +#define MT6589_GPIO155__FUNC_DSP1_ID (MTK_PIN_NO(155) | 5) +#define MT6589_GPIO155__FUNC_MD1_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(155) | 6) +#define MT6589_GPIO155__FUNC_TESTB_OUT20 (MTK_PIN_NO(155) | 7) + +#define MT6589_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define MT6589_GPIO156__FUNC_DPI0_G1 (MTK_PIN_NO(156) | 1) +#define MT6589_GPIO156__FUNC_EINT111 (MTK_PIN_NO(156) | 2) +#define MT6589_GPIO156__FUNC_DSP1_ICK (MTK_PIN_NO(156) | 5) +#define MT6589_GPIO156__FUNC_MD_ABB_AFUNC_D_56 (MTK_PIN_NO(156) | 6) +#define MT6589_GPIO156__FUNC_TESTB_OUT21 (MTK_PIN_NO(156) | 7) + +#define MT6589_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define MT6589_GPIO157__FUNC_DPI0_G2 (MTK_PIN_NO(157) | 1) +#define MT6589_GPIO157__FUNC_EINT112 (MTK_PIN_NO(157) | 2) +#define MT6589_GPIO157__FUNC_DSP1_IMS (MTK_PIN_NO(157) | 5) +#define MT6589_GPIO157__FUNC_MD1_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(157) | 6) +#define MT6589_GPIO157__FUNC_TESTB_OUT22 (MTK_PIN_NO(157) | 7) + +#define MT6589_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define MT6589_GPIO158__FUNC_DPI0_G3 (MTK_PIN_NO(158) | 1) +#define MT6589_GPIO158__FUNC_EINT113 (MTK_PIN_NO(158) | 2) +#define MT6589_GPIO158__FUNC_DSP2_IMS (MTK_PIN_NO(158) | 5) +#define MT6589_GPIO158__FUNC_MD1_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(158) | 6) +#define MT6589_GPIO158__FUNC_TESTB_OUT23 (MTK_PIN_NO(158) | 7) + +#define MT6589_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define MT6589_GPIO159__FUNC_DPI0_G4 (MTK_PIN_NO(159) | 1) +#define MT6589_GPIO159__FUNC_EINT114 (MTK_PIN_NO(159) | 2) +#define MT6589_GPIO159__FUNC_DPI1_D_2X_0 (MTK_PIN_NO(159) | 3) +#define MT6589_GPIO159__FUNC_CM2DAT_2X_0 (MTK_PIN_NO(159) | 4) +#define MT6589_GPIO159__FUNC_DSP2_ID (MTK_PIN_NO(159) | 5) +#define MT6589_GPIO159__FUNC_MD_ABB_AFUNC_D_53 (MTK_PIN_NO(159) | 6) +#define MT6589_GPIO159__FUNC_TESTB_OUT24 (MTK_PIN_NO(159) | 7) + +#define MT6589_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define MT6589_GPIO160__FUNC_DPI0_G5 (MTK_PIN_NO(160) | 1) +#define MT6589_GPIO160__FUNC_EINT115 (MTK_PIN_NO(160) | 2) +#define MT6589_GPIO160__FUNC_DPI1_D_2X_1 (MTK_PIN_NO(160) | 3) +#define MT6589_GPIO160__FUNC_CM2DAT_2X_1 (MTK_PIN_NO(160) | 4) +#define MT6589_GPIO160__FUNC_DSP2_ICK (MTK_PIN_NO(160) | 5) +#define MT6589_GPIO160__FUNC_MD_ABB_AFUNC_D_54 (MTK_PIN_NO(160) | 6) +#define MT6589_GPIO160__FUNC_TESTB_OUT25 (MTK_PIN_NO(160) | 7) + +#define MT6589_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define MT6589_GPIO161__FUNC_DPI0_G6 (MTK_PIN_NO(161) | 1) +#define MT6589_GPIO161__FUNC_EINT116 (MTK_PIN_NO(161) | 2) +#define MT6589_GPIO161__FUNC_DPI1_D_2X_2 (MTK_PIN_NO(161) | 3) +#define MT6589_GPIO161__FUNC_CM2DAT_2X_2 (MTK_PIN_NO(161) | 4) +#define MT6589_GPIO161__FUNC_MD2_RTCK_PAD (MTK_PIN_NO(161) | 5) +#define MT6589_GPIO161__FUNC_MD1_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(161) | 6) +#define MT6589_GPIO161__FUNC_TESTB_OUT26 (MTK_PIN_NO(161) | 7) + +#define MT6589_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define MT6589_GPIO162__FUNC_DPI0_G7 (MTK_PIN_NO(162) | 1) +#define MT6589_GPIO162__FUNC_EINT117 (MTK_PIN_NO(162) | 2) +#define MT6589_GPIO162__FUNC_DPI1_D_2X_3 (MTK_PIN_NO(162) | 3) +#define MT6589_GPIO162__FUNC_CM2DAT_2X_3 (MTK_PIN_NO(162) | 4) +#define MT6589_GPIO162__FUNC_MD2_TCK_PAD (MTK_PIN_NO(162) | 5) +#define MT6589_GPIO162__FUNC_MD1_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(162) | 6) +#define MT6589_GPIO162__FUNC_TESTB_OUT27 (MTK_PIN_NO(162) | 7) + +#define MT6589_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define MT6589_GPIO163__FUNC_DPI0_R0 (MTK_PIN_NO(163) | 1) +#define MT6589_GPIO163__FUNC_EINT118 (MTK_PIN_NO(163) | 2) +#define MT6589_GPIO163__FUNC_DPI1_D_2X_4 (MTK_PIN_NO(163) | 3) +#define MT6589_GPIO163__FUNC_CM2DAT_2X_4 (MTK_PIN_NO(163) | 4) +#define MT6589_GPIO163__FUNC_MD2_TDI_PAD (MTK_PIN_NO(163) | 5) +#define MT6589_GPIO163__FUNC_MD1_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(163) | 6) +#define MT6589_GPIO163__FUNC_TESTB_OUT28 (MTK_PIN_NO(163) | 7) + +#define MT6589_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define MT6589_GPIO164__FUNC_DPI0_R1 (MTK_PIN_NO(164) | 1) +#define MT6589_GPIO164__FUNC_EINT119 (MTK_PIN_NO(164) | 2) +#define MT6589_GPIO164__FUNC_DPI1_D_2X_5 (MTK_PIN_NO(164) | 3) +#define MT6589_GPIO164__FUNC_CM2DAT_2X_5 (MTK_PIN_NO(164) | 4) +#define MT6589_GPIO164__FUNC_MD2_TDO_PAD (MTK_PIN_NO(164) | 5) +#define MT6589_GPIO164__FUNC_MD1_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(164) | 6) +#define MT6589_GPIO164__FUNC_TESTB_OUT29 (MTK_PIN_NO(164) | 7) + +#define MT6589_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define MT6589_GPIO165__FUNC_DPI0_R2 (MTK_PIN_NO(165) | 1) +#define MT6589_GPIO165__FUNC_EINT120 (MTK_PIN_NO(165) | 2) +#define MT6589_GPIO165__FUNC_DPI1_D_2X_6 (MTK_PIN_NO(165) | 3) +#define MT6589_GPIO165__FUNC_CM2DAT_2X_6 (MTK_PIN_NO(165) | 4) +#define MT6589_GPIO165__FUNC_MD2_TMS_PAD (MTK_PIN_NO(165) | 5) +#define MT6589_GPIO165__FUNC_TESTB_OUT30 (MTK_PIN_NO(165) | 7) + +#define MT6589_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define MT6589_GPIO166__FUNC_DPI0_R3 (MTK_PIN_NO(166) | 1) +#define MT6589_GPIO166__FUNC_EINT121 (MTK_PIN_NO(166) | 2) +#define MT6589_GPIO166__FUNC_DPI1_D_2X_7 (MTK_PIN_NO(166) | 3) +#define MT6589_GPIO166__FUNC_CM2DAT_2X_7 (MTK_PIN_NO(166) | 4) +#define MT6589_GPIO166__FUNC_MD2_NTRST_PAD (MTK_PIN_NO(166) | 5) +#define MT6589_GPIO166__FUNC_MD_ABB_AFUNC_D_55 (MTK_PIN_NO(166) | 6) +#define MT6589_GPIO166__FUNC_TESTB_OUT31 (MTK_PIN_NO(166) | 7) + +#define MT6589_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define MT6589_GPIO167__FUNC_DPI0_R4 (MTK_PIN_NO(167) | 1) +#define MT6589_GPIO167__FUNC_EINT122 (MTK_PIN_NO(167) | 2) +#define MT6589_GPIO167__FUNC_DPI1_D_2X_8 (MTK_PIN_NO(167) | 3) +#define MT6589_GPIO167__FUNC_CM2DAT_2X_8 (MTK_PIN_NO(167) | 4) +#define MT6589_GPIO167__FUNC_TESTA_OUT0 (MTK_PIN_NO(167) | 7) + +#define MT6589_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define MT6589_GPIO168__FUNC_DPI0_R5 (MTK_PIN_NO(168) | 1) +#define MT6589_GPIO168__FUNC_EINT123 (MTK_PIN_NO(168) | 2) +#define MT6589_GPIO168__FUNC_DPI1_D_2X_9 (MTK_PIN_NO(168) | 3) +#define MT6589_GPIO168__FUNC_CM2DAT_2X_9 (MTK_PIN_NO(168) | 4) +#define MT6589_GPIO168__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(168) | 5) +#define MT6589_GPIO168__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(168) | 6) +#define MT6589_GPIO168__FUNC_TESTA_OUT1 (MTK_PIN_NO(168) | 7) + +#define MT6589_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define MT6589_GPIO169__FUNC_DPI0_R6 (MTK_PIN_NO(169) | 1) +#define MT6589_GPIO169__FUNC_EINT124 (MTK_PIN_NO(169) | 2) +#define MT6589_GPIO169__FUNC_DPI1_D_2X_10 (MTK_PIN_NO(169) | 3) +#define MT6589_GPIO169__FUNC_CM2VSYNC_2X (MTK_PIN_NO(169) | 4) +#define MT6589_GPIO169__FUNC_TESTA_OUT2 (MTK_PIN_NO(169) | 7) + +#define MT6589_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define MT6589_GPIO170__FUNC_DPI0_R7 (MTK_PIN_NO(170) | 1) +#define MT6589_GPIO170__FUNC_EINT125 (MTK_PIN_NO(170) | 2) +#define MT6589_GPIO170__FUNC_DPI1_D_2X_11 (MTK_PIN_NO(170) | 3) +#define MT6589_GPIO170__FUNC_CM2HSYNC_2X (MTK_PIN_NO(170) | 4) +#define MT6589_GPIO170__FUNC_TESTA_OUT3 (MTK_PIN_NO(170) | 7) + +#define MT6589_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define MT6589_GPIO171__FUNC_MSDC1_INSI (MTK_PIN_NO(171) | 1) +#define MT6589_GPIO171__FUNC_EINT57 (MTK_PIN_NO(171) | 2) +#define MT6589_GPIO171__FUNC_SCL5 (MTK_PIN_NO(171) | 3) +#define MT6589_GPIO171__FUNC_PWM6 (MTK_PIN_NO(171) | 4) +#define MT6589_GPIO171__FUNC_CLKM5 (MTK_PIN_NO(171) | 5) +#define MT6589_GPIO171__FUNC_MD2_PLL_A_FUNC_DOUT_0 (MTK_PIN_NO(171) | 6) +#define MT6589_GPIO171__FUNC_TESTB_OUT6 (MTK_PIN_NO(171) | 7) + +#define MT6589_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define MT6589_GPIO172__FUNC_MSDC2_INSI (MTK_PIN_NO(172) | 1) +#define MT6589_GPIO172__FUNC_EINT65 (MTK_PIN_NO(172) | 2) +#define MT6589_GPIO172__FUNC_BPI2_BUS6 (MTK_PIN_NO(172) | 3) +#define MT6589_GPIO172__FUNC_A_FUNC_DIN_6 (MTK_PIN_NO(172) | 7) + +#define MT6589_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define MT6589_GPIO173__FUNC_MSDC2_SDWPI (MTK_PIN_NO(173) | 1) +#define MT6589_GPIO173__FUNC_EINT66 (MTK_PIN_NO(173) | 2) +#define MT6589_GPIO173__FUNC_BPI2_BUS17 (MTK_PIN_NO(173) | 3) +#define MT6589_GPIO173__FUNC_DUAL_BPI1_BUS14 (MTK_PIN_NO(173) | 4) +#define MT6589_GPIO173__FUNC_DUAL_BPI1_BUS15 (MTK_PIN_NO(173) | 5) +#define MT6589_GPIO173__FUNC_A_FUNC_DIN_5 (MTK_PIN_NO(173) | 7) + +#define MT6589_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define MT6589_GPIO174__FUNC_MSDC2_DAT2 (MTK_PIN_NO(174) | 1) +#define MT6589_GPIO174__FUNC_EINT63 (MTK_PIN_NO(174) | 2) +#define MT6589_GPIO174__FUNC_BPI2_BUS4 (MTK_PIN_NO(174) | 3) +#define MT6589_GPIO174__FUNC_DSP2_IMS (MTK_PIN_NO(174) | 4) +#define MT6589_GPIO174__FUNC_A_FUNC_DIN_8 (MTK_PIN_NO(174) | 7) + +#define MT6589_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define MT6589_GPIO175__FUNC_MSDC2_DAT3 (MTK_PIN_NO(175) | 1) +#define MT6589_GPIO175__FUNC_EINT64 (MTK_PIN_NO(175) | 2) +#define MT6589_GPIO175__FUNC_BPI2_BUS5 (MTK_PIN_NO(175) | 3) +#define MT6589_GPIO175__FUNC_DSP2_ID (MTK_PIN_NO(175) | 4) +#define MT6589_GPIO175__FUNC_A_FUNC_DIN_7 (MTK_PIN_NO(175) | 7) + +#define MT6589_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define MT6589_GPIO176__FUNC_MSDC2_CMD (MTK_PIN_NO(176) | 1) +#define MT6589_GPIO176__FUNC_EINT60 (MTK_PIN_NO(176) | 2) +#define MT6589_GPIO176__FUNC_BPI2_BUS1 (MTK_PIN_NO(176) | 3) +#define MT6589_GPIO176__FUNC_DSP1_IMS (MTK_PIN_NO(176) | 4) +#define MT6589_GPIO176__FUNC_PCM1_WS (MTK_PIN_NO(176) | 5) +#define MT6589_GPIO176__FUNC_A_FUNC_DIN_11 (MTK_PIN_NO(176) | 7) + +#define MT6589_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define MT6589_GPIO177__FUNC_MSDC2_CLK (MTK_PIN_NO(177) | 1) +#define MT6589_GPIO177__FUNC_EINT59 (MTK_PIN_NO(177) | 2) +#define MT6589_GPIO177__FUNC_BPI2_BUS0 (MTK_PIN_NO(177) | 3) +#define MT6589_GPIO177__FUNC_DSP1_ICK (MTK_PIN_NO(177) | 4) +#define MT6589_GPIO177__FUNC_PCM1_CK (MTK_PIN_NO(177) | 5) +#define MT6589_GPIO177__FUNC_A_FUNC_DIN_12 (MTK_PIN_NO(177) | 7) + +#define MT6589_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define MT6589_GPIO178__FUNC_MSDC2_DAT1 (MTK_PIN_NO(178) | 1) +#define MT6589_GPIO178__FUNC_EINT62 (MTK_PIN_NO(178) | 2) +#define MT6589_GPIO178__FUNC_BPI2_BUS3 (MTK_PIN_NO(178) | 3) +#define MT6589_GPIO178__FUNC_DSP2_ICK (MTK_PIN_NO(178) | 4) +#define MT6589_GPIO178__FUNC_PCM1_DO (MTK_PIN_NO(178) | 5) +#define MT6589_GPIO178__FUNC_A_FUNC_DIN_9 (MTK_PIN_NO(178) | 7) + +#define MT6589_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define MT6589_GPIO179__FUNC_MSDC2_DAT0 (MTK_PIN_NO(179) | 1) +#define MT6589_GPIO179__FUNC_EINT61 (MTK_PIN_NO(179) | 2) +#define MT6589_GPIO179__FUNC_BPI2_BUS2 (MTK_PIN_NO(179) | 3) +#define MT6589_GPIO179__FUNC_DSP1_ID (MTK_PIN_NO(179) | 4) +#define MT6589_GPIO179__FUNC_PCM1_DI (MTK_PIN_NO(179) | 5) +#define MT6589_GPIO179__FUNC_A_FUNC_DIN_10 (MTK_PIN_NO(179) | 7) + +#define MT6589_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define MT6589_GPIO180__FUNC_MSDC1_DAT0 (MTK_PIN_NO(180) | 1) +#define MT6589_GPIO180__FUNC_EINT53 (MTK_PIN_NO(180) | 2) +#define MT6589_GPIO180__FUNC_SCL1 (MTK_PIN_NO(180) | 3) +#define MT6589_GPIO180__FUNC_PWM2 (MTK_PIN_NO(180) | 4) +#define MT6589_GPIO180__FUNC_CLKM1 (MTK_PIN_NO(180) | 5) +#define MT6589_GPIO180__FUNC_MD2_PLL_A_FUNC_DOUT_1 (MTK_PIN_NO(180) | 6) +#define MT6589_GPIO180__FUNC_TESTB_OUT2 (MTK_PIN_NO(180) | 7) + +#define MT6589_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define MT6589_GPIO181__FUNC_MSDC1_DAT1 (MTK_PIN_NO(181) | 1) +#define MT6589_GPIO181__FUNC_EINT54 (MTK_PIN_NO(181) | 2) +#define MT6589_GPIO181__FUNC_SDA1 (MTK_PIN_NO(181) | 3) +#define MT6589_GPIO181__FUNC_PWM3 (MTK_PIN_NO(181) | 4) +#define MT6589_GPIO181__FUNC_CLKM2 (MTK_PIN_NO(181) | 5) +#define MT6589_GPIO181__FUNC_MD2_PLL_A_FUNC_DOUT_2 (MTK_PIN_NO(181) | 6) +#define MT6589_GPIO181__FUNC_TESTB_OUT3 (MTK_PIN_NO(181) | 7) + +#define MT6589_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define MT6589_GPIO182__FUNC_MSDC1_SDWPI (MTK_PIN_NO(182) | 1) +#define MT6589_GPIO182__FUNC_EINT58 (MTK_PIN_NO(182) | 2) +#define MT6589_GPIO182__FUNC_SDA5 (MTK_PIN_NO(182) | 3) +#define MT6589_GPIO182__FUNC_PWM7 (MTK_PIN_NO(182) | 4) +#define MT6589_GPIO182__FUNC_CLKM6 (MTK_PIN_NO(182) | 5) +#define MT6589_GPIO182__FUNC_MD2_PLL_A_FUNC_DOUT_3 (MTK_PIN_NO(182) | 6) +#define MT6589_GPIO182__FUNC_TESTB_OUT7 (MTK_PIN_NO(182) | 7) + +#define MT6589_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define MT6589_GPIO183__FUNC_MSDC1_CMD (MTK_PIN_NO(183) | 1) +#define MT6589_GPIO183__FUNC_EINT52 (MTK_PIN_NO(183) | 2) +#define MT6589_GPIO183__FUNC_SDA0 (MTK_PIN_NO(183) | 3) +#define MT6589_GPIO183__FUNC_PWM1 (MTK_PIN_NO(183) | 4) +#define MT6589_GPIO183__FUNC_CLKM0 (MTK_PIN_NO(183) | 5) +#define MT6589_GPIO183__FUNC_MD2_PLL_A_FUNC_DOUT_4 (MTK_PIN_NO(183) | 6) +#define MT6589_GPIO183__FUNC_TESTB_OUT1 (MTK_PIN_NO(183) | 7) + +#define MT6589_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define MT6589_GPIO184__FUNC_MSDC1_CLK (MTK_PIN_NO(184) | 1) +#define MT6589_GPIO184__FUNC_EINT51 (MTK_PIN_NO(184) | 2) +#define MT6589_GPIO184__FUNC_SCL0 (MTK_PIN_NO(184) | 3) +#define MT6589_GPIO184__FUNC_DISP_PWM (MTK_PIN_NO(184) | 4) +#define MT6589_GPIO184__FUNC_MD2_PLL_A_FUNC_DOUT_5 (MTK_PIN_NO(184) | 6) +#define MT6589_GPIO184__FUNC_TESTB_OUT0 (MTK_PIN_NO(184) | 7) + +#define MT6589_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define MT6589_GPIO185__FUNC_MSDC1_DAT2 (MTK_PIN_NO(185) | 1) +#define MT6589_GPIO185__FUNC_EINT55 (MTK_PIN_NO(185) | 2) +#define MT6589_GPIO185__FUNC_SCL4 (MTK_PIN_NO(185) | 3) +#define MT6589_GPIO185__FUNC_PWM4 (MTK_PIN_NO(185) | 4) +#define MT6589_GPIO185__FUNC_CLKM3 (MTK_PIN_NO(185) | 5) +#define MT6589_GPIO185__FUNC_MD2_PLL_A_FUNC_DOUT_6 (MTK_PIN_NO(185) | 6) +#define MT6589_GPIO185__FUNC_TESTB_OUT4 (MTK_PIN_NO(185) | 7) + +#define MT6589_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define MT6589_GPIO186__FUNC_MSDC1_DAT3 (MTK_PIN_NO(186) | 1) +#define MT6589_GPIO186__FUNC_EINT56 (MTK_PIN_NO(186) | 2) +#define MT6589_GPIO186__FUNC_SDA4 (MTK_PIN_NO(186) | 3) +#define MT6589_GPIO186__FUNC_PWM5 (MTK_PIN_NO(186) | 4) +#define MT6589_GPIO186__FUNC_CLKM4 (MTK_PIN_NO(186) | 5) +#define MT6589_GPIO186__FUNC_MD2_PLL_A_FUNC_DOUT_7 (MTK_PIN_NO(186) | 6) +#define MT6589_GPIO186__FUNC_TESTB_OUT5 (MTK_PIN_NO(186) | 7) + +#define MT6589_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define MT6589_GPIO187__FUNC_EINT36 (MTK_PIN_NO(187) | 2) + +#define MT6589_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define MT6589_GPIO188__FUNC_EINT35 (MTK_PIN_NO(188) | 2) + +#define MT6589_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define MT6589_GPIO189__FUNC_EINT169 (MTK_PIN_NO(189) | 2) + +#define MT6589_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define MT6589_GPIO190__FUNC_EINT168 (MTK_PIN_NO(190) | 2) + +#define MT6589_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define MT6589_GPIO191__FUNC_EINT163 (MTK_PIN_NO(191) | 2) + +#define MT6589_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define MT6589_GPIO192__FUNC_EINT162 (MTK_PIN_NO(192) | 2) + +#define MT6589_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define MT6589_GPIO193__FUNC_EINT167 (MTK_PIN_NO(193) | 2) + +#define MT6589_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define MT6589_GPIO194__FUNC_EINT166 (MTK_PIN_NO(194) | 2) + +#define MT6589_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define MT6589_GPIO195__FUNC_EINT165 (MTK_PIN_NO(195) | 2) + +#define MT6589_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define MT6589_GPIO196__FUNC_EINT164 (MTK_PIN_NO(196) | 2) + +#define MT6589_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define MT6589_GPIO197__FUNC_CMDAT6 (MTK_PIN_NO(197) | 1) +#define MT6589_GPIO197__FUNC_EINT175 (MTK_PIN_NO(197) | 2) + +#define MT6589_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define MT6589_GPIO198__FUNC_CMDAT7 (MTK_PIN_NO(198) | 1) +#define MT6589_GPIO198__FUNC_EINT174 (MTK_PIN_NO(198) | 2) + +#define MT6589_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define MT6589_GPIO199__FUNC_CMDAT8 (MTK_PIN_NO(199) | 1) +#define MT6589_GPIO199__FUNC_EINT171 (MTK_PIN_NO(199) | 2) + +#define MT6589_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define MT6589_GPIO200__FUNC_CMDAT9 (MTK_PIN_NO(200) | 1) +#define MT6589_GPIO200__FUNC_EINT170 (MTK_PIN_NO(200) | 2) + +#define MT6589_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define MT6589_GPIO201__FUNC_CMHSYNC (MTK_PIN_NO(201) | 1) +#define MT6589_GPIO201__FUNC_EINT173 (MTK_PIN_NO(201) | 2) + +#define MT6589_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define MT6589_GPIO202__FUNC_CMVSYNC (MTK_PIN_NO(202) | 1) +#define MT6589_GPIO202__FUNC_EINT172 (MTK_PIN_NO(202) | 2) + +#define MT6589_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define MT6589_GPIO203__FUNC_CMDAT2 (MTK_PIN_NO(203) | 1) +#define MT6589_GPIO203__FUNC_EINT181 (MTK_PIN_NO(203) | 2) +#define MT6589_GPIO203__FUNC_CMCSD2 (MTK_PIN_NO(203) | 3) + +#define MT6589_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define MT6589_GPIO204__FUNC_CMDAT3 (MTK_PIN_NO(204) | 1) +#define MT6589_GPIO204__FUNC_EINT180 (MTK_PIN_NO(204) | 2) +#define MT6589_GPIO204__FUNC_CMCSD3 (MTK_PIN_NO(204) | 3) + +#define MT6589_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define MT6589_GPIO205__FUNC_CMDAT4 (MTK_PIN_NO(205) | 1) +#define MT6589_GPIO205__FUNC_EINT177 (MTK_PIN_NO(205) | 2) + +#define MT6589_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define MT6589_GPIO206__FUNC_CMDAT5 (MTK_PIN_NO(206) | 1) +#define MT6589_GPIO206__FUNC_EINT176 (MTK_PIN_NO(206) | 2) + +#define MT6589_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define MT6589_GPIO207__FUNC_CMDAT0 (MTK_PIN_NO(207) | 1) +#define MT6589_GPIO207__FUNC_EINT179 (MTK_PIN_NO(207) | 2) +#define MT6589_GPIO207__FUNC_CMCSD0 (MTK_PIN_NO(207) | 3) + +#define MT6589_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define MT6589_GPIO208__FUNC_CMDAT1 (MTK_PIN_NO(208) | 1) +#define MT6589_GPIO208__FUNC_EINT178 (MTK_PIN_NO(208) | 2) +#define MT6589_GPIO208__FUNC_CMCSD1 (MTK_PIN_NO(208) | 3) + +#define MT6589_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define MT6589_GPIO209__FUNC_CMPCLK (MTK_PIN_NO(209) | 1) +#define MT6589_GPIO209__FUNC_EINT182 (MTK_PIN_NO(209) | 2) +#define MT6589_GPIO209__FUNC_CMCSK (MTK_PIN_NO(209) | 3) +#define MT6589_GPIO209__FUNC_CM2MCLK_4X (MTK_PIN_NO(209) | 4) +#define MT6589_GPIO209__FUNC_TS_AUXADC_SEL_3 (MTK_PIN_NO(209) | 5) +#define MT6589_GPIO209__FUNC_TESTA_OUT27 (MTK_PIN_NO(209) | 7) + +#define MT6589_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define MT6589_GPIO210__FUNC_CMMCLK (MTK_PIN_NO(210) | 1) +#define MT6589_GPIO210__FUNC_EINT183 (MTK_PIN_NO(210) | 2) +#define MT6589_GPIO210__FUNC_TS_AUXADC_SEL_2 (MTK_PIN_NO(210) | 5) +#define MT6589_GPIO210__FUNC_TESTA_OUT28 (MTK_PIN_NO(210) | 7) + +#define MT6589_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define MT6589_GPIO211__FUNC_CMRST (MTK_PIN_NO(211) | 1) +#define MT6589_GPIO211__FUNC_EINT185 (MTK_PIN_NO(211) | 2) +#define MT6589_GPIO211__FUNC_TS_AUXADC_SEL_1 (MTK_PIN_NO(211) | 5) +#define MT6589_GPIO211__FUNC_TESTA_OUT30 (MTK_PIN_NO(211) | 7) + +#define MT6589_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define MT6589_GPIO212__FUNC_CMPDN (MTK_PIN_NO(212) | 1) +#define MT6589_GPIO212__FUNC_EINT184 (MTK_PIN_NO(212) | 2) +#define MT6589_GPIO212__FUNC_TS_AUXADC_SEL_0 (MTK_PIN_NO(212) | 5) +#define MT6589_GPIO212__FUNC_TESTA_OUT29 (MTK_PIN_NO(212) | 7) + +#define MT6589_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define MT6589_GPIO213__FUNC_CMFLASH (MTK_PIN_NO(213) | 1) +#define MT6589_GPIO213__FUNC_EINT186 (MTK_PIN_NO(213) | 2) +#define MT6589_GPIO213__FUNC_CM2MCLK_3X (MTK_PIN_NO(213) | 3) +#define MT6589_GPIO213__FUNC_TESTA_OUT31 (MTK_PIN_NO(213) | 7) + +#define MT6589_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define MT6589_GPIO214__FUNC_SDA1 (MTK_PIN_NO(214) | 1) +#define MT6589_GPIO214__FUNC_EINT93 (MTK_PIN_NO(214) | 2) +#define MT6589_GPIO214__FUNC_CLKM3 (MTK_PIN_NO(214) | 3) +#define MT6589_GPIO214__FUNC_PWM3 (MTK_PIN_NO(214) | 4) +#define MT6589_GPIO214__FUNC_TS_AUX_SCLK_PWDB (MTK_PIN_NO(214) | 5) +#define MT6589_GPIO214__FUNC_A_FUNC_DIN_17 (MTK_PIN_NO(214) | 7) + +#define MT6589_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define MT6589_GPIO215__FUNC_SCL1 (MTK_PIN_NO(215) | 1) +#define MT6589_GPIO215__FUNC_EINT92 (MTK_PIN_NO(215) | 2) +#define MT6589_GPIO215__FUNC_CLKM2 (MTK_PIN_NO(215) | 3) +#define MT6589_GPIO215__FUNC_PWM2 (MTK_PIN_NO(215) | 4) +#define MT6589_GPIO215__FUNC_TS_AUX_DIN (MTK_PIN_NO(215) | 5) +#define MT6589_GPIO215__FUNC_A_FUNC_DIN_18 (MTK_PIN_NO(215) | 7) + +#define MT6589_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define MT6589_GPIO216__FUNC_SDA2 (MTK_PIN_NO(216) | 1) +#define MT6589_GPIO216__FUNC_EINT95 (MTK_PIN_NO(216) | 2) +#define MT6589_GPIO216__FUNC_CLKM5 (MTK_PIN_NO(216) | 3) +#define MT6589_GPIO216__FUNC_PWM5 (MTK_PIN_NO(216) | 4) +#define MT6589_GPIO216__FUNC_TS_AUX_PWDB (MTK_PIN_NO(216) | 5) +#define MT6589_GPIO216__FUNC_A_FUNC_DIN_15 (MTK_PIN_NO(216) | 7) + +#define MT6589_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define MT6589_GPIO217__FUNC_SCL2 (MTK_PIN_NO(217) | 1) +#define MT6589_GPIO217__FUNC_EINT94 (MTK_PIN_NO(217) | 2) +#define MT6589_GPIO217__FUNC_CLKM4 (MTK_PIN_NO(217) | 3) +#define MT6589_GPIO217__FUNC_PWM4 (MTK_PIN_NO(217) | 4) +#define MT6589_GPIO217__FUNC_TS_AUXADC_TEST_CK (MTK_PIN_NO(217) | 5) +#define MT6589_GPIO217__FUNC_A_FUNC_DIN_16 (MTK_PIN_NO(217) | 7) + +#define MT6589_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define MT6589_GPIO218__FUNC_SRCLKENAI (MTK_PIN_NO(218) | 1) + +#define MT6589_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define MT6589_GPIO219__FUNC_URXD3 (MTK_PIN_NO(219) | 1) +#define MT6589_GPIO219__FUNC_EINT87 (MTK_PIN_NO(219) | 2) +#define MT6589_GPIO219__FUNC_UTXD3 (MTK_PIN_NO(219) | 3) +#define MT6589_GPIO219__FUNC_MD2_URXD (MTK_PIN_NO(219) | 4) +#define MT6589_GPIO219__FUNC_TS_AUX_ST (MTK_PIN_NO(219) | 5) +#define MT6589_GPIO219__FUNC_PWM4 (MTK_PIN_NO(219) | 6) +#define MT6589_GPIO219__FUNC_MD2_EINT4 (MTK_PIN_NO(219) | 7) + +#define MT6589_GPIO220__FUNC_GPIO220 (MTK_PIN_NO(220) | 0) +#define MT6589_GPIO220__FUNC_UTXD3 (MTK_PIN_NO(220) | 1) +#define MT6589_GPIO220__FUNC_EINT86 (MTK_PIN_NO(220) | 2) +#define MT6589_GPIO220__FUNC_URXD3 (MTK_PIN_NO(220) | 3) +#define MT6589_GPIO220__FUNC_MD2_UTXD (MTK_PIN_NO(220) | 4) +#define MT6589_GPIO220__FUNC_TS_AUX_CS_B (MTK_PIN_NO(220) | 5) +#define MT6589_GPIO220__FUNC_PWM3 (MTK_PIN_NO(220) | 6) +#define MT6589_GPIO220__FUNC_MD2_EINT3 (MTK_PIN_NO(220) | 7) + +#define MT6589_GPIO221__FUNC_GPIO221 (MTK_PIN_NO(221) | 0) +#define MT6589_GPIO221__FUNC_MRG_I2S_PCM_CLK (MTK_PIN_NO(221) | 1) +#define MT6589_GPIO221__FUNC_I2SIN_CK (MTK_PIN_NO(221) | 3) +#define MT6589_GPIO221__FUNC_PCM0_CK (MTK_PIN_NO(221) | 4) +#define MT6589_GPIO221__FUNC_DSP2_ICK (MTK_PIN_NO(221) | 5) +#define MT6589_GPIO221__FUNC_IMG_TEST_CK (MTK_PIN_NO(221) | 6) +#define MT6589_GPIO221__FUNC_USB_SCL (MTK_PIN_NO(221) | 7) + +#define MT6589_GPIO222__FUNC_GPIO222 (MTK_PIN_NO(222) | 0) +#define MT6589_GPIO222__FUNC_MRG_I2S_PCM_SYNC (MTK_PIN_NO(222) | 1) +#define MT6589_GPIO222__FUNC_EINT16 (MTK_PIN_NO(222) | 2) +#define MT6589_GPIO222__FUNC_I2SIN_WS (MTK_PIN_NO(222) | 3) +#define MT6589_GPIO222__FUNC_PCM0_WS (MTK_PIN_NO(222) | 4) +#define MT6589_GPIO222__FUNC_DISP_TEST_CK (MTK_PIN_NO(222) | 6) + +#define MT6589_GPIO223__FUNC_GPIO223 (MTK_PIN_NO(223) | 0) +#define MT6589_GPIO223__FUNC_MRG_I2S_PCM_RX (MTK_PIN_NO(223) | 1) +#define MT6589_GPIO223__FUNC_I2SIN_DAT (MTK_PIN_NO(223) | 3) +#define MT6589_GPIO223__FUNC_PCM0_DI (MTK_PIN_NO(223) | 4) +#define MT6589_GPIO223__FUNC_DSP2_ID (MTK_PIN_NO(223) | 5) +#define MT6589_GPIO223__FUNC_MFG_TEST_CK (MTK_PIN_NO(223) | 6) +#define MT6589_GPIO223__FUNC_USB_SDA (MTK_PIN_NO(223) | 7) + +#define MT6589_GPIO224__FUNC_GPIO224 (MTK_PIN_NO(224) | 0) +#define MT6589_GPIO224__FUNC_MRG_I2S_PCM_TX (MTK_PIN_NO(224) | 1) +#define MT6589_GPIO224__FUNC_EINT17 (MTK_PIN_NO(224) | 2) +#define MT6589_GPIO224__FUNC_I2SOUT_DAT (MTK_PIN_NO(224) | 3) +#define MT6589_GPIO224__FUNC_PCM0_DO (MTK_PIN_NO(224) | 4) +#define MT6589_GPIO224__FUNC_VDEC_TEST_CK (MTK_PIN_NO(224) | 6) + +#define MT6589_GPIO225__FUNC_GPIO225 (MTK_PIN_NO(225) | 0) +#define MT6589_GPIO225__FUNC_MD1_DAI_RX_GPIO (MTK_PIN_NO(225) | 1) +#define MT6589_GPIO225__FUNC_EINT18 (MTK_PIN_NO(225) | 2) +#define MT6589_GPIO225__FUNC_BT_SYNC (MTK_PIN_NO(225) | 3) +#define MT6589_GPIO225__FUNC_MD2_DAI_RX_GPIO (MTK_PIN_NO(225) | 4) +#define MT6589_GPIO225__FUNC_DSP2_IMS (MTK_PIN_NO(225) | 5) +#define MT6589_GPIO225__FUNC_VENC_TEST_CK (MTK_PIN_NO(225) | 6) + +#define MT6589_GPIO226__FUNC_GPIO226 (MTK_PIN_NO(226) | 0) +#define MT6589_GPIO226__FUNC_MSDC3_DAT2 (MTK_PIN_NO(226) | 1) +#define MT6589_GPIO226__FUNC_EINT71 (MTK_PIN_NO(226) | 2) +#define MT6589_GPIO226__FUNC_SCL6 (MTK_PIN_NO(226) | 3) +#define MT6589_GPIO226__FUNC_PWM5 (MTK_PIN_NO(226) | 4) +#define MT6589_GPIO226__FUNC_CLKM4 (MTK_PIN_NO(226) | 5) +#define MT6589_GPIO226__FUNC_A_FUNC_DIN_0 (MTK_PIN_NO(226) | 7) + +#define MT6589_GPIO227__FUNC_GPIO227 (MTK_PIN_NO(227) | 0) +#define MT6589_GPIO227__FUNC_MSDC3_DAT3 (MTK_PIN_NO(227) | 1) +#define MT6589_GPIO227__FUNC_EINT72 (MTK_PIN_NO(227) | 2) +#define MT6589_GPIO227__FUNC_SDA6 (MTK_PIN_NO(227) | 3) +#define MT6589_GPIO227__FUNC_PWM6 (MTK_PIN_NO(227) | 4) +#define MT6589_GPIO227__FUNC_CLKM5 (MTK_PIN_NO(227) | 5) +#define MT6589_GPIO227__FUNC_A_FUNC_CK (MTK_PIN_NO(227) | 7) + +#define MT6589_GPIO228__FUNC_GPIO228 (MTK_PIN_NO(228) | 0) +#define MT6589_GPIO228__FUNC_MSDC3_CMD (MTK_PIN_NO(228) | 1) +#define MT6589_GPIO228__FUNC_EINT68 (MTK_PIN_NO(228) | 2) +#define MT6589_GPIO228__FUNC_SDA2 (MTK_PIN_NO(228) | 3) +#define MT6589_GPIO228__FUNC_PWM2 (MTK_PIN_NO(228) | 4) +#define MT6589_GPIO228__FUNC_CLKM1 (MTK_PIN_NO(228) | 5) +#define MT6589_GPIO228__FUNC_A_FUNC_DIN_3 (MTK_PIN_NO(228) | 7) + +#define MT6589_GPIO229__FUNC_GPIO229 (MTK_PIN_NO(229) | 0) +#define MT6589_GPIO229__FUNC_MSDC3_CLK (MTK_PIN_NO(229) | 1) +#define MT6589_GPIO229__FUNC_EINT67 (MTK_PIN_NO(229) | 2) +#define MT6589_GPIO229__FUNC_SCL2 (MTK_PIN_NO(229) | 3) +#define MT6589_GPIO229__FUNC_PWM1 (MTK_PIN_NO(229) | 4) +#define MT6589_GPIO229__FUNC_CLKM0 (MTK_PIN_NO(229) | 5) +#define MT6589_GPIO229__FUNC_A_FUNC_DIN_4 (MTK_PIN_NO(229) | 7) + +#define MT6589_GPIO230__FUNC_GPIO230 (MTK_PIN_NO(230) | 0) +#define MT6589_GPIO230__FUNC_MSDC3_DAT1 (MTK_PIN_NO(230) | 1) +#define MT6589_GPIO230__FUNC_EINT70 (MTK_PIN_NO(230) | 2) +#define MT6589_GPIO230__FUNC_SDA3 (MTK_PIN_NO(230) | 3) +#define MT6589_GPIO230__FUNC_PWM4 (MTK_PIN_NO(230) | 4) +#define MT6589_GPIO230__FUNC_CLKM3 (MTK_PIN_NO(230) | 5) +#define MT6589_GPIO230__FUNC_A_FUNC_DIN_1 (MTK_PIN_NO(230) | 7) + +#define MT6589_GPIO231__FUNC_GPIO231 (MTK_PIN_NO(231) | 0) +#define MT6589_GPIO231__FUNC_MSDC3_DAT0 (MTK_PIN_NO(231) | 1) +#define MT6589_GPIO231__FUNC_EINT69 (MTK_PIN_NO(231) | 2) +#define MT6589_GPIO231__FUNC_SCL3 (MTK_PIN_NO(231) | 3) +#define MT6589_GPIO231__FUNC_PWM3 (MTK_PIN_NO(231) | 4) +#define MT6589_GPIO231__FUNC_CLKM2 (MTK_PIN_NO(231) | 5) +#define MT6589_GPIO231__FUNC_A_FUNC_DIN_2 (MTK_PIN_NO(231) | 7) #endif /* __MT6589_PINFUNC_H */ From a63a87b233b32887964024f239555e90ae386da2 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:26:02 +0900 Subject: [PATCH 35/98] arm: dts: mediatek: mt6589: add msdc 0-4 Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 309 +++++++++++++++++++++++++ 1 file changed, 309 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 1c627bbe78cf79..a7802258a42541 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -261,5 +262,313 @@ clock-names = "baud", "bus"; status = "disabled"; }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt6589-mmc", + "mediatek,mt2701-mmc"; + reg = <0x11230000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_MSDC0>, + <&topckgen CLK_TOP_MUX_MSDC0>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt6589-mmc", + "mediatek,mt2701-mmc"; + reg = <0x11240000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_MSDC1>, + <&topckgen CLK_TOP_MUX_MSDC1>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt6589-mmc", + "mediatek,mt2701-mmc"; + reg = <0x11250000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_MSDC2>, + <&topckgen CLK_TOP_MUX_MSDC2>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc3: mmc@11260000 { + compatible = "mediatek,mt6589-mmc", + "mediatek,mt2701-mmc"; + reg = <0x11260000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_MSDC3>, + <&topckgen CLK_TOP_MUX_MSDC3>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + + mmc4: mmc@11270000 { + compatible = "mediatek,mt6589-mmc", + "mediatek,mt2701-mmc"; + reg = <0x11270000 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_MSDC4>, + <&topckgen CLK_TOP_MUX_MSDC4>; + clock-names = "source", "hclk"; + status = "disabled"; + }; + }; +}; + +&pio { + mmc0_pins_default: mmc0default { +/* + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + }; +*/ + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0 { +/* + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <2>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <2>; + bias-pull-down = ; + }; +*/ + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1default { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + //drive-strength = <4>; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-disable; + //drive-strength = <4>; + drive-strength = <8>; + }; + +/* 182:00001001 + pins-wp { + pinmux = ; + input-enable; + bias-disable; + }; +*/ + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_pins_uhs: mmc1 { +/* + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <4>; + }; + + pins-clk { + pinmux = ; + drive-strength = <4>; + }; +*/ + /* dummy */ + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc2_pins_default: mmc2default { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <4>; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + drive-strength = <4>; + }; + + pins-wp { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc2_pins_uhs: mmc2 { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <4>; + }; + + pins-clk { + pinmux = ; + drive-strength = <4>; + }; + }; + + mmc3_pins_default: mmc3default { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <4>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + drive-strength = <4>; + }; + }; + + mmc3_pins_uhs: mmc3 { + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <4>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + }; + + mmc4_pins_default: mmc4default { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-pull-down; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc4_pins_uhs: mmc4 { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <2>; + bias-pull-up = ; + }; + + pins-clk { + pinmux = ; + drive-strength = <2>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; }; }; From 3036e8ad598d0a37dfe9df951c9b252ef47c67f9 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:26:49 +0900 Subject: [PATCH 36/98] arm: dts: mediatek: mt6589: lenovo-blade-b8000-f: add mmcs Signed-off-by: Akari Tsuyukusa --- .../mediatek/mt6589-lenovo-blade-b8000-f.dts | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts index e59c4c3ce2f9a4..5377465225a240 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts @@ -4,8 +4,67 @@ */ #include "mt6589-lenovo-blade.dtsi" +#include / { model = "Lenovo YOGA Tablet 10 (Wi-Fi)"; compatible = "lenovo,blade-b8000-f", "lenovo,blade", "mediatek,mt6589"; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +/* Internal storage */ +&mmc0 { +// status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + non-removable; + bus-width = <8>; + max-frequency = <50000000>; +// cap-mmc-highspeed; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + +/* SD Card */ +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_uhs>; + bus-width = <4>; +// max-frequency = <50000000>; + max-frequency = <400000>; +// cap-sd-highspeed; +// cd-gpios = <&pio 171 GPIO_ACTIVE_HIGH>; +// gpio182 is fake + cd-gpios = <&pio 182 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; }; From 3758cd0ae4c5a7aa28ff5fe3776dc091a70fa1e2 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 13:32:15 +0900 Subject: [PATCH 37/98] clk: mediatek: mt6589: reindex clock ids Signed-off-by: Akari Tsuyukusa --- include/dt-bindings/clock/mt6589-clk.h | 409 ++++++++++++------------- 1 file changed, 203 insertions(+), 206 deletions(-) diff --git a/include/dt-bindings/clock/mt6589-clk.h b/include/dt-bindings/clock/mt6589-clk.h index 67e6b75118522c..ed8c44a43d2b2a 100644 --- a/include/dt-bindings/clock/mt6589-clk.h +++ b/include/dt-bindings/clock/mt6589-clk.h @@ -1,11 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ -/* clock IDs from mt_clkmgr.h */ - - /* APMIXEDSYS */ #define CLK_APMIXED_ARMPLL 0 #define CLK_APMIXED_MAINPLL 1 @@ -19,212 +16,212 @@ /* TOPCKGEN */ -#define CLK_TOP_CLK_NULL 1 +#define CLK_TOP_CLK_NULL 0 -#define CLK_TOP_CLKPH_MCK 11 -#define CLK_TOP_CPUM_TCK_IN 12 +#define CLK_TOP_CLKPH_MCK 1 +#define CLK_TOP_CPUM_TCK_IN 2 -#define CLK_TOP_SYSPLL 21 -#define CLK_TOP_MAINPLL_D3 22 -#define CLK_TOP_MAINPLL_D5 23 -#define CLK_TOP_MAINPLL_D7 24 +#define CLK_TOP_SYSPLL 3 +#define CLK_TOP_MAINPLL_D3 4 +#define CLK_TOP_MAINPLL_D5 5 +#define CLK_TOP_MAINPLL_D7 6 /* GPU: 403MHz */ -#define CLK_TOP_SYSPLL_D2 31 -#define CLK_TOP_SYSPLL_D2P5 32 +#define CLK_TOP_SYSPLL_D2 7 +#define CLK_TOP_SYSPLL_D2P5 8 /* MAINPLL / 3 / 2 = GPU: 268MHz */ -#define CLK_TOP_SYSPLL_D3 33 -#define CLK_TOP_SYSPLL_D3P5 34 +#define CLK_TOP_SYSPLL_D3 9 +#define CLK_TOP_SYSPLL_D3P5 10 /* MAINPLL / 2 / 4 */ -#define CLK_TOP_SYSPLL_D4 35 -#define CLK_TOP_SYSPLL_D5 36 +#define CLK_TOP_SYSPLL_D4 11 +#define CLK_TOP_SYSPLL_D5 12 /* MAINPLL /2 / 6 */ -#define CLK_TOP_SYSPLL_D6 37 -#define CLK_TOP_SYSPLL_D8 38 -#define CLK_TOP_SYSPLL_D10 39 -#define CLK_TOP_SYSPLL_D12 40 -#define CLK_TOP_SYSPLL_D16 41 -#define CLK_TOP_SYSPLL_D24 42 +#define CLK_TOP_SYSPLL_D6 13 +#define CLK_TOP_SYSPLL_D8 14 +#define CLK_TOP_SYSPLL_D10 15 +#define CLK_TOP_SYSPLL_D12 16 +#define CLK_TOP_SYSPLL_D16 17 +#define CLK_TOP_SYSPLL_D24 18 /* may be univpll1 parent */ -#define CLK_TOP_UNIVPLL_D2 51 +#define CLK_TOP_UNIVPLL_D2 19 /* must be univpll2 parent */ -#define CLK_TOP_UNIVPLL_D3 52 +#define CLK_TOP_UNIVPLL_D3 20 /* UNIVPLL / 5 */ -#define CLK_TOP_UNIVPLL_D5 53 -#define CLK_TOP_UNIVPLL_D7 54 -#define CLK_TOP_UNIVPLL_D10 55 -#define CLK_TOP_UNIVPLL_D26 56 +#define CLK_TOP_UNIVPLL_D5 21 +#define CLK_TOP_UNIVPLL_D7 22 +#define CLK_TOP_UNIVPLL_D10 23 +#define CLK_TOP_UNIVPLL_D26 24 /* GPU: 312MHz */ -#define CLK_TOP_UNIVPLL1_D2 61 +#define CLK_TOP_UNIVPLL1_D2 25 /* GPU: 156MHz */ -#define CLK_TOP_UNIVPLL1_D4 62 -#define CLK_TOP_UNIVPLL1_D6 63 -#define CLK_TOP_UNIVPLL1_D8 64 -#define CLK_TOP_UNIVPLL1_D10 65 +#define CLK_TOP_UNIVPLL1_D4 26 +#define CLK_TOP_UNIVPLL1_D6 27 +#define CLK_TOP_UNIVPLL1_D8 28 +#define CLK_TOP_UNIVPLL1_D10 29 /* UNIVPLL / 3 / 2 */ -#define CLK_TOP_UNIVPLL2_D2 71 +#define CLK_TOP_UNIVPLL2_D2 30 /* unknown */ -#define CLK_TOP_UNIVPLL2_D4 72 -#define CLK_TOP_UNIVPLL2_D6 73 -#define CLK_TOP_UNIVPLL2_D8 74 +#define CLK_TOP_UNIVPLL2_D4 31 +#define CLK_TOP_UNIVPLL2_D6 32 +#define CLK_TOP_UNIVPLL2_D8 33 -#define CLK_TOP_MMPLL_D2 81 +#define CLK_TOP_MMPLL_D2 34 /* GPU: 476MHz */ -#define CLK_TOP_MMPLL_D3 82 +#define CLK_TOP_MMPLL_D3 35 /* GPU: 357MHz */ -#define CLK_TOP_MMPLL_D4 83 +#define CLK_TOP_MMPLL_D4 36 /* GPU: 286MHz */ -#define CLK_TOP_MMPLL_D5 84 +#define CLK_TOP_MMPLL_D5 37 /* GPU: 238MHz */ -#define CLK_TOP_MMPLL_D6 85 -#define CLK_TOP_MMPLL_D7 86 +#define CLK_TOP_MMPLL_D6 38 +#define CLK_TOP_MMPLL_D7 39 -#define CLK_TOP_LVDSPLL 91 -#define CLK_TOP_LVDSPLL_D2 92 -#define CLK_TOP_LVDSPLL_D4 93 -#define CLK_TOP_LVDSPLL_D8 94 +#define CLK_TOP_LVDSPLL 40 +#define CLK_TOP_LVDSPLL_D2 41 +#define CLK_TOP_LVDSPLL_D4 42 +#define CLK_TOP_LVDSPLL_D8 43 -#define CLK_TOP_LVDSTX_CLKDIG_CT 101 +#define CLK_TOP_LVDSTX_CLKDIG_CT 44 -#define CLK_TOP_TVHDMI_H 111 +#define CLK_TOP_TVHDMI_H 45 -#define CLK_TOP_HDMITX_CLKDIG_D2 121 -#define CLK_TOP_HDMITX_CLKDIG_D3 122 +#define CLK_TOP_HDMITX_CLKDIG_D2 46 +#define CLK_TOP_HDMITX_CLKDIG_D3 47 -#define CLK_TOP_TVHDMI_D2 131 -#define CLK_TOP_TVHDMI_D4 132 +#define CLK_TOP_TVHDMI_D2 48 +#define CLK_TOP_TVHDMI_D4 49 -#define CLK_TOP_MEMPLL_MCK_D4 141 +#define CLK_TOP_MEMPLL_MCK_D4 50 -#define CLK_TOP_APLL 151 -#define CLK_TOP_APLL_D4 152 -#define CLK_TOP_APLL_D8 153 -#define CLK_TOP_APLL_D16 154 -#define CLK_TOP_APLL_D24 155 +#define CLK_TOP_APLL 51 +#define CLK_TOP_APLL_D4 52 +#define CLK_TOP_APLL_D8 53 +#define CLK_TOP_APLL_D16 54 +#define CLK_TOP_APLL_D24 55 -#define CLK_TOP_VPLL_DPIX 161 +#define CLK_TOP_VPLL_DPIX 56 -#define CLK_TOP_AD_ISP_208M_CK 171 +#define CLK_TOP_AD_ISP_208M_CK 57 -#define CLK_TOP_AD_MSDC_H208M_CK 181 +#define CLK_TOP_AD_MSDC_H208M_CK 58 /* MUXs */ /* CLK_CFG_0 */ -#define CLK_TOP_MUX_AXI 201 -#define CLK_TOP_MUX_SMI 202 -#define CLK_TOP_MUX_MFG 203 -#define CLK_TOP_MUX_IRDA 204 +#define CLK_TOP_MUX_AXI 59 +#define CLK_TOP_MUX_SMI 60 +#define CLK_TOP_MUX_MFG 61 +#define CLK_TOP_MUX_IRDA 62 /* CLK_CFG_1 */ -#define CLK_TOP_MUX_CAM 205 -#define CLK_TOP_MUX_AUDINTBUS 206 -#define CLK_TOP_MUX_JPG 207 -#define CLK_TOP_MUX_DISP 208 +#define CLK_TOP_MUX_CAM 63 +#define CLK_TOP_MUX_AUDINTBUS 64 +#define CLK_TOP_MUX_JPG 65 +#define CLK_TOP_MUX_DISP 66 /* CLK_CFG_2 */ -#define CLK_TOP_MUX_MSDC1 209 -#define CLK_TOP_MUX_MSDC2 210 -#define CLK_TOP_MUX_MSDC3 211 -#define CLK_TOP_MUX_MSDC4 212 +#define CLK_TOP_MUX_MSDC1 67 +#define CLK_TOP_MUX_MSDC2 68 +#define CLK_TOP_MUX_MSDC3 69 +#define CLK_TOP_MUX_MSDC4 70 /* CLK_CFG_3 */ -#define CLK_TOP_MUX_USB20 213 +#define CLK_TOP_MUX_USB20 71 // 214 // 215 // 216 /* CLK_CFG_4 */ -#define CLK_TOP_MUX_HYD 217 -#define CLK_TOP_MUX_VENC 218 -#define CLK_TOP_MUX_SPI 219 -#define CLK_TOP_MUX_UART 220 +#define CLK_TOP_MUX_HYD 72 +#define CLK_TOP_MUX_VENC 73 +#define CLK_TOP_MUX_SPI 74 +#define CLK_TOP_MUX_UART 75 /* CLK_CFG_6 */ -#define CLK_TOP_MUX_MEM 221 -#define CLK_TOP_MUX_CAMTG 222 -#define CLK_TOP_MUX_FD 223 -#define CLK_TOP_MUX_AUDIO 224 +#define CLK_TOP_MUX_MEM 76 +#define CLK_TOP_MUX_CAMTG 77 +#define CLK_TOP_MUX_FD 78 +#define CLK_TOP_MUX_AUDIO 79 /* CLK_CFG_7 */ -#define CLK_TOP_MUX_FIX 225 -#define CLK_TOP_MUX_VDEC 226 -#define CLK_TOP_MUX_DPILVDS 227 +#define CLK_TOP_MUX_FIX 80 +#define CLK_TOP_MUX_VDEC 81 +#define CLK_TOP_MUX_DPILVDS 82 /* CLK_CFG_8 */ -#define CLK_TOP_MUX_PMICSPI 228 -#define CLK_TOP_MUX_MSDC0 229 -#define CLK_TOP_MUX_SMI_MFG_AS 230 +#define CLK_TOP_MUX_PMICSPI 83 +#define CLK_TOP_MUX_MSDC0 84 +#define CLK_TOP_MUX_SMI_MFG_AS 85 -#define CLK_TOPCK_PMICSPI 301 +#define CLK_TOPCK_PMICSPI 86 /* INFRACFG */ -#define CLK_INFRA_MUX1 1 - -#define CLK_INFRA_DBGCLK 64 -#define CLK_INFRA_SMI 65 -#define CLK_INFRA_SPI0 66 -#define CLK_INFRA_AUDIO 69 -#define CLK_INFRA_DEVAPC 70 -#define CLK_INFRA_MFGAXI 71 -#define CLK_INFRA_M4U 72 -#define CLK_INFRA_MD1MCUAXI 73 -#define CLK_INFRA_MD1HWMIXAXI 74 -#define CLK_INFRA_MD1AHB 75 -#define CLK_INFRA_MD2MCUAXI 76 -#define CLK_INFRA_MD2HWMIXAXI 77 -#define CLK_INFRA_MD2AHB 78 -#define CLK_INFRA_CPUM 79 -#define CLK_INFRA_KP 80 -#define CLK_INFRA_CCIF0 84 -#define CLK_INFRA_CCIF1 85 -#define CLK_INFRA_PMICSPI 86 -#define CLK_INFRA_PMICWRAP 87 +#define CLK_INFRA_MUX1 0 + +#define CLK_INFRA_DBGCLK 1 +#define CLK_INFRA_SMI 2 +#define CLK_INFRA_SPI0 3 +#define CLK_INFRA_AUDIO 4 +#define CLK_INFRA_DEVAPC 5 +#define CLK_INFRA_MFGAXI 6 +#define CLK_INFRA_M4U 7 +#define CLK_INFRA_MD1MCUAXI 8 +#define CLK_INFRA_MD1HWMIXAXI 9 +#define CLK_INFRA_MD1AHB 10 +#define CLK_INFRA_MD2MCUAXI 11 +#define CLK_INFRA_MD2HWMIXAXI 12 +#define CLK_INFRA_MD2AHB 13 +#define CLK_INFRA_CPUM 14 +#define CLK_INFRA_KP 15 +#define CLK_INFRA_CCIF0 16 +#define CLK_INFRA_CCIF1 17 +#define CLK_INFRA_PMICSPI 18 +#define CLK_INFRA_PMICWRAP 19 /* PERICFG */ -#define CLK_PERI0_NFI 0 -#define CLK_PERI0_THERM 1 -#define CLK_PERI0_PWM1 2 -#define CLK_PERI0_PWM2 3 -#define CLK_PERI0_PWM3 4 -#define CLK_PERI0_PWM4 5 -#define CLK_PERI0_PWM5 6 -#define CLK_PERI0_PWM6 7 -#define CLK_PERI0_PWM7 8 -#define CLK_PERI0_PWM 9 -#define CLK_PERI0_USB0 10 -#define CLK_PERI0_USB1 11 -#define CLK_PERI0_APDMA 12 -#define CLK_PERI0_MSDC0 13 -#define CLK_PERI0_MSDC1 14 -#define CLK_PERI0_MSDC2 15 -#define CLK_PERI0_MSDC3 16 -#define CLK_PERI0_MSDC4 17 -#define CLK_PERI0_APHIF 18 -#define CLK_PERI0_MDHIF 19 -#define CLK_PERI0_NLI 20 -#define CLK_PERI0_IRDA 21 -#define CLK_PERI0_UART0 22 -#define CLK_PERI0_UART1 23 -#define CLK_PERI0_UART2 24 -#define CLK_PERI0_UART3 25 -#define CLK_PERI0_I2C0 26 -#define CLK_PERI0_I2C1 27 -#define CLK_PERI0_I2C2 28 -#define CLK_PERI0_I2C3 29 -#define CLK_PERI0_I2C4 30 -#define CLK_PERI0_I2C5 31 - -#define CLK_PERI1_I2C6 32 -#define CLK_PERI1_PWRAP 33 +#define CLK_PERI0_NFI 0 +#define CLK_PERI0_THERM 1 +#define CLK_PERI0_PWM1 2 +#define CLK_PERI0_PWM2 3 +#define CLK_PERI0_PWM3 4 +#define CLK_PERI0_PWM4 5 +#define CLK_PERI0_PWM5 6 +#define CLK_PERI0_PWM6 7 +#define CLK_PERI0_PWM7 8 +#define CLK_PERI0_PWM 9 +#define CLK_PERI0_USB0 10 +#define CLK_PERI0_USB1 11 +#define CLK_PERI0_APDMA 12 +#define CLK_PERI0_MSDC0 13 +#define CLK_PERI0_MSDC1 14 +#define CLK_PERI0_MSDC2 15 +#define CLK_PERI0_MSDC3 16 +#define CLK_PERI0_MSDC4 17 +#define CLK_PERI0_APHIF 18 +#define CLK_PERI0_MDHIF 19 +#define CLK_PERI0_NLI 20 +#define CLK_PERI0_IRDA 21 +#define CLK_PERI0_UART0 22 +#define CLK_PERI0_UART1 23 +#define CLK_PERI0_UART2 24 +#define CLK_PERI0_UART3 25 +#define CLK_PERI0_I2C0 26 +#define CLK_PERI0_I2C1 27 +#define CLK_PERI0_I2C2 28 +#define CLK_PERI0_I2C3 29 +#define CLK_PERI0_I2C4 30 +#define CLK_PERI0_I2C5 31 + +#define CLK_PERI1_I2C6 32 +#define CLK_PERI1_PWRAP 33 #define CLK_PERI1_AUXADC 34 -#define CLK_PERI1_SPI1 35 -#define CLK_PERI1_FHCTL 36 +#define CLK_PERI1_SPI1 35 +#define CLK_PERI1_FHCTL 36 #define CLK_PERI_MUX_UART0 37 #define CLK_PERI_MUX_UART1 38 @@ -233,76 +230,76 @@ /* DISP */ -#define CLK_DISP0_LARB2_SMI 128 -#define CLK_DISP0_ROT_ENGINE 129 -#define CLK_DISP0_ROT_SMI 130 -#define CLK_DISP0_SCL 131 -#define CLK_DISP0_OVL_ENGINE 132 -#define CLK_DISP0_OVL_SMI 133 -#define CLK_DISP0_COLOR 134 -#define CLK_DISP0_2DSHP 135 -#define CLK_DISP0_BLS 136 -#define CLK_DISP0_WDMA0_ENGINE 137 -#define CLK_DISP0_WDMA0_SMI 138 -#define CLK_DISP0_WDMA1_ENGINE 139 -#define CLK_DISP0_WDMA1_SMI 140 -#define CLK_DISP0_RDMA0_ENGINE 141 -#define CLK_DISP0_RDMA0_SMI 142 -#define CLK_DISP0_RDMA0_OUTPUT 143 -#define CLK_DISP0_RDMA1_ENGINE 144 -#define CLK_DISP0_RDMA1_SMI 145 -#define CLK_DISP0_RDMA1_OUTPUT 146 -#define CLK_DISP0_GAMMA_ENGINE 147 -#define CLK_DISP0_GAMMA_PIXEL 148 -#define CLK_DISP0_CMDQ_ENGINE 149 -#define CLK_DISP0_CMDQ_SMI 150 -#define CLK_DISP0_G2D_ENGINE 151 -#define CLK_DISP0_G2D_SMI 152 - -#define CLK_DISP1_DBI_ENGINE 160 -#define CLK_DISP1_DBI_SMI 161 -#define CLK_DISP1_DBI_OUTPUT 162 -#define CLK_DISP1_DSI_ENGINE 163 -#define CLK_DISP1_DSI_DIGITAL 164 -#define CLK_DISP1_DSI_DIGITAL_LANE 165 -#define CLK_DISP1_DPI0 166 -#define CLK_DISP1_DPI1 167 -#define CLK_DISP1_LCD 168 -#define CLK_DISP1_SLCD 169 +#define CLK_DISP0_LARB2_SMI 0 +#define CLK_DISP0_ROT_ENGINE 1 +#define CLK_DISP0_ROT_SMI 2 +#define CLK_DISP0_SCL 3 +#define CLK_DISP0_OVL_ENGINE 4 +#define CLK_DISP0_OVL_SMI 5 +#define CLK_DISP0_COLOR 6 +#define CLK_DISP0_2DSHP 7 +#define CLK_DISP0_BLS 8 +#define CLK_DISP0_WDMA0_ENGINE 9 +#define CLK_DISP0_WDMA0_SMI 10 +#define CLK_DISP0_WDMA1_ENGINE 11 +#define CLK_DISP0_WDMA1_SMI 12 +#define CLK_DISP0_RDMA0_ENGINE 13 +#define CLK_DISP0_RDMA0_SMI 14 +#define CLK_DISP0_RDMA0_OUTPUT 15 +#define CLK_DISP0_RDMA1_ENGINE 16 +#define CLK_DISP0_RDMA1_SMI 17 +#define CLK_DISP0_RDMA1_OUTPUT 18 +#define CLK_DISP0_GAMMA_ENGINE 19 +#define CLK_DISP0_GAMMA_PIXEL 20 +#define CLK_DISP0_CMDQ_ENGINE 21 +#define CLK_DISP0_CMDQ_SMI 22 +#define CLK_DISP0_G2D_ENGINE 23 +#define CLK_DISP0_G2D_SMI 24 + +#define CLK_DISP1_DBI_ENGINE 25 +#define CLK_DISP1_DBI_SMI 26 +#define CLK_DISP1_DBI_OUTPUT 27 +#define CLK_DISP1_DSI_ENGINE 28 +#define CLK_DISP1_DSI_DIGITAL 29 +#define CLK_DISP1_DSI_DIGITAL_LANE 30 +#define CLK_DISP1_DPI0 31 +#define CLK_DISP1_DPI1 32 +#define CLK_DISP1_LCD 33 +#define CLK_DISP1_SLCD 34 /* IMG */ -#define CLK_IMAGE_LARB3_SMI 192 -#define CLK_IMAGE_LARB4_SMI 194 -#define CLK_IMAGE_COMMN_SMI 196 -#define CLK_IMAGE_CAM_SMI 197 -#define CLK_IMAGE_CAM_CAM 198 -#define CLK_IMAGE_SEN_TG 199 -#define CLK_IMAGE_SEN_CAM 200 -#define CLK_IMAGE_JPGD_SMI 201 -#define CLK_IMAGE_JPGD_JPG 202 -#define CLK_IMAGE_JPGE_SMI 203 -#define CLK_IMAGE_JPGE_JPG 204 -#define CLK_IMAGE_FPC 205 +#define CLK_IMAGE_LARB3_SMI 0 +#define CLK_IMAGE_LARB4_SMI 1 +#define CLK_IMAGE_COMMN_SMI 2 +#define CLK_IMAGE_CAM_SMI 3 +#define CLK_IMAGE_CAM_CAM 4 +#define CLK_IMAGE_SEN_TG 5 +#define CLK_IMAGE_SEN_CAM 6 +#define CLK_IMAGE_JPGD_SMI 7 +#define CLK_IMAGE_JPGD_JPG 8 +#define CLK_IMAGE_JPGE_SMI 9 +#define CLK_IMAGE_JPGE_JPG 10 +#define CLK_IMAGE_FPC 11 /* MFG */ -#define CLK_MFG_AXI 224 -#define CLK_MFG_MEM 225 -#define CLK_MFG_G3D 226 -#define CLK_MFG_HYD 227 +#define CLK_MFG_AXI 0 +#define CLK_MFG_MEM 1 +#define CLK_MFG_G3D 2 +#define CLK_MFG_HYD 3 /* AUD */ -#define CLK_AUDIO_AFE 258 -#define CLK_AUDIO_I2S 262 +#define CLK_AUDIO_AFE 0 +#define CLK_AUDIO_I2S 1 /* VDEC */ -#define CLK_VDEC0_VDE 288 +#define CLK_VDEC0_VDE 0 -#define CLK_VDEC1_SMI 320 +#define CLK_VDEC1_SMI 1 /* VENC */ -#define CLK_VENC_VEN 352 +#define CLK_VENC_VEN 0 From 10683b2696f3de96a1f7dcd8807da35b8b2e5969 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 21:08:38 +0900 Subject: [PATCH 38/98] mt6589: Pinctrl v2 driver (#25) * wip: mt6589 pinctrl-v2 * pinctrl: mediatek: common-v2: add DRV_GRP5 in enum * pinctrl: mediatek: common-v2: add DRV_GRP5 def * wip: todo * pinctrl: mediatek: mt6589: fix drive * pinctrl: mediatek: mt6589: fix fix * REVERT: pinctrl: mediatek: common-v1: introduce per-function Link: https://lists.infradead.org/pipermail/linux-mediatek/2026-February/104167.html * dt-bindings: mfd: syscon: remove mediatek,mt6589-pctl-[ab]-syscfg * dt-bindings: pinctrl: mediatek: remove mediatek,mt6589-pinctrl * pinctrl: mediatek: mt6589: wip wip * pinctrl: mediatek: mt6589: add R0 * pinctrl: mediatek: mt6589: cleanup * arm: dts: mediatek: mt6589: change pio to v2 * arm: dts: mediatek: mt6589: DRV+SR * arm: dts: mediatek: mt6589: reduce lines * pinctrl: mediatek: mt6589: reduce more lines * pinctrl: mediatek: mt6589: note * dt-bindings: pinctrl: mediatek: add mt6589 pinctrl (wip) * pinctrl: mediatek: mt6589: remove tdsel/rdsel * pinctrl: mediatek: mt6589: clean * pinctrl: mediatek: mt6589: cleanup header * pinctrl: mediatek: mt6589: add funcs * clk: mediatek: mt6589: reindex clock ids * pinctrl: mediatek: mt6589: fix * pinctrl: mediatek: mt6589: fix eintmux * pinctrl: mediatek: mt6589: fix (sim and drv/sr) * wip: pinctrl: mediatek: mt6589: TDSEL/RDSEL * pinctrl: mediatek: mt6589: remove TDSEL/RDSEL * pinctrl: mediatek: mt6589: cleanup * arm: dts: mediatek: mt6589: remove unused syscfg_pctl_a/b * dt-bindings: pinctrl: mediatek: complete mt6589 pinctrl * pinctrl: mediatek: update pinmux definitions for mt6589 Signed-off-by: Akari Tsuyukusa --------- Signed-off-by: Akari Tsuyukusa --- .../devicetree/bindings/mfd/syscon.yaml | 4 - .../pinctrl/mediatek,mt6589-pinctrl.yaml | 172 +++ .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 - arch/arm/boot/dts/mediatek/mt6589.dtsi | 22 +- drivers/pinctrl/mediatek/Kconfig | 2 +- drivers/pinctrl/mediatek/pinctrl-mt2701.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt2712.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt6397.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt6589.c | 761 ++++++----- drivers/pinctrl/mediatek/pinctrl-mt8127.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8135.c | 8 - drivers/pinctrl/mediatek/pinctrl-mt8167.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8173.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8365.c | 2 + drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 + .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 1 + .../pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 62 +- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 9 - drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h | 1169 ++++++++++------- 20 files changed, 1361 insertions(+), 867 deletions(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 7fc84cdeaa1185..27672adeb1fedb 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -84,8 +84,6 @@ select: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg - - mediatek,mt6589-pctl-a-syscfg - - mediatek,mt6589-pctl-b-syscfg - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg @@ -192,8 +190,6 @@ properties: - mediatek,mt2701-pctl-a-syscfg - mediatek,mt2712-pctl-a-syscfg - mediatek,mt6397-pctl-pmic-syscfg - - mediatek,mt6589-pctl-a-syscfg - - mediatek,mt6589-pctl-b-syscfg - mediatek,mt7988-topmisc - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml new file mode 100644 index 00000000000000..bd9cacf1be01cb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6589-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6589 Pin Controller + +maintainers: + - Akari Tsuyukusa + +description: + The MediaTek pin controller on MT6589 is used to control pin functions, pull + up/down resistance and drive strength options. + +properties: + compatible: + enum: + - mediatek,mt6589-pinctrl + + reg: + minItems: 3 + maxItems: 3 + description: Physical addresses for GPIO base(s) and EINT registers. + + reg-names: + items: + - const: gpio + - const: gpio1 + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: + Specifies the summary IRQ. + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': + type: object + additionalProperties: false + + patternProperties: + '-pins*$': + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 8, 10, 12, 14, 16, 20, 24, 28, 32] + + slew-rate: + enum: [0, 1] + + # TODO + mediatek,pull-up-adv: + description: | + Pull up settings for R0. User can configure those special pins. + Valid arguments are described as below: + 0: R0 disabled. + 1: R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + mediatek,pull-down-adv: + description: | + Pull down settings for R0. User can configure those special pins. + Valid arguments are described as below: + 0: R0 disabled. + 1: R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + required: + - pinmux + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <1>; + #size-cells = <1>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6589-pinctrl"; + reg = <0x10005000 0x1000>, + <0x1020c000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "gpio", "gpio1", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 232>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + interrupts = , + , + ; + + usb_pins_default: usb-pins { + pins_iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index 19270dd0fec1bb..b9680b896f12f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -18,7 +18,6 @@ properties: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl - mediatek,mt6397-pinctrl - - mediatek,mt6589-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl - mediatek,mt8135-pinctrl diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index a7802258a42541..b6331ba16cbe82 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -144,33 +144,23 @@ #clock-cells = <1>; }; - /* - * EINT registers: 0x1000b000 - * GPIO base: 0x10005000, GPIO1 base 0x1020c000 - */ pio: pinctrl@10005000 { compatible = "mediatek,mt6589-pinctrl"; - reg = <0x1000b000 0x1000>; - mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; + reg = <0x10005000 0x1000>, + <0x1020c000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "gpio", "gpio1", "eint"; gpio-controller; #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 232>; interrupt-controller; + interrupt-parent = <&gic>; #interrupt-cells = <2>; interrupts = , , ; }; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt6589-pctl-a-syscfg", "syscon"; - reg = <0x10005000 0x1000>; - }; - - syscfg_pctl_b: syscfg_pctl_b@1020c000 { - compatible = "mediatek,mt6589-pctl-b-syscfg", "syscon"; - reg = <0x1020c000 0x1000>; - }; - timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 8d9f84701793ac..b2d5637f4d1423 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -102,7 +102,7 @@ config PINCTRL_MT6589 depends on MACH_MT6589 || COMPILE_TEST depends on OF default MACH_MT6589 - select PINCTRL_MTK + select PINCTRL_MTK_PARIS config PINCTRL_MT7623 bool "MediaTek MT7623 pin control with generic binding" diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 30bec29de9bdc0..6b1c7122b0fb99 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -504,6 +504,8 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { .dout_offset = 0x0500, .din_offset = 0x0630, .pinmux_offset = 0x0760, + .type1_start = 280, + .type1_end = 280, .port_shf = 4, .port_mask = 0x1f, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index eb6ecaa726793a..bb7394ae252b48 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -553,6 +553,8 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { .dout_offset = 0x0300, .din_offset = 0x0400, .pinmux_offset = 0x0500, + .type1_start = 210, + .type1_end = 210, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index af5f48039895e6..03d0f65d7bcc1f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -27,6 +27,8 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { .dout_offset = (MT6397_PIN_REG_BASE + 0x080), .din_offset = (MT6397_PIN_REG_BASE + 0x0a0), .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0), + .type1_start = 41, + .type1_end = 41, .port_shf = 3, .port_mask = 0x3, .port_align = 2, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6589.c b/drivers/pinctrl/mediatek/pinctrl-mt6589.c index 45d04d4559892d..6149199e1a38e9 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6589.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6589.c @@ -1,39 +1,11 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku - * - * Based on pinctrl-mt2701.c - * Copyright (c) 2015 MediaTek Inc. - * Author: Biao Huang + * Copyright (C) Akari Tsuyukusa */ -#include -#include -#include -#include -#include - -#include "pinctrl-mtk-common.h" +#include "pinctrl-paris.h" #include "pinctrl-mtk-mt6589.h" -/* - * E2, E4, E8, E16: Drive - * SR: ??? - * DM: Dummy - * MSB <-> LSB - */ -static const struct mtk_drv_group_desc mt6589_drv_grp[] = { - /* grp 0: SR E8 E4 E2: 2/4/6/8/10/12/14/16mA */ - MTK_DRV_GRP(2, 16, 0, 2, 2), - /* grp 1: SR E8 E4 DM: 4/8/12/16mA */ - MTK_DRV_GRP(4, 16, 1, 2, 4), - /* grp 2: SR E4 E2 DM: 2/4/6/8mA */ - MTK_DRV_GRP(2, 8, 1, 2, 2), - /* grp 3: SR E16 E8 E4 4/8/12/16/20/24/28/32mA */ - MTK_DRV_GRP(4, 32, 0, 2, 4), -}; - - /* GPIO0 */ #define DRV_CON0 0x0500 #define DRV_CON1 0x0510 @@ -53,413 +25,564 @@ static const struct mtk_drv_group_desc mt6589_drv_grp[] = { #define DRV_CON11 0x05b0 #define DRV_CON12 0x05c0 -static const struct mtk_pin_drv_grp mt6589_pin_drv[] = { +/* for 2nd base */ +#define PINS_FIELD1(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ + PIN_FIELD_CALC(_s_pin, _e_pin, 1, _s_addr, _x_addrs, _s_bit, \ + _x_bits, 32, 1) + +/* all R0 are in one register */ +#define PIN_FIELD_R0(_bit, _pin) \ + PIN_FIELD_CALC(_pin, _pin, 0, 0x04f0, 0x0, _bit, 1, 32, 1) + +/* + * MT6589's Drive/Slew Rate register + * + * E2, E4, E8, E16: Drive + * SR: Slew Rate + * DM: Dummy + * MSB <-> LSB + * + * DRV_GRP1: SR E8 E4 DM : 4/8/12/16mA + * DRV_GRP3: SR E4 E2 DM : 2/4/6/8mA + * DRV_GRP4: SR E8 E4 E2 : 2/4/6/8/10/12/14/16mA + * DRV_GRP5: SR E16 E8 E4 : 4/8/12/16/20/24/28/32mA + */ + +#define PIN_FIELD_SR(_pin, _offset, _bit, _base) \ + PIN_FIELD_CALC(_pin, _pin, _base, _offset, 0x0, _bit, 1, 32, 1) + +#define PINS_FIELD_SR(_pin_s, _pin_e, _offset, _bit, _base) \ + PIN_FIELD_CALC(_pin_s, _pin_e, _base, _offset, 0x0, _bit, 1, 32, 1) + +#define PIN_FIELD_DRV(_pin, _offset, _bit, _base) \ + PIN_FIELD_CALC(_pin, _pin, _base, _offset, 0x0, _bit, 3, 32, 1) + +#define PINS_FIELD_DRV(_pin_s, _pin_e, _offset, _bit, _base) \ + PIN_FIELD_CALC(_pin_s, _pin_e, _base, _offset, 0x0, _bit, 3, 32, 1) + +static const struct mtk_pin_field_calc mt6589_pin_mode_range[] = { + PIN_FIELD_CALC(0, 43, 0, 0x0c00, 0x10, 0, 3, 16, 0), + PIN_FIELD_CALC(44, 46, 0, 0x0980, 0x10, 0, 4, 16, 0), + PIN_FIELD_CALC(47, 49, 0, 0x09a0, 0x10, 0, 4, 16, 0), + PIN_FIELD_CALC(50, 231, 0, 0x0ca0, 0x10, 0, 3, 16, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_dir_range[] = { + PIN_FIELD_CALC(0, 231, 0, 0x0000, 0x10, 0, 1, 16, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_di_range[] = { + PIN_FIELD_CALC(0, 231, 0, 0x0800, 0x10, 0, 1, 16, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_do_range[] = { + PIN_FIELD_CALC(0, 231, 0, 0x0a00, 0x10, 0, 1, 16, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_sr_range[] = { /* MSDC0_DAT 7 to 4 */ - MTK_PIN_DRV_GRP(0, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(1, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(2, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(3, DRV_CON0, 0, 0), + PINS_FIELD_SR(0, 3, DRV_CON0, 3, 0), /* MSDC0_RSTB */ - MTK_PIN_DRV_GRP(4, DRV_CON0, 8, 1), + PIN_FIELD_SR(4, DRV_CON0, 11, 0), /* MSDC0_CMD */ - MTK_PIN_DRV_GRP(5, DRV_CON0, 4, 0), + PIN_FIELD_SR(5, DRV_CON0, 7, 0), /* MSDC0_CLK */ - MTK_PIN_DRV_GRP(6, DRV_CON12, 12, 0), + PIN_FIELD_SR(6, DRV_CON12, 15, 0), /* MSDC0_DAT 3 to 0 */ - MTK_PIN_DRV_GRP(7, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(8, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(9, DRV_CON0, 0, 0), - MTK_PIN_DRV_GRP(10, DRV_CON0, 0, 0), + PINS_FIELD_SR(7, 10, DRV_CON0, 3, 0), /* NFI */ - MTK_PIN_DRV_GRP(11, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(12, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(13, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(14, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(15, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(16, DRV_CON0, 12, 1), - MTK_PIN_DRV_GRP(17, DRV_CON0, 12, 1), + PINS_FIELD_SR(11, 17, DRV_CON0, 15, 0), /* NLD 0 to 15 */ - MTK_PIN_DRV_GRP(18, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(19, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(20, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(21, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(22, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(23, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(24, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(25, DRV_CON0, 16, 1), - MTK_PIN_DRV_GRP(26, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(27, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(28, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(29, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(30, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(31, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(32, DRV_CON0, 20, 1), - MTK_PIN_DRV_GRP(33, DRV_CON0, 20, 1), + PINS_FIELD_SR(18, 25, DRV_CON0, 19, 0), + PINS_FIELD_SR(26, 33, DRV_CON0, 23, 0), /* EINT 0 to 4 */ - MTK_PIN_DRV_GRP(34, DRV_CON0, 24, 2), - MTK_PIN_DRV_GRP(35, DRV_CON0, 28, 2), - MTK_PIN_DRV_GRP(36, DRV_CON1, 0, 2), - MTK_PIN_DRV_GRP(37, DRV_CON1, 4, 2), - MTK_PIN_DRV_GRP(38, DRV_CON1, 8, 2), + PIN_FIELD_SR(34, DRV_CON0, 27, 0), + PIN_FIELD_SR(35, DRV_CON0, 31, 0), + PIN_FIELD_SR(36, DRV_CON1, 3, 0), + PIN_FIELD_SR(37, DRV_CON1, 7, 0), + PIN_FIELD_SR(38, DRV_CON1, 11, 0), /* SPI0 */ - MTK_PIN_DRV_GRP(39, DRV_CON1, 12, 1), - MTK_PIN_DRV_GRP(40, DRV_CON1, 12, 1), - MTK_PIN_DRV_GRP(41, DRV_CON1, 12, 1), - MTK_PIN_DRV_GRP(42, DRV_CON1, 12, 1), - MTK_PIN_DRV_GRP(43, DRV_CON1, 12, 1), + PINS_FIELD_SR(39, 43, DRV_CON1, 15, 0), /* SIM */ - MTK_PIN_DRV_GRP(44, DRV_CON1, 16, 1), - MTK_PIN_DRV_GRP(45, DRV_CON1, 16, 1), - MTK_PIN_DRV_GRP(46, DRV_CON1, 16, 1), - MTK_PIN_DRV_GRP(47, DRV_CON1, 16, 1), - MTK_PIN_DRV_GRP(48, DRV_CON1, 16, 1), - MTK_PIN_DRV_GRP(49, DRV_CON1, 16, 1), + PINS_FIELD_SR(44, 49, DRV_CON1, 19, 0), /* ADC */ - MTK_PIN_DRV_GRP(50, DRV_CON1, 20, 1), - MTK_PIN_DRV_GRP(51, DRV_CON1, 20, 1), - MTK_PIN_DRV_GRP(52, DRV_CON1, 20, 1), + PINS_FIELD_SR(50, 52, DRV_CON1, 23, 0), /* DAC */ - MTK_PIN_DRV_GRP(53, DRV_CON1, 24, 1), - MTK_PIN_DRV_GRP(54, DRV_CON1, 24, 1), - MTK_PIN_DRV_GRP(55, DRV_CON1, 24, 1), + PINS_FIELD_SR(53, 55, DRV_CON1, 27, 0), /* RTC32K_CK */ /* - MTK_PIN_DRV_GRP(56, , , 1), // no drive? + PIN_FIELD_SR(56, , , 0), // no drive? */ /* IDDIG */ - MTK_PIN_DRV_GRP(57, DRV_CON1, 28, 2), + PIN_FIELD_SR(57, DRV_CON1, 31, 0), /* WATCHDOG */ - MTK_PIN_DRV_GRP(58, DRV_CON2, 0, 1), + PIN_FIELD_SR(58, DRV_CON2, 3, 0), /* SRCLKENA */ - MTK_PIN_DRV_GRP(59, DRV_CON2, 4, 1), + PIN_FIELD_SR(59, DRV_CON2, 7, 0), /* SRCVOLTEN */ - MTK_PIN_DRV_GRP(60, DRV_CON2, 8, 1), + PIN_FIELD_SR(60, DRV_CON2, 11, 0), /* JTAG */ - MTK_PIN_DRV_GRP(61, DRV_CON3, 0, 1), - MTK_PIN_DRV_GRP(62, DRV_CON3, 0, 1), - MTK_PIN_DRV_GRP(63, DRV_CON3, 0, 1), - MTK_PIN_DRV_GRP(64, DRV_CON3, 0, 1), - MTK_PIN_DRV_GRP(65, DRV_CON3, 0, 1), - MTK_PIN_DRV_GRP(66, DRV_CON3, 0, 1), + PINS_FIELD_SR(61, 66, DRV_CON3, 3, 0), /* UR2 */ - MTK_PIN_DRV_GRP(69, DRV_CON3, 4, 1), - MTK_PIN_DRV_GRP(70, DRV_CON3, 8, 1), - MTK_PIN_DRV_GRP(71, DRV_CON3, 12, 1), - MTK_PIN_DRV_GRP(72, DRV_CON3, 16, 1), + PIN_FIELD_SR(69, DRV_CON3, 7, 0), + PIN_FIELD_SR(70, DRV_CON3, 11, 0), + PIN_FIELD_SR(71, DRV_CON3, 15, 0), + PIN_FIELD_SR(72, DRV_CON3, 19, 0), /* PWM 1 to 4 */ - MTK_PIN_DRV_GRP(73, DRV_CON3, 20, 1), - MTK_PIN_DRV_GRP(74, DRV_CON3, 24, 1), - MTK_PIN_DRV_GRP(75, DRV_CON3, 28, 1), - MTK_PIN_DRV_GRP(76, DRV_CON4, 0, 1), + PIN_FIELD_SR(73, DRV_CON3, 23, 0), + PIN_FIELD_SR(74, DRV_CON3, 27, 0), + PIN_FIELD_SR(75, DRV_CON3, 31, 0), + PIN_FIELD_SR(76, DRV_CON4, 3, 0), /* UR1 */ - MTK_PIN_DRV_GRP(77, DRV_CON4, 4, 1), - MTK_PIN_DRV_GRP(78, DRV_CON4, 8, 1), - MTK_PIN_DRV_GRP(79, DRV_CON4, 12, 1), - MTK_PIN_DRV_GRP(80, DRV_CON4, 16, 1), + PIN_FIELD_SR(77, DRV_CON4, 7, 0), + PIN_FIELD_SR(78, DRV_CON4, 11, 0), + PIN_FIELD_SR(79, DRV_CON4, 15, 0), + PIN_FIELD_SR(80, DRV_CON4, 19, 0), /* UR4 */ - MTK_PIN_DRV_GRP(81, DRV_CON4, 20, 1), - MTK_PIN_DRV_GRP(82, DRV_CON4, 24, 1), + PIN_FIELD_SR(81, DRV_CON4, 23, 0), + PIN_FIELD_SR(82, DRV_CON4, 27, 0), /* BPI1B */ - MTK_PIN_DRV_GRP(83, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(84, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(85, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(86, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(87, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(88, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(89, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(90, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(91, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(92, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(93, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(94, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(95, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(96, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(97, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(98, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(99, DRV_CON5, 12, 1), + PINS_FIELD_SR(83, 99, DRV_CON5, 15, 0), /* VM 1, 0 */ - MTK_PIN_DRV_GRP(100, DRV_CON5, 12, 1), - MTK_PIN_DRV_GRP(101, DRV_CON5, 12, 1), + PINS_FIELD_SR(100, 101, DRV_CON5, 15, 0), /* BSI 1 */ - MTK_PIN_DRV_GRP(102, DRV_CON5, 16, 1), - MTK_PIN_DRV_GRP(103, DRV_CON5, 16, 1), - MTK_PIN_DRV_GRP(104, DRV_CON5, 16, 1), + PINS_FIELD_SR(102, 104, DRV_CON5, 19, 0), /* TXBPI1 */ - MTK_PIN_DRV_GRP(105, DRV_CON5, 20, 1), + PIN_FIELD_SR(105, DRV_CON5, 23, 0), /* EXT_CLK_EN */ - MTK_PIN_DRV_GRP(106, DRV_CON4, 28, 1), + PIN_FIELD_SR(106, DRV_CON4, 31, 0), /* SRCLKENA2 */ - MTK_PIN_DRV_GRP(107, DRV_CON5, 0, 1), + PIN_FIELD_SR(107, DRV_CON5, 3, 0), /* BSI1A */ - MTK_PIN_DRV_GRP(108, DRV_CON5, 4, 1), - MTK_PIN_DRV_GRP(109, DRV_CON5, 4, 1), - MTK_PIN_DRV_GRP(110, DRV_CON5, 4, 1), - MTK_PIN_DRV_GRP(111, DRV_CON5, 4, 1), - MTK_PIN_DRV_GRP(112, DRV_CON5, 4, 1), + PINS_FIELD_SR(108, 112, DRV_CON5, 7, 0), /* BSI1C */ - MTK_PIN_DRV_GRP(113, DRV_CON5, 8, 1), - MTK_PIN_DRV_GRP(114, DRV_CON5, 8, 1), + PINS_FIELD_SR(113, 114, DRV_CON5, 11, 0), /* EINT10_AUXIN2, EINT11_AUXIN3, EINT16_AUXIN3 */ - MTK_PIN_DRV_GRP(115, DRV_CON6, 0, 1), - MTK_PIN_DRV_GRP(116, DRV_CON6, 4, 1), - MTK_PIN_DRV_GRP(117, DRV_CON6, 8, 1), + PIN_FIELD_SR(115, DRV_CON6, 3, 1), + PIN_FIELD_SR(116, DRV_CON6, 7, 1), + PIN_FIELD_SR(117, DRV_CON6, 11, 1), /* I2S */ - MTK_PIN_DRV_GRP(120, DRV_CON6, 12, 1), - MTK_PIN_DRV_GRP(121, DRV_CON6, 12, 1), - MTK_PIN_DRV_GRP(122, DRV_CON6, 12, 1), - MTK_PIN_DRV_GRP(123, DRV_CON6, 12, 1), + PINS_FIELD_SR(120, 123, DRV_CON6, 15, 1), /* EINT 5 to 9 */ - MTK_PIN_DRV_GRP(124, DRV_CON6, 16, 2), - MTK_PIN_DRV_GRP(125, DRV_CON6, 20, 2), - MTK_PIN_DRV_GRP(126, DRV_CON6, 24, 2), - MTK_PIN_DRV_GRP(127, DRV_CON6, 28, 2), - MTK_PIN_DRV_GRP(128, DRV_CON7, 0, 2), + PIN_FIELD_SR(124, DRV_CON6, 19, 1), + PIN_FIELD_SR(125, DRV_CON6, 23, 1), + PIN_FIELD_SR(126, DRV_CON6, 27, 1), + PIN_FIELD_SR(127, DRV_CON6, 31, 1), + PIN_FIELD_SR(128, DRV_CON7, 3, 1), /* DISP_PWM */ - MTK_PIN_DRV_GRP(129, DRV_CON7, 28, 1), + PIN_FIELD_SR(129, DRV_CON7, 31, 1), /* LPTE/MSDC4_DAT0, LRSTB/MSDC4_DAT1 */ - MTK_PIN_DRV_GRP(130, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(131, DRV_CON8, 20, 0), + PINS_FIELD_SR(130, 131, DRV_CON8, 23, 1), /* LPCE1B, LPCE0B */ - MTK_PIN_DRV_GRP(132, DRV_CON8, 28, 1), - MTK_PIN_DRV_GRP(133, DRV_CON9, 0, 1), + PIN_FIELD_SR(132, DRV_CON8, 31, 1), + PIN_FIELD_SR(133, DRV_CON9, 3, 1), /* SPI1 / MSDC4 */ - MTK_PIN_DRV_GRP(134, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(135, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(136, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(137, DRV_CON8, 20, 0), + PINS_FIELD_SR(134, 137, DRV_CON8, 23, 1), /* LCD / MSDC4 */ - MTK_PIN_DRV_GRP(138, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(139, DRV_CON8, 0, 0), - MTK_PIN_DRV_GRP(140, DRV_CON8, 20, 0), - MTK_PIN_DRV_GRP(141, DRV_CON7, 16, 0), - MTK_PIN_DRV_GRP(142, DRV_CON7, 20, 1), + PIN_FIELD_SR(138, DRV_CON8, 23, 1), + PIN_FIELD_SR(139, DRV_CON8, 3, 1), + PIN_FIELD_SR(140, DRV_CON8, 23, 1), + PIN_FIELD_SR(141, DRV_CON7, 19, 1), + PIN_FIELD_SR(142, DRV_CON7, 23, 1), /* DPI */ - MTK_PIN_DRV_GRP(143, DRV_CON9, 8, 1), - MTK_PIN_DRV_GRP(144, DRV_CON9, 8, 1), - MTK_PIN_DRV_GRP(145, DRV_CON9, 8, 1), - MTK_PIN_DRV_GRP(146, DRV_CON9, 8, 1), - MTK_PIN_DRV_GRP(147, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(148, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(149, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(150, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(151, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(152, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(153, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(154, DRV_CON9, 12, 1), - MTK_PIN_DRV_GRP(155, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(156, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(157, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(158, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(159, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(160, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(161, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(162, DRV_CON9, 16, 1), - MTK_PIN_DRV_GRP(163, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(164, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(165, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(166, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(167, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(168, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(169, DRV_CON9, 20, 1), - MTK_PIN_DRV_GRP(170, DRV_CON9, 20, 1), + PINS_FIELD_SR(143, 146, DRV_CON9, 11, 1), + PINS_FIELD_SR(147, 154, DRV_CON9, 15, 1), + PINS_FIELD_SR(155, 162, DRV_CON9, 19, 1), + PINS_FIELD_SR(163, 170, DRV_CON9, 23, 1), /* MSDC1_INSI, MSDC2_INSI */ - MTK_PIN_DRV_GRP(171, DRV_CON9, 24, 1), - MTK_PIN_DRV_GRP(172, DRV_CON10, 0, 1), + PIN_FIELD_SR(171, DRV_CON9, 27, 1), + PIN_FIELD_SR(172, DRV_CON10, 3, 0), /* MSDC2 */ - MTK_PIN_DRV_GRP(173, DRV_CON10, 4, 1), - MTK_PIN_DRV_GRP(174, DRV_CON10, 8, 3), - MTK_PIN_DRV_GRP(175, DRV_CON10, 8, 3), - MTK_PIN_DRV_GRP(176, DRV_CON10, 12, 3), - MTK_PIN_DRV_GRP(177, DRV_CON12, 20, 3), - MTK_PIN_DRV_GRP(178, DRV_CON10, 8, 3), - MTK_PIN_DRV_GRP(179, DRV_CON10, 8, 3), + PIN_FIELD_SR(173, DRV_CON10, 7, 0), + PINS_FIELD_SR(174, 175, DRV_CON10, 11, 0), + PIN_FIELD_SR(176, DRV_CON10, 15, 0), + PIN_FIELD_SR(177, DRV_CON12, 23, 0), + PINS_FIELD_SR(178, 179, DRV_CON10, 11, 0), /* MSDC1 */ - MTK_PIN_DRV_GRP(180, DRV_CON10, 20, 3), - MTK_PIN_DRV_GRP(181, DRV_CON10, 20, 3), - MTK_PIN_DRV_GRP(182, DRV_CON10, 16, 1), - MTK_PIN_DRV_GRP(183, DRV_CON10, 24, 3), - MTK_PIN_DRV_GRP(184, DRV_CON12, 16, 3), - MTK_PIN_DRV_GRP(185, DRV_CON10, 20, 3), - MTK_PIN_DRV_GRP(186, DRV_CON10, 20, 3), + PINS_FIELD_SR(180, 181, DRV_CON10, 23, 0), + PIN_FIELD_SR(182, DRV_CON10, 19, 0), + PIN_FIELD_SR(183, DRV_CON10, 27, 0), + PIN_FIELD_SR(184, DRV_CON12, 19, 0), + PINS_FIELD_SR(185, 186, DRV_CON10, 23, 0), /* CMPCLK, CMMCLK, CMRST, CMPDN, CMFLASH */ - MTK_PIN_DRV_GRP(209, DRV_CON11, 0, 1), - MTK_PIN_DRV_GRP(210, DRV_CON11, 4, 1), - MTK_PIN_DRV_GRP(211, DRV_CON11, 8, 1), - MTK_PIN_DRV_GRP(212, DRV_CON11, 12, 1), - MTK_PIN_DRV_GRP(213, DRV_CON11, 16, 1), + PIN_FIELD_SR(209, DRV_CON11, 3, 0), + PIN_FIELD_SR(210, DRV_CON11, 7, 0), + PIN_FIELD_SR(211, DRV_CON11, 11, 0), + PIN_FIELD_SR(212, DRV_CON11, 15, 0), + PIN_FIELD_SR(213, DRV_CON11, 19, 0), /* SRCLKENAI */ - MTK_PIN_DRV_GRP(218, DRV_CON11, 20, 1), + PIN_FIELD_SR(218, DRV_CON11, 23, 0), /* UR3 */ - MTK_PIN_DRV_GRP(219, DRV_CON11, 24, 1), - MTK_PIN_DRV_GRP(220, DRV_CON11, 28, 1), + PIN_FIELD_SR(219, DRV_CON11, 27, 0), + PIN_FIELD_SR(220, DRV_CON11, 31, 0), /* PCM0 */ - MTK_PIN_DRV_GRP(221, DRV_CON12, 0, 2), - MTK_PIN_DRV_GRP(222, DRV_CON12, 0, 2), - MTK_PIN_DRV_GRP(223, DRV_CON12, 0, 2), - MTK_PIN_DRV_GRP(224, DRV_CON12, 0, 2), - MTK_PIN_DRV_GRP(225, DRV_CON12, 0, 2), + PINS_FIELD_SR(221, 235, DRV_CON12, 3, 0), /* MSDC3 */ - MTK_PIN_DRV_GRP(226, DRV_CON12, 4, 0), - MTK_PIN_DRV_GRP(227, DRV_CON12, 4, 0), - MTK_PIN_DRV_GRP(228, DRV_CON12, 8, 0), - MTK_PIN_DRV_GRP(229, DRV_CON12, 24, 0), - MTK_PIN_DRV_GRP(230, DRV_CON12, 4, 0), - MTK_PIN_DRV_GRP(231, DRV_CON12, 4, 0), + PINS_FIELD_SR(226, 227, DRV_CON12, 7, 0), + PIN_FIELD_SR(228, DRV_CON12, 11, 0), + PIN_FIELD_SR(229, DRV_CON12, 27, 0), + PINS_FIELD_SR(230, 231, DRV_CON12, 7, 0), }; -#define MT6589_SIM_MODE_PER_REG 3 -#define MT6589_SIM_MODE_BITS 4 +static const struct mtk_pin_field_calc mt6589_pin_smt_range[] = { + PIN_FIELD_CALC(0, 113, 0, 0x0300, 0x10, 0, 1, 16, 0), + PIN_FIELD_CALC(114, 169, 1, 0x0370, 0x10, 2, 1, 16, 0), + PIN_FIELD_CALC(170, 231, 0, 0x03a0, 0x10, 10, 1, 16, 0), +}; -/* based on mtk_pmx_set_mode (pinctrl-mtk-common.c)*/ -static void mt6589_pinmux_set(struct regmap *reg, unsigned int pin, unsigned int mode) -{ - unsigned int pin2, reg_addr, val; - unsigned char bit; - unsigned int mask = (1L << MT6589_SIM_MODE_BITS) - 1; - if (pin < 44 || pin > 49) return; - - pin2 = pin - 44; - if (pin2 <= 2) reg_addr = 0x0980; - else reg_addr = 0x09a0; - - mode &= mask; - bit = pin2 % MT6589_SIM_MODE_PER_REG; - mask <<= (MT6589_SIM_MODE_BITS * bit); - val = (mode << (MT6589_SIM_MODE_BITS * bit)); - regmap_update_bits(reg, reg_addr, mask, val); -} +static const struct mtk_pin_field_calc mt6589_pin_drv_range[] = { + /* MSDC0_DAT 7 to 4 */ + PINS_FIELD_DRV(0, 3, DRV_CON0, 0, 0), -static int mt6589_pull_set(struct regmap *regmap, - const struct mtk_pinctrl_devdata *devdata, - unsigned int pin, bool isup, unsigned int arg) -{ - unsigned int pin2, reg_addr, bit_en, bit_sel; - unsigned int mask, val; - bool enable = (arg != MTK_PUPD_SET_R1R0_00); + /* MSDC0_RSTB */ + PIN_FIELD_DRV(4, DRV_CON0, 8, 0), - if (pin < 44 || pin > 49) - return -EINVAL; + /* MSDC0_CMD */ + PIN_FIELD_DRV(5, DRV_CON0, 4, 0), - pin2 = pin - 44; - if (pin2 <= 2) - reg_addr = 0x0990; - else - reg_addr = 0x09b0; + /* MSDC0_CLK */ + PIN_FIELD_DRV(6, DRV_CON12, 12, 0), - bit_en = (pin2 % 3) + 4; - bit_sel = (pin2 % 3) + 8; + /* MSDC0_DAT 3 to 0 */ + PINS_FIELD_DRV(7, 10, DRV_CON0, 0, 0), - mask = BIT(bit_en) | BIT(bit_sel); - val = (enable ? BIT(bit_en) : 0) | (isup ? BIT(bit_sel) : 0); + /* NFI */ + PINS_FIELD_DRV(11, 17, DRV_CON0, 12, 0), - regmap_update_bits(regmap, reg_addr, mask, val); + /* NLD 0 to 15 */ + PINS_FIELD_DRV(18, 25, DRV_CON0, 16, 0), + PINS_FIELD_DRV(26, 33, DRV_CON0, 20, 0), - return 0; -} + /* EINT 0 to 4 */ + PIN_FIELD_DRV(34, DRV_CON0, 24, 0), + PIN_FIELD_DRV(35, DRV_CON0, 28, 0), + PIN_FIELD_DRV(36, DRV_CON1, 0, 0), + PIN_FIELD_DRV(37, DRV_CON1, 4, 0), + PIN_FIELD_DRV(38, DRV_CON1, 8, 0), + + /* SPI0 */ + PINS_FIELD_DRV(39, 43, DRV_CON1, 12, 0), + + /* SIM */ + PINS_FIELD_DRV(44, 49, DRV_CON1, 16, 0), + + /* ADC */ + PINS_FIELD_DRV(50, 53, DRV_CON1, 20, 0), + + /* DAC */ + PINS_FIELD_DRV(53, 55, DRV_CON1, 24, 0), + + /* RTC32K_CK */ + /* + PIN_FIELD_DRV(56, , , 0), // no drive? + */ + + /* IDDIG */ + PIN_FIELD_DRV(57, DRV_CON1, 28, 0), + + /* WATCHDOG */ + PIN_FIELD_DRV(58, DRV_CON2, 0, 0), + + /* SRCLKENA */ + PIN_FIELD_DRV(59, DRV_CON2, 4, 0), + + /* SRCVOLTEN */ + PIN_FIELD_DRV(60, DRV_CON2, 8, 0), + + /* JTAG */ + PINS_FIELD_DRV(61, 66, DRV_CON3, 0, 0), + + /* UR2 */ + PIN_FIELD_DRV(69, DRV_CON3, 4, 0), + PIN_FIELD_DRV(70, DRV_CON3, 8, 0), + PIN_FIELD_DRV(71, DRV_CON3, 12, 0), + PIN_FIELD_DRV(72, DRV_CON3, 16, 0), + + /* PWM 1 to 4 */ + PIN_FIELD_DRV(73, DRV_CON3, 20, 0), + PIN_FIELD_DRV(74, DRV_CON3, 24, 0), + PIN_FIELD_DRV(75, DRV_CON3, 28, 0), + PIN_FIELD_DRV(76, DRV_CON4, 0, 0), -/* TODO: MSDC_R0, BIAS */ -static const struct mtk_pinctrl_devdata mt6589_pinctrl_data = { + /* UR1 */ + PIN_FIELD_DRV(77, DRV_CON4, 4, 0), + PIN_FIELD_DRV(78, DRV_CON4, 8, 0), + PIN_FIELD_DRV(79, DRV_CON4, 12, 0), + PIN_FIELD_DRV(80, DRV_CON4, 16, 0), + + /* UR4 */ + PIN_FIELD_DRV(81, DRV_CON4, 20, 0), + PIN_FIELD_DRV(82, DRV_CON4, 24, 0), + + /* BPI1B */ + PINS_FIELD_DRV(83, 99, DRV_CON5, 12, 0), + + /* VM 1, 0 */ + PINS_FIELD_DRV(100, 101, DRV_CON5, 12, 0), + + /* BSI 1 */ + PINS_FIELD_DRV(102, 104, DRV_CON5, 16, 0), + + /* TXBPI1 */ + PIN_FIELD_DRV(105, DRV_CON5, 20, 0), + + /* EXT_CLK_EN */ + PIN_FIELD_DRV(106, DRV_CON4, 28, 0), + + /* SRCLKENA2 */ + PIN_FIELD_DRV(107, DRV_CON5, 0, 0), + + /* BSI1A */ + PINS_FIELD_DRV(108, 112, DRV_CON5, 4, 0), + + /* BSI1C */ + PINS_FIELD_DRV(113, 114, DRV_CON5, 8, 0), + + /* EINT10_AUXIN2, EINT11_AUXIN3, EINT16_AUXIN3 */ + PIN_FIELD_DRV(115, DRV_CON6, 0, 1), + PIN_FIELD_DRV(116, DRV_CON6, 4, 1), + PIN_FIELD_DRV(117, DRV_CON6, 8, 1), + + /* I2S */ + PINS_FIELD_DRV(120, 123, DRV_CON6, 12, 1), + + /* EINT 5 to 9 */ + PIN_FIELD_DRV(124, DRV_CON6, 16, 1), + PIN_FIELD_DRV(125, DRV_CON6, 20, 1), + PIN_FIELD_DRV(126, DRV_CON6, 24, 1), + PIN_FIELD_DRV(127, DRV_CON6, 28, 1), + PIN_FIELD_DRV(128, DRV_CON7, 0, 1), + + /* DISP_PWM */ + PIN_FIELD_DRV(129, DRV_CON7, 28, 1), + + /* LPTE/MSDC4_DAT0, LRSTB/MSDC4_DAT1 */ + PINS_FIELD_DRV(130, 131, DRV_CON8, 20, 1), + + /* LPCE1B, LPCE0B */ + PIN_FIELD_DRV(132, DRV_CON8, 28, 1), + PIN_FIELD_DRV(133, DRV_CON9, 0, 1), + + /* SPI1 / MSDC4 */ + PINS_FIELD_DRV(134, 137, DRV_CON8, 20, 1), + + /* LCD / MSDC4 */ + PIN_FIELD_DRV(138, DRV_CON8, 20, 1), + PIN_FIELD_DRV(139, DRV_CON8, 0, 1), + PIN_FIELD_DRV(140, DRV_CON8, 20, 1), + PIN_FIELD_DRV(141, DRV_CON7, 16, 1), + PIN_FIELD_DRV(142, DRV_CON7, 20, 1), + + /* DPI */ + PINS_FIELD_DRV(143, 146, DRV_CON9, 8, 1), + PINS_FIELD_DRV(147, 154, DRV_CON9, 12, 1), + PINS_FIELD_DRV(155, 162, DRV_CON9, 16, 1), + PINS_FIELD_DRV(163, 170, DRV_CON9, 20, 1), + + /* MSDC1_INSI, MSDC2_INSI */ + PIN_FIELD_DRV(171, DRV_CON9, 24, 1), + PIN_FIELD_DRV(172, DRV_CON10, 0, 0), + + /* MSDC2 */ + PIN_FIELD_DRV(173, DRV_CON10, 4, 0), + PINS_FIELD_DRV(174, 175, DRV_CON10, 8, 0), + PIN_FIELD_DRV(176, DRV_CON10, 12, 0), + PIN_FIELD_DRV(177, DRV_CON12, 20, 0), + PINS_FIELD_DRV(178, 179, DRV_CON10, 8, 0), + + /* MSDC1 */ + PINS_FIELD_DRV(180, 181, DRV_CON10, 20, 0), + PIN_FIELD_DRV(182, DRV_CON10, 16, 0), + PIN_FIELD_DRV(183, DRV_CON10, 24, 0), + PIN_FIELD_DRV(184, DRV_CON12, 16, 0), + PINS_FIELD_DRV(185, 186, DRV_CON10, 20, 0), + + /* CMPCLK, CMMCLK, CMRST, CMPDN, CMFLASH */ + PIN_FIELD_DRV(209, DRV_CON11, 0, 0), + PIN_FIELD_DRV(210, DRV_CON11, 4, 0), + PIN_FIELD_DRV(211, DRV_CON11, 8, 0), + PIN_FIELD_DRV(212, DRV_CON11, 12, 0), + PIN_FIELD_DRV(213, DRV_CON11, 16, 0), + + /* SRCLKENAI */ + PIN_FIELD_DRV(218, DRV_CON11, 20, 0), + + /* UR3 */ + PIN_FIELD_DRV(219, DRV_CON11, 24, 0), + PIN_FIELD_DRV(220, DRV_CON11, 28, 0), + + /* PCM0 */ + PINS_FIELD_DRV(221, 225, DRV_CON12, 0, 0), + + /* MSDC3 */ + PINS_FIELD_DRV(226, 227, DRV_CON12, 4, 0), + PIN_FIELD_DRV(228, DRV_CON12, 8, 0), + PIN_FIELD_DRV(229, DRV_CON12, 24, 0), + PINS_FIELD_DRV(230, 231, DRV_CON12, 4, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_r0_range[] = { + PIN_FIELD_R0(0, 6), + PIN_FIELD_R0(1, 5), + PIN_FIELD_R0(2, 10), + PIN_FIELD_R0(3, 9), + PIN_FIELD_R0(4, 8), + PIN_FIELD_R0(5, 7), + PIN_FIELD_R0(6, 3), + PIN_FIELD_R0(7, 2), + PIN_FIELD_R0(8, 1), + PIN_FIELD_R0(9, 0), + PIN_FIELD_R0(10, 229), + PIN_FIELD_R0(11, 228), + PIN_FIELD_R0(12, 231), + PIN_FIELD_R0(13, 230), + PIN_FIELD_R0(14, 226), + PIN_FIELD_R0(15, 227), + PIN_FIELD_R0(16, 139), + PIN_FIELD_R0(17, 141), + PIN_FIELD_R0(18, 130), + PIN_FIELD_R0(19, 131), + PIN_FIELD_R0(20, 138), + PIN_FIELD_R0(21, 140), + PIN_FIELD_R0(22, 137), + PIN_FIELD_R0(23, 134), + PIN_FIELD_R0(24, 135), + PIN_FIELD_R0(25, 136), +}; + +static const struct mtk_pin_field_calc mt6589_pin_ies_range[] = { + PIN_FIELD_CALC(0, 113, 0, 0x0100, 0x10, 0, 1, 16, 0), + PIN_FIELD_CALC(114, 169, 1, 0x0170, 0x10, 2, 1, 16, 0), + PIN_FIELD_CALC(170, 231, 0, 0x01a0, 0x10, 10, 1, 16, 0), +}; + +/* If pin has R0, PULLEN=R1 */ +static const struct mtk_pin_field_calc mt6589_pin_pullen_range[] = { + PIN_FIELD_CALC(0, 43, 0, 0x0200, 0x10, 0, 1, 16, 0), + PIN_FIELD_CALC(44, 46, 0, 0x0990, 0x0, 4, 1, 16, 0), + PIN_FIELD_CALC(47, 49, 0, 0x09b0, 0x0, 4, 1, 16, 0), + PIN_FIELD_CALC(50, 113, 0, 0x0230, 0x10, 2, 1, 16, 0), + PIN_FIELD_CALC(114, 169, 1, 0x0270, 0x10, 2, 1, 16, 0), + PIN_FIELD_CALC(170, 231, 0, 0x02a0, 0x10, 10, 1, 16, 0), +}; + +static const struct mtk_pin_field_calc mt6589_pin_pullsel_range[] = { + PIN_FIELD_CALC(0, 43, 0, 0x0400, 0x10, 0, 1, 16, 0), + PIN_FIELD_CALC(44, 46, 0, 0x0990, 0x0, 8, 1, 16, 0), + PIN_FIELD_CALC(47, 49, 0, 0x09b0, 0x0, 8, 1, 16, 0), + PIN_FIELD_CALC(50, 113, 0, 0x0430, 0x10, 2, 1, 16, 0) + PIN_FIELD_CALC(114, 169, 1, 0x0470, 0x10, 2, 1, 16, 0), + PIN_FIELD_CALC(170, 231, 0, 0x04a0, 0x10, 10, 1, 16, 0), +}; + +static const struct mtk_pin_reg_calc mt6589_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6589_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6589_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6589_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6589_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt6589_pin_sr_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt6589_pin_smt_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt6589_pin_drv_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt6589_pin_r0_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt6589_pin_ies_range), + [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt6589_pin_pullen_range), + [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt6589_pin_pullsel_range), +}; + +static const char * const mt6589_pinctrl_register_base_names[] = { + "gpio", "gpio1", +}; + +static const struct mtk_eint_hw mt6589_eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 192, + .db_cnt = 16, + .db_time = debounce_time_mt6795, +}; + +static const struct mtk_pin_soc mt6589_pinctrl_data = { + .reg_cal = mt6589_reg_cals, .pins = mtk_pins_mt6589, .npins = ARRAY_SIZE(mtk_pins_mt6589), - .grp_desc = mt6589_drv_grp, - .n_grp_cls = ARRAY_SIZE(mt6589_drv_grp), - .pin_drv_grp = mt6589_pin_drv, - .n_pin_drv_grps = ARRAY_SIZE(mt6589_pin_drv), - .drv_multibase = true, - .spec_pull_set = mt6589_pull_set, - .dir_offset = 0x0000, - .ies_offset = 0x0100, - .ies_multibase = true, - .pullen_offset = 0x0200, - .pullen_multibase = true, - .smt_offset = 0x0300, - .smt_multibase = true, - .pullsel_offset = 0x0400, - .pullsel_multibase = true, - .dout_offset = 0x0800, - .din_offset = 0x0a00, - .pinmux_offset = 0x0c00, - .spec_pinmux_set = mt6589_pinmux_set, - .type1_start = 114, - .type1_end = 169 + 1, - .port_shf = 4, - .port_mask = 0xf, - .port_align = 4, - .mode_mask = 0xf, - .mode_per_reg = 5, - .mode_shf = 4, - .eint_hw = { - .port_mask = 7, - .ports = 6, - .ap_num = 192, - .db_cnt = 16, - .db_time = debounce_time_mt6795, - }, + .ngrps = ARRAY_SIZE(mtk_pins_mt6589), + .eint_hw = &mt6589_eint_hw, + .gpio_m = 0, + .base_names = mt6589_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt6589_pinctrl_register_base_names), + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_rev1, + .drive_get = mtk_pinconf_drive_get_rev1, + .adv_pull_set = mtk_pinconf_adv_pull_set, + .adv_pull_get = mtk_pinconf_adv_pull_get, }; -static const struct of_device_id mt6589_pctrl_match[] = { +static const struct of_device_id mt6589_pinctrl_match[] = { { .compatible = "mediatek,mt6589-pinctrl", .data = &mt6589_pinctrl_data }, {}, }; -MODULE_DEVICE_TABLE(of, mt6589_pctrl_match); +MODULE_DEVICE_TABLE(of, mt6589_pinctrl_match); -static struct platform_driver mtk_pinctrl_driver = { - .probe = mtk_pctrl_common_probe, +static struct platform_driver mt6589_pinctrl_driver = { + .probe = mtk_paris_pinctrl_probe, .driver = { .name = "mediatek-mt6589-pinctrl", - .of_match_table = mt6589_pctrl_match, - .pm = pm_sleep_ptr(&mtk_eint_pm_ops), + .of_match_table = mt6589_pinctrl_match, }, }; -static int __init mtk_pinctrl_init(void) +static int __init mt6589_pinctrl_init(void) { - return platform_driver_register(&mtk_pinctrl_driver); + return platform_driver_register(&mt6589_pinctrl_driver); } -arch_initcall(mtk_pinctrl_init); +arch_initcall(mt6589_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6589 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index 1ec1ddb317c33e..f5030a9ea40b42 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -272,6 +272,8 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .dout_offset = 0x0400, .din_offset = 0x0500, .pinmux_offset = 0x0600, + .type1_start = 143, + .type1_end = 143, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 9c9689be33be25..77c6ac464e8607 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -292,23 +292,15 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp), .pin_drv_grp = mt8135_pin_drv, .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv), - .drv_multibase = true, .spec_pull_set = spec_pull_set, .dir_offset = 0x0000, - .dir_multibase = true, .ies_offset = 0x0100, - .ies_multibase = true, .pullen_offset = 0x0200, - .pullen_multibase = true, .smt_offset = 0x0300, - .smt_multibase = true, .pullsel_offset = 0x0400, - .pullsel_multibase = true, .dout_offset = 0x0800, - .dout_multibase = true, .din_offset = 0x0A00, .pinmux_offset = 0x0C00, - .pinmux_multibase = true, .type1_start = 34, .type1_end = 149, .port_shf = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 27dfaabbf41ed6..143c2662227252 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -305,6 +305,8 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .dout_offset = 0x0100, .din_offset = 0x0200, .pinmux_offset = 0x0300, + .type1_start = 125, + .type1_end = 125, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index cc1ad89635021b..b214deeafbf1d6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -313,6 +313,8 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .dout_offset = 0x0400, .din_offset = 0x0500, .pinmux_offset = 0x0600, + .type1_start = 135, + .type1_end = 135, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c index a58175cd81de17..c20b9e2e02ddad 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -456,6 +456,8 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { .smt_offset = 0x0470, .pullen_offset = 0x0860, .pullsel_offset = 0x0900, + .type1_start = 145, + .type1_end = 145, .port_shf = 4, .port_mask = 0x1f, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index c91e5f001c1090..abda75d4354e28 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -305,6 +305,8 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .dout_offset = 0x0100, .din_offset = 0x0200, .pinmux_offset = 0x0300, + .type1_start = 125, + .type1_end = 125, .port_shf = 4, .port_mask = 0xf, .port_align = 4, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 4918d38abfc29d..dbe170ac07d338 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -43,6 +43,7 @@ static const struct mtk_drive_desc mtk_drive[] = { [DRV_GRP2] = { 2, 8, 2, 1 }, [DRV_GRP3] = { 2, 8, 2, 2 }, [DRV_GRP4] = { 2, 16, 2, 1 }, + [DRV_GRP5] = { 4, 32, 4, 1 }, }; static void mtk_w32(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 val) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h index 36d2898037dd04..eef342caf56b6a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h @@ -104,6 +104,7 @@ enum { DRV_GRP2, DRV_GRP3, DRV_GRP4, + DRV_GRP5, DRV_GRP_MAX, }; diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index f4abb23bd26a59..7c1c54781c7af1 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -42,15 +42,14 @@ static const char * const mtk_gpio_functions[] = { }; /* - * Some chips (e.g., mt8135) have multiple base addresses for pin configuration. - * When multibase is true and the pin number falls within the specified range - * [type1_start, type1_end), the second base address should be used. + * There are two base address for pull related configuration + * in mt8135, and different GPIO pins use different base address. + * When pin number greater than type1_start and less than type1_end, + * should use the second base address. */ static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, - unsigned long pin, bool multibase) + unsigned long pin) { - if (!multibase) - return pctl->regmap1; if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end) return pctl->regmap2; return pctl->regmap1; @@ -83,8 +82,7 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, else reg_addr = SET_ADDR(reg_addr, pctl); - regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), - reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); return 0; } @@ -102,8 +100,7 @@ static int mtk_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) else reg_addr = CLR_ADDR(reg_addr, pctl); - return regmap_write(mtk_get_regmap(pctl, offset, pctl->devdata->dout_multibase), - reg_addr, bit); + return regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); } static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, @@ -111,7 +108,6 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, { unsigned int reg_addr, offset; unsigned int bit; - bool multibase; /** * Due to some soc are not support ies/smt config, add this special @@ -127,18 +123,12 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) return -EINVAL; - if (arg == PIN_CONFIG_INPUT_ENABLE) - multibase = pctl->devdata->ies_multibase; - else - multibase = pctl->devdata->smt_multibase; - /* * Due to some pins are irregular, their input enable and smt * control register are discontinuous, so we need this special handle. */ if (pctl->devdata->spec_ies_smt_set) { - return pctl->devdata->spec_ies_smt_set( - mtk_get_regmap(pctl, pin, multibase), + return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), pctl->devdata, pin, value, arg); } @@ -154,7 +144,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, else reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); - regmap_write(mtk_get_regmap(pctl, pin, multibase), reg_addr, bit); + regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); return 0; } @@ -239,8 +229,7 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl, shift = pin_drv->bit + drv_grp->low_bit; mask <<= shift; val <<= shift; - return regmap_update_bits( - mtk_get_regmap(pctl, pin, pctl->devdata->drv_multibase), + return regmap_update_bits(mtk_get_regmap(pctl, pin), pin_drv->offset, mask, val); } @@ -325,9 +314,9 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, * the parameter should be "MTK_PUPD_SET_R1R0_00". */ r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00; - ret = pctl->devdata->spec_pull_set( - mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), - pctl->devdata, pin, isup, r1r0); + ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin), + pctl->devdata, pin, isup, + r1r0); if (!ret) return 0; } @@ -345,8 +334,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, pctl->devdata->pullen_offset; reg_pullsel = mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset; - /* MT8365 do not use multibase. */ - ret = pctl->devdata->mt8365_set_clr_mode(pctl->regmap1, + ret = pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), bit, reg_pullen, reg_pullsel, enable, isup); if (ret) @@ -370,10 +358,8 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) + pctl->devdata->pullsel_offset, pctl); - regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullen_multibase), - reg_pullen, bit); - regmap_write(mtk_get_regmap(pctl, pin, pctl->devdata->pullsel_multibase), - reg_pullsel, bit); + regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit); + regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit); return 0; } @@ -724,9 +710,8 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); if (pctl->devdata->spec_pinmux_set) - pctl->devdata->spec_pinmux_set( - mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), - pin, mode); + pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), + pin, mode); reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf) + pctl->devdata->pinmux_offset; @@ -735,9 +720,8 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, bit = pin % pctl->devdata->mode_per_reg; mask <<= (GPIO_MODE_BITS * bit); val = (mode << (GPIO_MODE_BITS * bit)); - return regmap_update_bits( - mtk_get_regmap(pctl, pin, pctl->devdata->pinmux_multibase), - reg_addr, mask, val); + return regmap_update_bits(mtk_get_regmap(pctl, pin), + reg_addr, mask, val); } static const struct mtk_desc_pin * @@ -848,8 +832,7 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) if (pctl->devdata->spec_dir_set) pctl->devdata->spec_dir_set(®_addr, offset); - regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->dir_multibase), - reg_addr, &read_val); + regmap_read(pctl->regmap1, reg_addr, &read_val); if (read_val & bit) return GPIO_LINE_DIRECTION_OUT; @@ -867,8 +850,7 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) pctl->devdata->din_offset; bit = BIT(offset & pctl->devdata->mode_mask); - regmap_read(mtk_get_regmap(pctl, offset, pctl->devdata->din_multibase), - reg_addr, &read_val); + regmap_read(pctl->regmap1, reg_addr, &read_val); return !!(read_val & bit); } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 81793d2973f866..3b96f3dd338d0e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -276,15 +276,6 @@ struct mtk_pinctrl_devdata { unsigned int mode_mask; unsigned int mode_per_reg; unsigned int mode_shf; - bool dir_multibase; - bool ies_multibase; - bool smt_multibase; - bool pullen_multibase; - bool pullsel_multibase; - bool drv_multibase; - bool dout_multibase; - bool din_multibase; - bool pinmux_multibase; }; struct mtk_pinctrl { diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h index 116879d078fb02..234cd196adc37b 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6589.h @@ -1,18 +1,18 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #ifndef __PINCTRL_MTK_MT6589_H #define __PINCTRL_MTK_MT6589_H -#include -#include "pinctrl-mtk-common.h" +#include "pinctrl-paris.h" -static const struct mtk_desc_pin mtk_pins_mt6589[] = { - MTK_PIN(PINCTRL_PIN(0, "GPIO0"), - NULL, "mt6589", +static const struct mtk_pin_desc mtk_pins_mt6589[] = { + MTK_PIN( + 0, "GPIO0", MTK_EINT_FUNCTION(2, 49), + DRV_GRP4, MTK_FUNCTION(0, "GPIO0"), MTK_FUNCTION(1, "MSDC0_DAT7"), MTK_FUNCTION(2, "EINT49"), @@ -22,9 +22,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "SPI1_MO"), MTK_FUNCTION(7, "NALE") ), - MTK_PIN(PINCTRL_PIN(1, "GPIO1"), - NULL, "mt6589", + MTK_PIN( + 1, "GPIO1", MTK_EINT_FUNCTION(2, 48), + DRV_GRP4, MTK_FUNCTION(0, "GPIO1"), MTK_FUNCTION(1, "MSDC0_DAT6"), MTK_FUNCTION(2, "EINT48"), @@ -34,9 +35,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "SPI1_CSN"), MTK_FUNCTION(7, "NCLE") ), - MTK_PIN(PINCTRL_PIN(2, "GPIO2"), - NULL, "mt6589", + MTK_PIN( + 2, "GPIO2", MTK_EINT_FUNCTION(2, 47), + DRV_GRP4, MTK_FUNCTION(0, "GPIO2"), MTK_FUNCTION(1, "MSDC0_DAT5"), MTK_FUNCTION(2, "EINT47"), @@ -46,18 +48,20 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "SPI1_CLK"), MTK_FUNCTION(7, "NLD4") ), - MTK_PIN(PINCTRL_PIN(3, "GPIO3"), - NULL, "mt6589", + MTK_PIN( + 3, "GPIO3", MTK_EINT_FUNCTION(2, 46), + DRV_GRP4, MTK_FUNCTION(0, "GPIO3"), MTK_FUNCTION(1, "MSDC0_DAT4"), MTK_FUNCTION(2, "EINT46"), MTK_FUNCTION(6, "LSCE1B_2X"), MTK_FUNCTION(7, "NLD5") ), - MTK_PIN(PINCTRL_PIN(4, "GPIO4"), - NULL, "mt6589", + MTK_PIN( + 4, "GPIO4", MTK_EINT_FUNCTION(2, 50), + DRV_GRP1, MTK_FUNCTION(0, "GPIO4"), MTK_FUNCTION(1, "MSDC0_RSTB"), MTK_FUNCTION(2, "EINT50"), @@ -66,70 +70,78 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "SPI1_MI"), MTK_FUNCTION(7, "NLD10") ), - MTK_PIN(PINCTRL_PIN(5, "GPIO5"), - NULL, "mt6589", + MTK_PIN( + 5, "GPIO5", MTK_EINT_FUNCTION(2, 41), + DRV_GRP4, MTK_FUNCTION(0, "GPIO5"), MTK_FUNCTION(1, "MSDC0_CMD"), MTK_FUNCTION(2, "EINT41"), MTK_FUNCTION(6, "LRSTB_2X"), MTK_FUNCTION(7, "NRNB") ), - MTK_PIN(PINCTRL_PIN(6, "GPIO6"), - NULL, "mt6589", + MTK_PIN( + 6, "GPIO6", MTK_EINT_FUNCTION(2, 40), + DRV_GRP4, MTK_FUNCTION(0, "GPIO6"), MTK_FUNCTION(1, "MSDC0_CLK"), MTK_FUNCTION(2, "EINT40"), MTK_FUNCTION(6, "LPTE"), MTK_FUNCTION(7, "NREB") ), - MTK_PIN(PINCTRL_PIN(7, "GPIO7"), - NULL, "mt6589", + MTK_PIN( + 7, "GPIO7", MTK_EINT_FUNCTION(2, 45), + DRV_GRP4, MTK_FUNCTION(0, "GPIO7"), MTK_FUNCTION(1, "MSDC0_DAT3"), MTK_FUNCTION(2, "EINT45"), MTK_FUNCTION(6, "LSCE0B_2X"), MTK_FUNCTION(7, "NLD7") ), - MTK_PIN(PINCTRL_PIN(8, "GPIO8"), - NULL, "mt6589", + MTK_PIN( + 8, "GPIO8", MTK_EINT_FUNCTION(2, 44), + DRV_GRP4, MTK_FUNCTION(0, "GPIO8"), MTK_FUNCTION(1, "MSDC0_DAT2"), MTK_FUNCTION(2, "EINT44"), MTK_FUNCTION(6, "LSA0_2X"), MTK_FUNCTION(7, "NLD14") ), - MTK_PIN(PINCTRL_PIN(9, "GPIO9"), - NULL, "mt6589", + MTK_PIN( + 9, "GPIO9", MTK_EINT_FUNCTION(2, 43), + DRV_GRP4, MTK_FUNCTION(0, "GPIO9"), MTK_FUNCTION(1, "MSDC0_DAT1"), MTK_FUNCTION(2, "EINT43"), MTK_FUNCTION(6, "LSCK_2X"), MTK_FUNCTION(7, "NLD11") ), - MTK_PIN(PINCTRL_PIN(10, "GPIO10"), - NULL, "mt6589", + MTK_PIN( + 10, "GPIO10", MTK_EINT_FUNCTION(2, 42), + DRV_GRP4, MTK_FUNCTION(0, "GPIO10"), MTK_FUNCTION(1, "MSDC0_DAT0"), MTK_FUNCTION(2, "EINT42"), MTK_FUNCTION(6, "LSDA_2X") ), - MTK_PIN(PINCTRL_PIN(11, "GPIO11"), - NULL, "mt6589", + MTK_PIN( + 11, "GPIO11", MTK_EINT_FUNCTION(2, 139), + DRV_GRP1, MTK_FUNCTION(0, "GPIO11"), MTK_FUNCTION(1, "NCEB0"), MTK_FUNCTION(2, "EINT139"), MTK_FUNCTION(7, "TESTA_OUT4") ), - MTK_PIN(PINCTRL_PIN(12, "GPIO12"), - NULL, "mt6589", + MTK_PIN( + 12, "GPIO12", MTK_EINT_FUNCTION(2, 140), + DRV_GRP1, MTK_FUNCTION(0, "GPIO12"), MTK_FUNCTION(1, "NCEB1"), MTK_FUNCTION(2, "EINT140"), @@ -138,18 +150,20 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "USB_DRVVBUS"), MTK_FUNCTION(7, "TESTA_OUT5") ), - MTK_PIN(PINCTRL_PIN(13, "GPIO13"), - NULL, "mt6589", + MTK_PIN( + 13, "GPIO13", MTK_EINT_FUNCTION(2, 141), + DRV_GRP1, MTK_FUNCTION(0, "GPIO13"), MTK_FUNCTION(1, "NRNB"), MTK_FUNCTION(2, "EINT141"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[0]"), MTK_FUNCTION(7, "TESTA_OUT6") ), - MTK_PIN(PINCTRL_PIN(14, "GPIO14"), - NULL, "mt6589", + MTK_PIN( + 14, "GPIO14", MTK_EINT_FUNCTION(2, 142), + DRV_GRP1, MTK_FUNCTION(0, "GPIO14"), MTK_FUNCTION(1, "NCLE"), MTK_FUNCTION(2, "EINT142"), @@ -158,9 +172,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "NALE"), MTK_FUNCTION(7, "TESTA_OUT7") ), - MTK_PIN(PINCTRL_PIN(15, "GPIO15"), - NULL, "mt6589", + MTK_PIN( + 15, "GPIO15", MTK_EINT_FUNCTION(2, 143), + DRV_GRP1, MTK_FUNCTION(0, "GPIO15"), MTK_FUNCTION(1, "NALE"), MTK_FUNCTION(2, "EINT143"), @@ -170,9 +185,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "NCLE"), MTK_FUNCTION(7, "TESTA_OUT8") ), - MTK_PIN(PINCTRL_PIN(16, "GPIO16"), - NULL, "mt6589", + MTK_PIN( + 16, "GPIO16", MTK_EINT_FUNCTION(2, 144), + DRV_GRP1, MTK_FUNCTION(0, "GPIO16"), MTK_FUNCTION(1, "NREB"), MTK_FUNCTION(2, "EINT144"), @@ -182,9 +198,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[1]"), MTK_FUNCTION(7, "TESTA_OUT9") ), - MTK_PIN(PINCTRL_PIN(17, "GPIO17"), - NULL, "mt6589", + MTK_PIN( + 17, "GPIO17", MTK_EINT_FUNCTION(2, 145), + DRV_GRP1, MTK_FUNCTION(0, "GPIO17"), MTK_FUNCTION(1, "NWEB"), MTK_FUNCTION(2, "EINT145"), @@ -194,9 +211,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[2]"), MTK_FUNCTION(7, "TESTA_OUT10") ), - MTK_PIN(PINCTRL_PIN(18, "GPIO18"), - NULL, "mt6589", + MTK_PIN( + 18, "GPIO18", MTK_EINT_FUNCTION(2, 146), + DRV_GRP1, MTK_FUNCTION(0, "GPIO18"), MTK_FUNCTION(1, "NLD0"), MTK_FUNCTION(2, "EINT146"), @@ -206,9 +224,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DAC_CK"), MTK_FUNCTION(7, "TESTA_OUT11") ), - MTK_PIN(PINCTRL_PIN(19, "GPIO19"), - NULL, "mt6589", + MTK_PIN( + 19, "GPIO19", MTK_EINT_FUNCTION(2, 147), + DRV_GRP1, MTK_FUNCTION(0, "GPIO19"), MTK_FUNCTION(1, "NLD1"), MTK_FUNCTION(2, "EINT147"), @@ -218,9 +237,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DAC_WS"), MTK_FUNCTION(7, "TESTA_OUT12") ), - MTK_PIN(PINCTRL_PIN(20, "GPIO20"), - NULL, "mt6589", + MTK_PIN( + 20, "GPIO20", MTK_EINT_FUNCTION(2, 148), + DRV_GRP1, MTK_FUNCTION(0, "GPIO20"), MTK_FUNCTION(1, "NLD2"), MTK_FUNCTION(2, "EINT148"), @@ -230,9 +250,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DAC_DAT_OUT"), MTK_FUNCTION(7, "TESTA_OUT13") ), - MTK_PIN(PINCTRL_PIN(21, "GPIO21"), - NULL, "mt6589", + MTK_PIN( + 21, "GPIO21", MTK_EINT_FUNCTION(2, 149), + DRV_GRP1, MTK_FUNCTION(0, "GPIO21"), MTK_FUNCTION(1, "NLD3"), MTK_FUNCTION(2, "EINT149"), @@ -241,9 +262,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[3]"), MTK_FUNCTION(7, "TESTA_OUT14") ), - MTK_PIN(PINCTRL_PIN(22, "GPIO22"), - NULL, "mt6589", + MTK_PIN( + 22, "GPIO22", MTK_EINT_FUNCTION(2, 150), + DRV_GRP1, MTK_FUNCTION(0, "GPIO22"), MTK_FUNCTION(1, "NLD4"), MTK_FUNCTION(2, "EINT150"), @@ -253,9 +275,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_DAI_RX_GPIO"), MTK_FUNCTION(7, "TESTA_OUT15") ), - MTK_PIN(PINCTRL_PIN(23, "GPIO23"), - NULL, "mt6589", + MTK_PIN( + 23, "GPIO23", MTK_EINT_FUNCTION(2, 151), + DRV_GRP1, MTK_FUNCTION(0, "GPIO23"), MTK_FUNCTION(1, "NLD5"), MTK_FUNCTION(2, "EINT151"), @@ -264,9 +287,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[4]"), MTK_FUNCTION(7, "TESTA_OUT16") ), - MTK_PIN(PINCTRL_PIN(24, "GPIO24"), - NULL, "mt6589", + MTK_PIN( + 24, "GPIO24", MTK_EINT_FUNCTION(2, 152), + DRV_GRP1, MTK_FUNCTION(0, "GPIO24"), MTK_FUNCTION(1, "NLD6"), MTK_FUNCTION(2, "EINT152"), @@ -275,9 +299,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[5]"), MTK_FUNCTION(7, "TESTA_OUT17") ), - MTK_PIN(PINCTRL_PIN(25, "GPIO25"), - NULL, "mt6589", + MTK_PIN( + 25, "GPIO25", MTK_EINT_FUNCTION(2, 153), + DRV_GRP1, MTK_FUNCTION(0, "GPIO25"), MTK_FUNCTION(1, "NLD7"), MTK_FUNCTION(2, "EINT153"), @@ -286,9 +311,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[6]"), MTK_FUNCTION(7, "TESTA_OUT18") ), - MTK_PIN(PINCTRL_PIN(26, "GPIO26"), - NULL, "mt6589", + MTK_PIN( + 26, "GPIO26", MTK_EINT_FUNCTION(2, 154), + DRV_GRP1, MTK_FUNCTION(0, "GPIO26"), MTK_FUNCTION(1, "NLD8"), MTK_FUNCTION(2, "EINT154"), @@ -297,9 +323,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[7]"), MTK_FUNCTION(7, "TESTA_OUT19") ), - MTK_PIN(PINCTRL_PIN(27, "GPIO27"), - NULL, "mt6589", + MTK_PIN( + 27, "GPIO27", MTK_EINT_FUNCTION(2, 155), + DRV_GRP1, MTK_FUNCTION(0, "GPIO27"), MTK_FUNCTION(1, "NLD9"), MTK_FUNCTION(2, "EINT155"), @@ -309,9 +336,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[8]"), MTK_FUNCTION(7, "TESTA_OUT20") ), - MTK_PIN(PINCTRL_PIN(28, "GPIO28"), - NULL, "mt6589", + MTK_PIN( + 28, "GPIO28", MTK_EINT_FUNCTION(2, 156), + DRV_GRP1, MTK_FUNCTION(0, "GPIO28"), MTK_FUNCTION(1, "NLD10"), MTK_FUNCTION(2, "EINT156"), @@ -321,9 +349,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[9]"), MTK_FUNCTION(7, "TESTA_OUT21") ), - MTK_PIN(PINCTRL_PIN(29, "GPIO29"), - NULL, "mt6589", + MTK_PIN( + 29, "GPIO29", MTK_EINT_FUNCTION(2, 157), + DRV_GRP1, MTK_FUNCTION(0, "GPIO29"), MTK_FUNCTION(1, "NLD11"), MTK_FUNCTION(2, "EINT157"), @@ -333,9 +362,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[10]"), MTK_FUNCTION(7, "TESTA_OUT22") ), - MTK_PIN(PINCTRL_PIN(30, "GPIO30"), - NULL, "mt6589", + MTK_PIN( + 30, "GPIO30", MTK_EINT_FUNCTION(2, 158), + DRV_GRP1, MTK_FUNCTION(0, "GPIO30"), MTK_FUNCTION(1, "NLD12"), MTK_FUNCTION(2, "EINT158"), @@ -345,9 +375,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[11]"), MTK_FUNCTION(7, "TESTA_OUT23") ), - MTK_PIN(PINCTRL_PIN(31, "GPIO31"), - NULL, "mt6589", + MTK_PIN( + 31, "GPIO31", MTK_EINT_FUNCTION(2, 159), + DRV_GRP1, MTK_FUNCTION(0, "GPIO31"), MTK_FUNCTION(1, "NLD13"), MTK_FUNCTION(2, "EINT159"), @@ -357,9 +388,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[12]"), MTK_FUNCTION(7, "TESTA_OUT24") ), - MTK_PIN(PINCTRL_PIN(32, "GPIO32"), - NULL, "mt6589", + MTK_PIN( + 32, "GPIO32", MTK_EINT_FUNCTION(2, 160), + DRV_GRP1, MTK_FUNCTION(0, "GPIO32"), MTK_FUNCTION(1, "NLD14"), MTK_FUNCTION(2, "EINT160"), @@ -369,9 +401,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[13]"), MTK_FUNCTION(7, "TESTA_OUT25") ), - MTK_PIN(PINCTRL_PIN(33, "GPIO33"), - NULL, "mt6589", + MTK_PIN( + 33, "GPIO33", MTK_EINT_FUNCTION(2, 161), + DRV_GRP1, MTK_FUNCTION(0, "GPIO33"), MTK_FUNCTION(1, "NLD15"), MTK_FUNCTION(2, "EINT161"), @@ -381,9 +414,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[14]"), MTK_FUNCTION(7, "TESTA_OUT26") ), - MTK_PIN(PINCTRL_PIN(34, "GPIO34"), - NULL, "mt6589", - MTK_EINT_FUNCTION(6, 0), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(1, 0), + DRV_GRP3, MTK_FUNCTION(0, "GPIO34"), MTK_FUNCTION(1, "EINT0"), MTK_FUNCTION(2, "PWM1"), @@ -392,9 +426,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_EINT1"), MTK_FUNCTION(7, "USB_SCL") ), - MTK_PIN(PINCTRL_PIN(35, "GPIO35"), - NULL, "mt6589", + MTK_PIN( + 35, "GPIO35", MTK_EINT_FUNCTION(1, 1), + DRV_GRP3, MTK_FUNCTION(0, "GPIO35"), MTK_FUNCTION(1, "EINT1"), MTK_FUNCTION(2, "PWM2"), @@ -403,9 +438,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_EINT2"), MTK_FUNCTION(7, "USB_SDA") ), - MTK_PIN(PINCTRL_PIN(36, "GPIO36"), - NULL, "mt6589", + MTK_PIN( + 36, "GPIO36", MTK_EINT_FUNCTION(1, 2), + DRV_GRP3, MTK_FUNCTION(0, "GPIO36"), MTK_FUNCTION(1, "EINT2"), MTK_FUNCTION(2, "PWM3"), @@ -413,17 +449,19 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "SRCLKENAI2"), MTK_FUNCTION(6, "MD1_EINT3") ), - MTK_PIN(PINCTRL_PIN(37, "GPIO37"), - NULL, "mt6589", + MTK_PIN( + 37, "GPIO37", MTK_EINT_FUNCTION(1, 3), + DRV_GRP3, MTK_FUNCTION(0, "GPIO37"), MTK_FUNCTION(1, "EINT3"), MTK_FUNCTION(6, "MD1_EINT5"), MTK_FUNCTION(7, "EXT_26M_CK") ), - MTK_PIN(PINCTRL_PIN(38, "GPIO38"), - NULL, "mt6589", + MTK_PIN( + 38, "GPIO38", MTK_EINT_FUNCTION(1, 4), + DRV_GRP3, MTK_FUNCTION(0, "GPIO38"), MTK_FUNCTION(1, "EINT4"), MTK_FUNCTION(2, "PWM4"), @@ -432,44 +470,50 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_DRVVBUS"), MTK_FUNCTION(6, "MD1_EINT4") ), - MTK_PIN(PINCTRL_PIN(39, "GPIO39"), - NULL, "mt6589", + MTK_PIN( + 39, "GPIO39", MTK_EINT_FUNCTION(2, 29), + DRV_GRP1, MTK_FUNCTION(0, "GPIO39"), MTK_FUNCTION(1, "PWRAP_SPIDI"), MTK_FUNCTION(2, "EINT29") ), - MTK_PIN(PINCTRL_PIN(40, "GPIO40"), - NULL, "mt6589", + MTK_PIN( + 40, "GPIO40", MTK_EINT_FUNCTION(2, 28), + DRV_GRP1, MTK_FUNCTION(0, "GPIO40"), MTK_FUNCTION(1, "PWRAP_SPIDO"), MTK_FUNCTION(2, "EINT28") ), - MTK_PIN(PINCTRL_PIN(41, "GPIO41"), - NULL, "mt6589", + MTK_PIN( + 41, "GPIO41", MTK_EINT_FUNCTION(2, 27), + DRV_GRP1, MTK_FUNCTION(0, "GPIO41"), MTK_FUNCTION(1, "PWRAP_SPICS_B_I"), MTK_FUNCTION(2, "EINT27") ), - MTK_PIN(PINCTRL_PIN(42, "GPIO42"), - NULL, "mt6589", + MTK_PIN( + 42, "GPIO42", MTK_EINT_FUNCTION(2, 26), + DRV_GRP1, MTK_FUNCTION(0, "GPIO42"), MTK_FUNCTION(1, "PWRAP_SPICK_I"), MTK_FUNCTION(2, "EINT26") ), - MTK_PIN(PINCTRL_PIN(43, "GPIO43"), - NULL, "mt6589", + MTK_PIN( + 43, "GPIO43", MTK_EINT_FUNCTION(2, 25), + DRV_GRP1, MTK_FUNCTION(0, "GPIO43"), MTK_FUNCTION(1, "PWRAP_EVENT_IN"), MTK_FUNCTION(2, "EINT25") ), - MTK_PIN(PINCTRL_PIN(44, "GPIO44"), - NULL, "mt6589", + MTK_PIN( + 44, "GPIO44", MTK_EINT_FUNCTION(2, 30), + DRV_GRP1, MTK_FUNCTION(0, "GPIO44"), MTK_FUNCTION(1, "MD1_SIM1_SCLK"), MTK_FUNCTION(2, "EINT30"), @@ -478,9 +522,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM2_SCLK"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[15]") ), - MTK_PIN(PINCTRL_PIN(45, "GPIO45"), - NULL, "mt6589", + MTK_PIN( + 45, "GPIO45", MTK_EINT_FUNCTION(2, 31), + DRV_GRP1, MTK_FUNCTION(0, "GPIO45"), MTK_FUNCTION(1, "MD1_SIM1_SRST"), MTK_FUNCTION(2, "EINT31"), @@ -489,9 +534,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM2_SRST"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[16]") ), - MTK_PIN(PINCTRL_PIN(46, "GPIO46"), - NULL, "mt6589", + MTK_PIN( + 46, "GPIO46", MTK_EINT_FUNCTION(2, 32), + DRV_GRP1, MTK_FUNCTION(0, "GPIO46"), MTK_FUNCTION(1, "MD1_SIM1_SDAT"), MTK_FUNCTION(2, "EINT32"), @@ -500,9 +546,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM2_SDAT"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[17]") ), - MTK_PIN(PINCTRL_PIN(47, "GPIO47"), - NULL, "mt6589", + MTK_PIN( + 47, "GPIO47", MTK_EINT_FUNCTION(2, 33), + DRV_GRP1, MTK_FUNCTION(0, "GPIO47"), MTK_FUNCTION(1, "MD1_SIM2_SCLK"), MTK_FUNCTION(2, "EINT33"), @@ -511,9 +558,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM1_SCLK"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[18]") ), - MTK_PIN(PINCTRL_PIN(48, "GPIO48"), - NULL, "mt6589", + MTK_PIN( + 48, "GPIO48", MTK_EINT_FUNCTION(2, 34), + DRV_GRP1, MTK_FUNCTION(0, "GPIO48"), MTK_FUNCTION(1, "MD1_SIM2_SRST"), MTK_FUNCTION(2, "EINT34"), @@ -522,9 +570,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM1_SRST"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[19]") ), - MTK_PIN(PINCTRL_PIN(49, "GPIO49"), - NULL, "mt6589", + MTK_PIN( + 49, "GPIO49", MTK_EINT_FUNCTION(2, 35), + DRV_GRP1, MTK_FUNCTION(0, "GPIO49"), MTK_FUNCTION(1, "MD1_SIM2_SDAT"), MTK_FUNCTION(2, "EINT35"), @@ -533,147 +582,166 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_SIM1_SDAT"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[20]") ), - MTK_PIN(PINCTRL_PIN(50, "GPIO50"), - NULL, "mt6589", + MTK_PIN( + 50, "GPIO50", MTK_EINT_FUNCTION(2, 19), + DRV_GRP1, MTK_FUNCTION(0, "GPIO50"), MTK_FUNCTION(1, "ADC_CK"), MTK_FUNCTION(2, "EINT19") ), - MTK_PIN(PINCTRL_PIN(51, "GPIO51"), - NULL, "mt6589", + MTK_PIN( + 51, "GPIO51", MTK_EINT_FUNCTION(2, 21), + DRV_GRP1, MTK_FUNCTION(0, "GPIO51"), MTK_FUNCTION(1, "ADC_WS"), MTK_FUNCTION(2, "EINT21") ), - MTK_PIN(PINCTRL_PIN(52, "GPIO52"), - NULL, "mt6589", + MTK_PIN( + 52, "GPIO52", MTK_EINT_FUNCTION(2, 20), + DRV_GRP1, MTK_FUNCTION(0, "GPIO52"), MTK_FUNCTION(1, "ADC_DAT_IN"), MTK_FUNCTION(2, "EINT20") ), - MTK_PIN(PINCTRL_PIN(53, "GPIO53"), - NULL, "mt6589", + MTK_PIN( + 53, "GPIO53", MTK_EINT_FUNCTION(2, 22), + DRV_GRP1, MTK_FUNCTION(0, "GPIO53"), MTK_FUNCTION(1, "DAC_CK"), MTK_FUNCTION(2, "EINT22") ), - MTK_PIN(PINCTRL_PIN(54, "GPIO54"), - NULL, "mt6589", + MTK_PIN( + 54, "GPIO54", MTK_EINT_FUNCTION(2, 24), + DRV_GRP1, MTK_FUNCTION(0, "GPIO54"), MTK_FUNCTION(1, "DAC_WS"), MTK_FUNCTION(2, "EINT24") ), - MTK_PIN(PINCTRL_PIN(55, "GPIO55"), - NULL, "mt6589", + MTK_PIN( + 55, "GPIO55", MTK_EINT_FUNCTION(2, 23), + DRV_GRP1, MTK_FUNCTION(0, "GPIO55"), MTK_FUNCTION(1, "DAC_DAT_OUT"), MTK_FUNCTION(2, "EINT23") ), - MTK_PIN(PINCTRL_PIN(56, "GPIO56"), - NULL, "mt6589", + MTK_PIN( + 56, "GPIO56", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_FIXED, /* maybe */ MTK_FUNCTION(0, "GPIO56"), MTK_FUNCTION(1, "RTC32K_CK") ), - MTK_PIN(PINCTRL_PIN(57, "GPIO57"), - NULL, "mt6589", + MTK_PIN( + 57, "GPIO57", MTK_EINT_FUNCTION(2, 34), + DRV_GRP3, MTK_FUNCTION(0, "GPIO57"), MTK_FUNCTION(1, "IDDIG"), MTK_FUNCTION(2, "EINT34") ), - MTK_PIN(PINCTRL_PIN(58, "GPIO58"), - NULL, "mt6589", + MTK_PIN( + 58, "GPIO58", MTK_EINT_FUNCTION(2, 36), + DRV_GRP1, MTK_FUNCTION(0, "GPIO58"), MTK_FUNCTION(1, "WATCHDOG"), MTK_FUNCTION(2, "EINT36") ), - MTK_PIN(PINCTRL_PIN(59, "GPIO59"), - NULL, "mt6589", + MTK_PIN( + 59, "GPIO59", MTK_EINT_FUNCTION(2, 38), + DRV_GRP1, MTK_FUNCTION(0, "GPIO59"), MTK_FUNCTION(1, "SRCLKENA"), MTK_FUNCTION(2, "EINT38") ), - MTK_PIN(PINCTRL_PIN(60, "GPIO60"), - NULL, "mt6589", + MTK_PIN( + 60, "GPIO60", MTK_EINT_FUNCTION(2, 37), + DRV_GRP1, MTK_FUNCTION(0, "GPIO60"), MTK_FUNCTION(1, "SRCVOLTEN"), MTK_FUNCTION(2, "EINT37") ), - MTK_PIN(PINCTRL_PIN(61, "GPIO61"), - NULL, "mt6589", + MTK_PIN( + 61, "GPIO61", MTK_EINT_FUNCTION(2, 188), + DRV_GRP1, MTK_FUNCTION(0, "GPIO61"), MTK_FUNCTION(1, "JTCK"), MTK_FUNCTION(2, "EINT188"), MTK_FUNCTION(3, "DSP1_ICK"), MTK_FUNCTION(7, "MD2_TCK_PAD") ), - MTK_PIN(PINCTRL_PIN(62, "GPIO62"), - NULL, "mt6589", + MTK_PIN( + 62, "GPIO62", MTK_EINT_FUNCTION(2, 190), + DRV_GRP1, MTK_FUNCTION(0, "GPIO62"), MTK_FUNCTION(1, "JTDO"), MTK_FUNCTION(2, "EINT190"), MTK_FUNCTION(3, "DSP2_IMS"), MTK_FUNCTION(7, "MD2_TDO_PAD") ), - MTK_PIN(PINCTRL_PIN(63, "GPIO63"), - NULL, "mt6589", + MTK_PIN( + 63, "GPIO63", MTK_EINT_FUNCTION(2, 0), + DRV_GRP1, MTK_FUNCTION(0, "GPIO63"), MTK_FUNCTION(1, "JTRST_B"), MTK_FUNCTION(2, "EINT0"), MTK_FUNCTION(3, "DSP2_ICK"), MTK_FUNCTION(7, "MD2_NTRST_PAD") ), - MTK_PIN(PINCTRL_PIN(64, "GPIO64"), - NULL, "mt6589", + MTK_PIN( + 64, "GPIO64", MTK_EINT_FUNCTION(2, 189), + DRV_GRP1, MTK_FUNCTION(0, "GPIO64"), MTK_FUNCTION(1, "JTDI"), MTK_FUNCTION(2, "EINT189"), MTK_FUNCTION(3, "DSP1_IMS"), MTK_FUNCTION(7, "MD2_TDI_PAD") ), - MTK_PIN(PINCTRL_PIN(65, "GPIO65"), - NULL, "mt6589", + MTK_PIN( + 65, "GPIO65", MTK_EINT_FUNCTION(2, 187), + DRV_GRP1, MTK_FUNCTION(0, "GPIO65"), MTK_FUNCTION(1, "JRTCK"), MTK_FUNCTION(2, "EINT187"), MTK_FUNCTION(3, "DSP1_ID"), MTK_FUNCTION(7, "MD2_RTCK_PAD") ), - MTK_PIN(PINCTRL_PIN(66, "GPIO66"), - NULL, "mt6589", + MTK_PIN( + 66, "GPIO66", MTK_EINT_FUNCTION(2, 191), + DRV_GRP1, MTK_FUNCTION(0, "GPIO66"), MTK_FUNCTION(1, "JTMS"), MTK_FUNCTION(2, "EINT191"), MTK_FUNCTION(3, "DSP2_ID"), MTK_FUNCTION(7, "MD2_TMS_PAD") ), - MTK_PIN(PINCTRL_PIN(67, "GPIO67"), - NULL, "mt6589", + MTK_PIN( + 67, "GPIO67", MTK_EINT_FUNCTION(2, 97), + DRV_FIXED, MTK_FUNCTION(0, "GPIO67"), MTK_FUNCTION(1, "SDA3"), MTK_FUNCTION(2, "EINT97"), MTK_FUNCTION(7, "A_FUNC_DIN[13]") ), - MTK_PIN(PINCTRL_PIN(68, "GPIO68"), - NULL, "mt6589", + MTK_PIN( + 68, "GPIO68", MTK_EINT_FUNCTION(2, 96), + DRV_FIXED, MTK_FUNCTION(0, "GPIO68"), MTK_FUNCTION(1, "SCL3"), MTK_FUNCTION(2, "EINT96"), @@ -681,9 +749,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "PWM6"), MTK_FUNCTION(7, "A_FUNC_DIN[14]") ), - MTK_PIN(PINCTRL_PIN(69, "GPIO69"), - NULL, "mt6589", + MTK_PIN( + 69, "GPIO69", MTK_EINT_FUNCTION(2, 83), + DRV_GRP1, MTK_FUNCTION(0, "GPIO69"), MTK_FUNCTION(1, "URXD2"), MTK_FUNCTION(2, "EINT83"), @@ -693,9 +762,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "UTXD2"), MTK_FUNCTION(7, "MD1_EINT4") ), - MTK_PIN(PINCTRL_PIN(70, "GPIO70"), - NULL, "mt6589", + MTK_PIN( + 70, "GPIO70", MTK_EINT_FUNCTION(2, 82), + DRV_GRP1, MTK_FUNCTION(0, "GPIO70"), MTK_FUNCTION(1, "UTXD2"), MTK_FUNCTION(2, "EINT82"), @@ -705,9 +775,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "URXD2"), MTK_FUNCTION(7, "MD1_EINT3") ), - MTK_PIN(PINCTRL_PIN(71, "GPIO71"), - NULL, "mt6589", + MTK_PIN( + 71, "GPIO71", MTK_EINT_FUNCTION(2, 84), + DRV_GRP1, MTK_FUNCTION(0, "GPIO71"), MTK_FUNCTION(1, "UCTS2"), MTK_FUNCTION(2, "EINT84"), @@ -717,9 +788,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "URTS2"), MTK_FUNCTION(7, "MD2_EINT1") ), - MTK_PIN(PINCTRL_PIN(72, "GPIO72"), - NULL, "mt6589", + MTK_PIN( + 72, "GPIO72", MTK_EINT_FUNCTION(2, 85), + DRV_GRP1, MTK_FUNCTION(0, "GPIO72"), MTK_FUNCTION(1, "URTS2"), MTK_FUNCTION(2, "EINT85"), @@ -729,9 +801,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "UCTS2"), MTK_FUNCTION(7, "MD2_EINT2") ), - MTK_PIN(PINCTRL_PIN(73, "GPIO73"), - NULL, "mt6589", + MTK_PIN( + 73, "GPIO73", MTK_EINT_FUNCTION(2, 73), + DRV_GRP1, MTK_FUNCTION(0, "GPIO73"), MTK_FUNCTION(1, "PWM1"), MTK_FUNCTION(2, "EINT73"), @@ -741,9 +814,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DISP_PWM"), MTK_FUNCTION(7, "MD2_TCK_PAD") ), - MTK_PIN(PINCTRL_PIN(74, "GPIO74"), - NULL, "mt6589", + MTK_PIN( + 74, "GPIO74", MTK_EINT_FUNCTION(2, 74), + DRV_GRP1, MTK_FUNCTION(0, "GPIO74"), MTK_FUNCTION(1, "PWM2"), MTK_FUNCTION(2, "EINT74"), @@ -753,9 +827,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DISP_PWM"), MTK_FUNCTION(7, "MD2_RTCK_PAD") ), - MTK_PIN(PINCTRL_PIN(75, "GPIO75"), - NULL, "mt6589", + MTK_PIN( + 75, "GPIO75", MTK_EINT_FUNCTION(2, 75), + DRV_GRP1, MTK_FUNCTION(0, "GPIO75"), MTK_FUNCTION(1, "PWM3"), MTK_FUNCTION(2, "EINT75"), @@ -765,9 +840,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DISP_PWM"), MTK_FUNCTION(7, "MD2_NTRST_PAD") ), - MTK_PIN(PINCTRL_PIN(76, "GPIO76"), - NULL, "mt6589", + MTK_PIN( + 76, "GPIO76", MTK_EINT_FUNCTION(2, 76), + DRV_GRP1, MTK_FUNCTION(0, "GPIO76"), MTK_FUNCTION(1, "PWM4"), MTK_FUNCTION(2, "EINT76"), @@ -776,9 +852,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "DISP_PWM"), MTK_FUNCTION(7, "MD2_TMS_PAD") ), - MTK_PIN(PINCTRL_PIN(77, "GPIO77"), - NULL, "mt6589", + MTK_PIN( + 77, "GPIO77", MTK_EINT_FUNCTION(2, 79), + DRV_GRP1, MTK_FUNCTION(0, "GPIO77"), MTK_FUNCTION(1, "URXD1"), MTK_FUNCTION(2, "EINT79"), @@ -788,9 +865,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "UTXD1"), MTK_FUNCTION(7, "MD2_TDO_PAD") ), - MTK_PIN(PINCTRL_PIN(78, "GPIO78"), - NULL, "mt6589", + MTK_PIN( + 78, "GPIO78", MTK_EINT_FUNCTION(2, 78), + DRV_GRP1, MTK_FUNCTION(0, "GPIO78"), MTK_FUNCTION(1, "UTXD1"), MTK_FUNCTION(2, "EINT78"), @@ -800,9 +878,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "URXD1"), MTK_FUNCTION(7, "MD2_TDI_PAD") ), - MTK_PIN(PINCTRL_PIN(79, "GPIO79"), - NULL, "mt6589", + MTK_PIN( + 79, "GPIO79", MTK_EINT_FUNCTION(2, 80), + DRV_GRP1, MTK_FUNCTION(0, "GPIO79"), MTK_FUNCTION(1, "UCTS1"), MTK_FUNCTION(2, "EINT80"), @@ -812,9 +891,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "URTS1"), MTK_FUNCTION(7, "MD1_EINT1") ), - MTK_PIN(PINCTRL_PIN(80, "GPIO80"), - NULL, "mt6589", + MTK_PIN( + 80, "GPIO80", MTK_EINT_FUNCTION(2, 81), + DRV_GRP1, MTK_FUNCTION(0, "GPIO80"), MTK_FUNCTION(1, "URTS1"), MTK_FUNCTION(2, "EINT81"), @@ -824,9 +904,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "UCTS1"), MTK_FUNCTION(7, "MD1_EINT2") ), - MTK_PIN(PINCTRL_PIN(81, "GPIO81"), - NULL, "mt6589", + MTK_PIN( + 81, "GPIO81", MTK_EINT_FUNCTION(2, 89), + DRV_GRP1, MTK_FUNCTION(0, "GPIO81"), MTK_FUNCTION(1, "URXD4"), MTK_FUNCTION(2, "EINT89"), @@ -836,9 +917,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "UTXD4"), MTK_FUNCTION(7, "MD2_EINT5") ), - MTK_PIN(PINCTRL_PIN(82, "GPIO82"), - NULL, "mt6589", + MTK_PIN( + 82, "GPIO82", MTK_EINT_FUNCTION(2, 88), + DRV_GRP1, MTK_FUNCTION(0, "GPIO82"), MTK_FUNCTION(1, "UTXD4"), MTK_FUNCTION(2, "EINT88"), @@ -848,9 +930,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "URXD4"), MTK_FUNCTION(7, "MD1_EINT5") ), - MTK_PIN(PINCTRL_PIN(83, "GPIO83"), - NULL, "mt6589", + MTK_PIN( + 83, "GPIO83", MTK_EINT_FUNCTION(2, 1), + DRV_GRP1, MTK_FUNCTION(0, "GPIO83"), MTK_FUNCTION(1, "DUAL_BPI1_BUS0"), MTK_FUNCTION(2, "EINT1"), @@ -858,9 +941,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[0]"), MTK_FUNCTION(7, "A_FUNC_DIN[31]") ), - MTK_PIN(PINCTRL_PIN(84, "GPIO84"), - NULL, "mt6589", + MTK_PIN( + 84, "GPIO84", MTK_EINT_FUNCTION(2, 2), + DRV_GRP1, MTK_FUNCTION(0, "GPIO84"), MTK_FUNCTION(1, "DUAL_BPI1_BUS1"), MTK_FUNCTION(2, "EINT2"), @@ -868,9 +952,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[1]"), MTK_FUNCTION(7, "A_FUNC_DIN[30]") ), - MTK_PIN(PINCTRL_PIN(85, "GPIO85"), - NULL, "mt6589", + MTK_PIN( + 85, "GPIO85", MTK_EINT_FUNCTION(2, 3), + DRV_GRP1, MTK_FUNCTION(0, "GPIO85"), MTK_FUNCTION(1, "DUAL_BPI1_BUS2"), MTK_FUNCTION(2, "EINT3"), @@ -878,9 +963,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[2]"), MTK_FUNCTION(7, "A_FUNC_DIN[29]") ), - MTK_PIN(PINCTRL_PIN(86, "GPIO86"), - NULL, "mt6589", + MTK_PIN( + 86, "GPIO86", MTK_EINT_FUNCTION(2, 4), + DRV_GRP1, MTK_FUNCTION(0, "GPIO86"), MTK_FUNCTION(1, "DUAL_BPI1_BUS3"), MTK_FUNCTION(2, "EINT4"), @@ -888,9 +974,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[3]"), MTK_FUNCTION(7, "A_FUNC_DIN[28]") ), - MTK_PIN(PINCTRL_PIN(87, "GPIO87"), - NULL, "mt6589", + MTK_PIN( + 87, "GPIO87", MTK_EINT_FUNCTION(2, 5), + DRV_GRP1, MTK_FUNCTION(0, "GPIO87"), MTK_FUNCTION(1, "DUAL_BPI1_BUS4"), MTK_FUNCTION(2, "EINT5"), @@ -898,9 +985,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[4]"), MTK_FUNCTION(7, "A_FUNC_DIN[27]") ), - MTK_PIN(PINCTRL_PIN(88, "GPIO88"), - NULL, "mt6589", + MTK_PIN( + 88, "GPIO88", MTK_EINT_FUNCTION(2, 6), + DRV_GRP1, MTK_FUNCTION(0, "GPIO88"), MTK_FUNCTION(1, "DUAL_BPI1_BUS5"), MTK_FUNCTION(2, "EINT6"), @@ -908,9 +996,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[5]"), MTK_FUNCTION(7, "A_FUNC_DIN[26]") ), - MTK_PIN(PINCTRL_PIN(89, "GPIO89"), - NULL, "mt6589", + MTK_PIN( + 89, "GPIO89", MTK_EINT_FUNCTION(2, 7), + DRV_GRP1, MTK_FUNCTION(0, "GPIO89"), MTK_FUNCTION(1, "DUAL_BPI1_BUS6"), MTK_FUNCTION(2, "EINT7"), @@ -918,9 +1007,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[6]"), MTK_FUNCTION(7, "A_FUNC_DIN[25]") ), - MTK_PIN(PINCTRL_PIN(90, "GPIO90"), - NULL, "mt6589", + MTK_PIN( + 90, "GPIO90", MTK_EINT_FUNCTION(2, 8), + DRV_GRP1, MTK_FUNCTION(0, "GPIO90"), MTK_FUNCTION(1, "DUAL_BPI1_BUS7"), MTK_FUNCTION(2, "EINT8"), @@ -930,9 +1020,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "USB_DRVVBUS"), MTK_FUNCTION(7, "A_FUNC_DIN[24]") ), - MTK_PIN(PINCTRL_PIN(91, "GPIO91"), - NULL, "mt6589", + MTK_PIN( + 91, "GPIO91", MTK_EINT_FUNCTION(2, 9), + DRV_GRP1, MTK_FUNCTION(0, "GPIO91"), MTK_FUNCTION(1, "DUAL_BPI1_BUS8"), MTK_FUNCTION(2, "EINT9"), @@ -940,9 +1031,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[8]"), MTK_FUNCTION(7, "A_FUNC_DIN[23]") ), - MTK_PIN(PINCTRL_PIN(92, "GPIO92"), - NULL, "mt6589", + MTK_PIN( + 92, "GPIO92", MTK_EINT_FUNCTION(2, 10), + DRV_GRP1, MTK_FUNCTION(0, "GPIO92"), MTK_FUNCTION(1, "DUAL_BPI1_BUS9"), MTK_FUNCTION(2, "EINT10"), @@ -950,54 +1042,60 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[9]"), MTK_FUNCTION(7, "A_FUNC_DIN[22]") ), - MTK_PIN(PINCTRL_PIN(93, "GPIO93"), - NULL, "mt6589", + MTK_PIN( + 93, "GPIO93", MTK_EINT_FUNCTION(2, 11), + DRV_GRP1, MTK_FUNCTION(0, "GPIO93"), MTK_FUNCTION(1, "DUAL_BPI1_BUS10"), MTK_FUNCTION(2, "EINT11"), MTK_FUNCTION(5, "USB_TEST_IO[10]"), MTK_FUNCTION(7, "A_FUNC_DIN[21]") ), - MTK_PIN(PINCTRL_PIN(94, "GPIO94"), - NULL, "mt6589", + MTK_PIN( + 94, "GPIO94", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO94"), MTK_FUNCTION(1, "DUAL_BPI1_BUS11"), MTK_FUNCTION(3, "BPI2_BUS11"), MTK_FUNCTION(5, "USB_TEST_IO[11]"), MTK_FUNCTION(7, "A_FUNC_DOUT[7]") ), - MTK_PIN(PINCTRL_PIN(95, "GPIO95"), - NULL, "mt6589", + MTK_PIN( + 95, "GPIO95", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO95"), MTK_FUNCTION(1, "DUAL_BPI1_BUS12"), MTK_FUNCTION(3, "BPI2_BUS12"), MTK_FUNCTION(5, "USB_TEST_IO[12]"), MTK_FUNCTION(7, "A_FUNC_DOUT[6]") ), - MTK_PIN(PINCTRL_PIN(96, "GPIO96"), - NULL, "mt6589", + MTK_PIN( + 96, "GPIO96", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO96"), MTK_FUNCTION(1, "DUAL_BPI1_BUS13"), MTK_FUNCTION(3, "BPI2_BUS13"), MTK_FUNCTION(5, "USB_TEST_IO[13]"), MTK_FUNCTION(7, "A_FUNC_DOUT[5]") ), - MTK_PIN(PINCTRL_PIN(97, "GPIO97"), - NULL, "mt6589", + MTK_PIN( + 97, "GPIO97", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO97"), MTK_FUNCTION(1, "DUAL_BPI1_BUS14"), MTK_FUNCTION(3, "BPI2_BUS16"), MTK_FUNCTION(5, "USB_TEST_IO[14]"), MTK_FUNCTION(7, "A_FUNC_DOUT[4]") ), - MTK_PIN(PINCTRL_PIN(98, "GPIO98"), - NULL, "mt6589", + MTK_PIN( + 98, "GPIO98", MTK_EINT_FUNCTION(2, 16), + DRV_GRP1, MTK_FUNCTION(0, "GPIO98"), MTK_FUNCTION(1, "DUAL_BPI1_BUS17"), MTK_FUNCTION(2, "EINT16"), @@ -1005,9 +1103,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[15]"), MTK_FUNCTION(7, "A_FUNC_DOUT[3]") ), - MTK_PIN(PINCTRL_PIN(99, "GPIO99"), - NULL, "mt6589", + MTK_PIN( + 99, "GPIO99", MTK_EINT_FUNCTION(2, 17), + DRV_GRP1, MTK_FUNCTION(0, "GPIO99"), MTK_FUNCTION(1, "DUAL_BPI1_BUS15"), MTK_FUNCTION(2, "EINT17"), @@ -1015,74 +1114,83 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[16]"), MTK_FUNCTION(7, "A_FUNC_DOUT[2]") ), - MTK_PIN(PINCTRL_PIN(100, "GPIO100"), - NULL, "mt6589", + MTK_PIN( + 100, "GPIO100", MTK_EINT_FUNCTION(2, 19), + DRV_GRP1, MTK_FUNCTION(0, "GPIO100"), MTK_FUNCTION(1, "VM1"), MTK_FUNCTION(2, "EINT19"), MTK_FUNCTION(5, "USB_TEST_IO[17]"), MTK_FUNCTION(7, "A_FUNC_DOUT[0]") ), - MTK_PIN(PINCTRL_PIN(101, "GPIO101"), - NULL, "mt6589", + MTK_PIN( + 101, "GPIO101", MTK_EINT_FUNCTION(2, 18), + DRV_GRP1, MTK_FUNCTION(0, "GPIO101"), MTK_FUNCTION(1, "VM0"), MTK_FUNCTION(2, "EINT18"), MTK_FUNCTION(5, "USB_TEST_IO[18]"), MTK_FUNCTION(7, "A_FUNC_DOUT[1]") ), - MTK_PIN(PINCTRL_PIN(102, "GPIO102"), - NULL, "mt6589", + MTK_PIN( + 102, "GPIO102", MTK_EINT_FUNCTION(2, 26), + DRV_GRP1, MTK_FUNCTION(0, "GPIO102"), MTK_FUNCTION(1, "BSI1B_CS0"), MTK_FUNCTION(2, "EINT26"), MTK_FUNCTION(5, "USB_TEST_IO[19]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[21]") ), - MTK_PIN(PINCTRL_PIN(103, "GPIO103"), - NULL, "mt6589", + MTK_PIN( + 103, "GPIO103", MTK_EINT_FUNCTION(2, 27), + DRV_GRP1, MTK_FUNCTION(0, "GPIO103"), MTK_FUNCTION(1, "BSI1B_DATA0"), MTK_FUNCTION(2, "EINT27"), MTK_FUNCTION(5, "USB_TEST_IO[20]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[22]") ), - MTK_PIN(PINCTRL_PIN(104, "GPIO104"), - NULL, "mt6589", + MTK_PIN( + 104, "GPIO104", MTK_EINT_FUNCTION(2, 25), + DRV_GRP1, MTK_FUNCTION(0, "GPIO104"), MTK_FUNCTION(1, "BSI1B_CLK"), MTK_FUNCTION(2, "EINT25"), MTK_FUNCTION(5, "USB_TEST_IO[21]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[23]") ), - MTK_PIN(PINCTRL_PIN(105, "GPIO105"), - NULL, "mt6589", + MTK_PIN( + 105, "GPIO105", MTK_EINT_FUNCTION(2, 30), + DRV_GRP1, MTK_FUNCTION(0, "GPIO105"), MTK_FUNCTION(1, "TXBPI1"), MTK_FUNCTION(2, "EINT30") ), - MTK_PIN(PINCTRL_PIN(106, "GPIO106"), - NULL, "mt6589", + MTK_PIN( + 106, "GPIO106", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO106"), MTK_FUNCTION(1, "EXT_CLK_EN") ), - MTK_PIN(PINCTRL_PIN(107, "GPIO107"), - NULL, "mt6589", + MTK_PIN( + 107, "GPIO107", MTK_EINT_FUNCTION(2, 39), + DRV_GRP1, MTK_FUNCTION(0, "GPIO107"), MTK_FUNCTION(1, "SRCLKENA2"), MTK_FUNCTION(2, "EINT39") ), - MTK_PIN(PINCTRL_PIN(108, "GPIO108"), - NULL, "mt6589", + MTK_PIN( + 108, "GPIO108", MTK_EINT_FUNCTION(2, 21), + DRV_GRP1, MTK_FUNCTION(0, "GPIO108"), MTK_FUNCTION(1, "BSI1A_CS0"), MTK_FUNCTION(2, "EINT21"), @@ -1090,18 +1198,20 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[22]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[24]") ), - MTK_PIN(PINCTRL_PIN(109, "GPIO109"), - NULL, "mt6589", + MTK_PIN( + 109, "GPIO109", MTK_EINT_FUNCTION(2, 24), + DRV_GRP1, MTK_FUNCTION(0, "GPIO109"), MTK_FUNCTION(1, "BSI1A_DATA2"), MTK_FUNCTION(2, "EINT24"), MTK_FUNCTION(5, "USB_TEST_IO[23]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[25]") ), - MTK_PIN(PINCTRL_PIN(110, "GPIO110"), - NULL, "mt6589", + MTK_PIN( + 110, "GPIO110", MTK_EINT_FUNCTION(2, 23), + DRV_GRP1, MTK_FUNCTION(0, "GPIO110"), MTK_FUNCTION(1, "BSI1A_DATA1"), MTK_FUNCTION(2, "EINT23"), @@ -1109,9 +1219,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[24]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[26]") ), - MTK_PIN(PINCTRL_PIN(111, "GPIO111"), - NULL, "mt6589", + MTK_PIN( + 111, "GPIO111", MTK_EINT_FUNCTION(2, 22), + DRV_GRP1, MTK_FUNCTION(0, "GPIO111"), MTK_FUNCTION(1, "BSI1A_DATA0"), MTK_FUNCTION(2, "EINT22"), @@ -1119,9 +1230,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[25]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[27]") ), - MTK_PIN(PINCTRL_PIN(112, "GPIO112"), - NULL, "mt6589", + MTK_PIN( + 112, "GPIO112", MTK_EINT_FUNCTION(2, 20), + DRV_GRP1, MTK_FUNCTION(0, "GPIO112"), MTK_FUNCTION(1, "BSI1A_CLK"), MTK_FUNCTION(2, "EINT20"), @@ -1129,9 +1241,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_TEST_IO[26]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[28]") ), - MTK_PIN(PINCTRL_PIN(113, "GPIO113"), - NULL, "mt6589", + MTK_PIN( + 113, "GPIO113", MTK_EINT_FUNCTION(2, 29), + DRV_GRP1, MTK_FUNCTION(0, "GPIO113"), MTK_FUNCTION(1, "BSI1C_DATA"), MTK_FUNCTION(2, "EINT29"), @@ -1141,39 +1254,44 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[29]"), MTK_FUNCTION(7, "USB_DRVVBUS") ), - MTK_PIN(PINCTRL_PIN(114, "GPIO114"), - NULL, "mt6589", + MTK_PIN( + 114, "GPIO114", MTK_EINT_FUNCTION(2, 28), + DRV_GRP1, MTK_FUNCTION(0, "GPIO114"), MTK_FUNCTION(1, "BSI1C_CLK"), MTK_FUNCTION(2, "EINT28"), MTK_FUNCTION(5, "USB_TEST_IO[28]"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[30]") ), - MTK_PIN(PINCTRL_PIN(115, "GPIO115"), - NULL, "mt6589", + MTK_PIN( + 115, "GPIO115", MTK_EINT_FUNCTION(1, 10), + DRV_GRP1, MTK_FUNCTION(0, "GPIO115"), MTK_FUNCTION(1, "EINT10"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[31]") ), - MTK_PIN(PINCTRL_PIN(116, "GPIO116"), - NULL, "mt6589", + MTK_PIN( + 116, "GPIO116", MTK_EINT_FUNCTION(1, 11), + DRV_GRP1, MTK_FUNCTION(0, "GPIO116"), MTK_FUNCTION(1, "EINT11"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[32]") ), - MTK_PIN(PINCTRL_PIN(117, "GPIO117"), - NULL, "mt6589", + MTK_PIN( + 117, "GPIO117", MTK_EINT_FUNCTION(1, 16), + DRV_GRP1, MTK_FUNCTION(0, "GPIO117"), MTK_FUNCTION(1, "EINT16"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[33]") ), - MTK_PIN(PINCTRL_PIN(118, "GPIO118"), - NULL, "mt6589", + MTK_PIN( + 118, "GPIO118", MTK_EINT_FUNCTION(2, 91), + DRV_FIXED, MTK_FUNCTION(0, "GPIO118"), MTK_FUNCTION(1, "SDA0"), MTK_FUNCTION(2, "EINT91"), @@ -1181,9 +1299,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "PWM1"), MTK_FUNCTION(7, "A_FUNC_DIN[19]") ), - MTK_PIN(PINCTRL_PIN(119, "GPIO119"), - NULL, "mt6589", + MTK_PIN( + 119, "GPIO119", MTK_EINT_FUNCTION(2, 90), + DRV_FIXED, MTK_FUNCTION(0, "GPIO119"), MTK_FUNCTION(1, "SCL0"), MTK_FUNCTION(2, "EINT90"), @@ -1191,9 +1310,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "DISP_PWM"), MTK_FUNCTION(7, "A_FUNC_DIN[20]") ), - MTK_PIN(PINCTRL_PIN(120, "GPIO120"), - NULL, "mt6589", + MTK_PIN( + 120, "GPIO120", MTK_EINT_FUNCTION(2, 10), + DRV_GRP1, MTK_FUNCTION(0, "GPIO120"), MTK_FUNCTION(1, "I2SIN_CK"), MTK_FUNCTION(2, "EINT10"), @@ -1202,9 +1322,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "DSP1_ICK"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[34]") ), - MTK_PIN(PINCTRL_PIN(121, "GPIO121"), - NULL, "mt6589", + MTK_PIN( + 121, "GPIO121", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO121"), MTK_FUNCTION(1, "I2SIN_WS"), MTK_FUNCTION(3, "DAC_WS"), @@ -1212,9 +1333,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "DSP1_ID"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[35]") ), - MTK_PIN(PINCTRL_PIN(122, "GPIO122"), - NULL, "mt6589", + MTK_PIN( + 122, "GPIO122", MTK_EINT_FUNCTION(2, 11), + DRV_GRP1, MTK_FUNCTION(0, "GPIO122"), MTK_FUNCTION(1, "I2SIN_DAT"), MTK_FUNCTION(2, "EINT11"), @@ -1222,9 +1344,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "DSP1_IMS"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[36]") ), - MTK_PIN(PINCTRL_PIN(123, "GPIO123"), - NULL, "mt6589", + MTK_PIN( + 123, "GPIO123", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO123"), MTK_FUNCTION(1, "I2SOUT_DAT"), MTK_FUNCTION(3, "DAC_DAT_OUT"), @@ -1232,9 +1355,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_EINT5"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[37]") ), - MTK_PIN(PINCTRL_PIN(124, "GPIO124"), - NULL, "mt6589", + MTK_PIN( + 124, "GPIO124", MTK_EINT_FUNCTION(1, 5), + DRV_GRP3, MTK_FUNCTION(0, "GPIO124"), MTK_FUNCTION(1, "EINT5"), MTK_FUNCTION(2, "PWM5"), @@ -1243,9 +1367,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_EINT1"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[38]") ), - MTK_PIN(PINCTRL_PIN(125, "GPIO125"), - NULL, "mt6589", + MTK_PIN( + 125, "GPIO125", MTK_EINT_FUNCTION(1, 6), + DRV_GRP3, MTK_FUNCTION(0, "GPIO125"), MTK_FUNCTION(1, "EINT6"), MTK_FUNCTION(2, "PWM6"), @@ -1254,9 +1379,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_EINT2"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[39]") ), - MTK_PIN(PINCTRL_PIN(126, "GPIO126"), - NULL, "mt6589", + MTK_PIN( + 126, "GPIO126", MTK_EINT_FUNCTION(1, 7), + DRV_GRP3, MTK_FUNCTION(0, "GPIO126"), MTK_FUNCTION(1, "EINT7"), MTK_FUNCTION(2, "PWM7"), @@ -1265,9 +1391,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_EINT3"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[40]") ), - MTK_PIN(PINCTRL_PIN(127, "GPIO127"), - NULL, "mt6589", + MTK_PIN( + 127, "GPIO127", MTK_EINT_FUNCTION(1, 8), + DRV_GRP3, MTK_FUNCTION(0, "GPIO127"), MTK_FUNCTION(1, "EINT8"), MTK_FUNCTION(2, "DISP_PWM"), @@ -1276,9 +1403,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[41]"), MTK_FUNCTION(7, "EXT_FRAME_SYNC") ), - MTK_PIN(PINCTRL_PIN(128, "GPIO128"), - NULL, "mt6589", + MTK_PIN( + 128, "GPIO128", MTK_EINT_FUNCTION(1, 9), + DRV_GRP3, MTK_FUNCTION(0, "GPIO128"), MTK_FUNCTION(1, "EINT9"), MTK_FUNCTION(3, "MD1_GPS_SYNC"), @@ -1286,9 +1414,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "USB_DRVVBUS"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[42]") ), - MTK_PIN(PINCTRL_PIN(129, "GPIO129"), - NULL, "mt6589", + MTK_PIN( + 129, "GPIO129", MTK_EINT_FUNCTION(2, 77), + DRV_GRP1, MTK_FUNCTION(0, "GPIO129"), MTK_FUNCTION(1, "DISP_PWM"), MTK_FUNCTION(2, "EINT77"), @@ -1298,9 +1427,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[43]"), MTK_FUNCTION(7, "PWM3") ), - MTK_PIN(PINCTRL_PIN(130, "GPIO130"), - NULL, "mt6589", + MTK_PIN( + 130, "GPIO130", MTK_EINT_FUNCTION(2, 133), + DRV_GRP4, MTK_FUNCTION(0, "GPIO130"), MTK_FUNCTION(1, "MSDC4_DAT0"), MTK_FUNCTION(2, "EINT133"), @@ -1309,18 +1439,20 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[46]"), MTK_FUNCTION(7, "LPTE") ), - MTK_PIN(PINCTRL_PIN(131, "GPIO131"), - NULL, "mt6589", + MTK_PIN( + 131, "GPIO131", MTK_EINT_FUNCTION(2, 134), + DRV_GRP4, MTK_FUNCTION(0, "GPIO131"), MTK_FUNCTION(1, "MSDC4_DAT1"), MTK_FUNCTION(2, "EINT134"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[47]"), MTK_FUNCTION(7, "LRSTB_1X") ), - MTK_PIN(PINCTRL_PIN(132, "GPIO132"), - NULL, "mt6589", + MTK_PIN( + 132, "GPIO132", MTK_EINT_FUNCTION(2, 127), + DRV_GRP1, MTK_FUNCTION(0, "GPIO132"), MTK_FUNCTION(1, "LPCE1B"), MTK_FUNCTION(2, "EINT127"), @@ -1328,9 +1460,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PWM2"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[44]") ), - MTK_PIN(PINCTRL_PIN(133, "GPIO133"), - NULL, "mt6589", + MTK_PIN( + 133, "GPIO133", MTK_EINT_FUNCTION(2, 126), + DRV_GRP1, MTK_FUNCTION(0, "GPIO133"), MTK_FUNCTION(1, "LPCE0B"), MTK_FUNCTION(2, "EINT126"), @@ -1338,9 +1471,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PWM1"), MTK_FUNCTION(6, "MD_ABB_AFUNC_D[45]") ), - MTK_PIN(PINCTRL_PIN(134, "GPIO134"), - NULL, "mt6589", + MTK_PIN( + 134, "GPIO134", MTK_EINT_FUNCTION(2, 136), + DRV_GRP4, MTK_FUNCTION(0, "GPIO134"), MTK_FUNCTION(1, "MSDC4_DAT5"), MTK_FUNCTION(2, "EINT136"), @@ -1350,9 +1484,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[48]"), MTK_FUNCTION(7, "SPI1_CSN") ), - MTK_PIN(PINCTRL_PIN(135, "GPIO135"), - NULL, "mt6589", + MTK_PIN( + 135, "GPIO135", MTK_EINT_FUNCTION(2, 137), + DRV_GRP4, MTK_FUNCTION(0, "GPIO135"), MTK_FUNCTION(1, "MSDC4_DAT6"), MTK_FUNCTION(2, "EINT137"), @@ -1362,9 +1497,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[49]"), MTK_FUNCTION(7, "SPI1_MO") ), - MTK_PIN(PINCTRL_PIN(136, "GPIO136"), - NULL, "mt6589", + MTK_PIN( + 136, "GPIO136", MTK_EINT_FUNCTION(2, 138), + DRV_GRP4, MTK_FUNCTION(0, "GPIO136"), MTK_FUNCTION(1, "MSDC4_DAT7"), MTK_FUNCTION(2, "EINT138"), @@ -1373,9 +1509,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[50]"), MTK_FUNCTION(7, "SPI1_MI") ), - MTK_PIN(PINCTRL_PIN(137, "GPIO137"), - NULL, "mt6589", + MTK_PIN( + 137, "GPIO137", MTK_EINT_FUNCTION(2, 135), + DRV_GRP4, MTK_FUNCTION(0, "GPIO137"), MTK_FUNCTION(1, "MSDC4_DAT4"), MTK_FUNCTION(2, "EINT135"), @@ -1385,9 +1522,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[51]"), MTK_FUNCTION(7, "SPI1_CLK") ), - MTK_PIN(PINCTRL_PIN(138, "GPIO138"), - NULL, "mt6589", + MTK_PIN( + 138, "GPIO138", MTK_EINT_FUNCTION(2, 131), + DRV_GRP4, MTK_FUNCTION(0, "GPIO138"), MTK_FUNCTION(1, "MSDC4_DAT2"), MTK_FUNCTION(2, "EINT131"), @@ -1397,9 +1535,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PCM1_WS"), MTK_FUNCTION(7, "LSCE0B_1X") ), - MTK_PIN(PINCTRL_PIN(139, "GPIO139"), - NULL, "mt6589", + MTK_PIN( + 139, "GPIO139", MTK_EINT_FUNCTION(2, 129), + DRV_GRP4, MTK_FUNCTION(0, "GPIO139"), MTK_FUNCTION(1, "MSDC4_CLK"), MTK_FUNCTION(2, "EINT129"), @@ -1409,9 +1548,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PCM1_DI"), MTK_FUNCTION(7, "LSCK_1X") ), - MTK_PIN(PINCTRL_PIN(140, "GPIO140"), - NULL, "mt6589", + MTK_PIN( + 140, "GPIO140", MTK_EINT_FUNCTION(2, 132), + DRV_GRP4, MTK_FUNCTION(0, "GPIO140"), MTK_FUNCTION(1, "MSDC4_DAT3"), MTK_FUNCTION(2, "EINT132"), @@ -1421,9 +1561,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PCM1_DO"), MTK_FUNCTION(7, "LSCE1B_1X") ), - MTK_PIN(PINCTRL_PIN(141, "GPIO141"), - NULL, "mt6589", + MTK_PIN( + 141, "GPIO141", MTK_EINT_FUNCTION(2, 128), + DRV_GRP4, MTK_FUNCTION(0, "GPIO141"), MTK_FUNCTION(1, "MSDC4_CMD"), MTK_FUNCTION(2, "EINT128"), @@ -1433,9 +1574,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_GPS_SYNC"), MTK_FUNCTION(7, "LSDA_1X") ), - MTK_PIN(PINCTRL_PIN(142, "GPIO142"), - NULL, "mt6589", + MTK_PIN( + 142, "GPIO142", MTK_EINT_FUNCTION(2, 130), + DRV_GRP1, MTK_FUNCTION(0, "GPIO142"), MTK_FUNCTION(1, "MSDC4_RSTB"), MTK_FUNCTION(2, "EINT130"), @@ -1445,9 +1587,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PCM1_CK"), MTK_FUNCTION(7, "LSA0_1X") ), - MTK_PIN(PINCTRL_PIN(143, "GPIO143"), - NULL, "mt6589", + MTK_PIN( + 143, "GPIO143", MTK_EINT_FUNCTION(2, 98), + DRV_GRP1, MTK_FUNCTION(0, "GPIO143"), MTK_FUNCTION(1, "DPI0_VSYNC"), MTK_FUNCTION(2, "EINT98"), @@ -1457,9 +1600,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[52]"), MTK_FUNCTION(7, "TESTB_OUT8") ), - MTK_PIN(PINCTRL_PIN(144, "GPIO144"), - NULL, "mt6589", + MTK_PIN( + 144, "GPIO144", MTK_EINT_FUNCTION(2, 99), + DRV_GRP1, MTK_FUNCTION(0, "GPIO144"), MTK_FUNCTION(1, "DPI0_HSYNC"), MTK_FUNCTION(2, "EINT99"), @@ -1469,9 +1613,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "IRDA_RXD"), MTK_FUNCTION(7, "TESTB_OUT9") ), - MTK_PIN(PINCTRL_PIN(145, "GPIO145"), - NULL, "mt6589", + MTK_PIN( + 145, "GPIO145", MTK_EINT_FUNCTION(2, 100), + DRV_GRP1, MTK_FUNCTION(0, "GPIO145"), MTK_FUNCTION(1, "DPI0_DE"), MTK_FUNCTION(2, "EINT100"), @@ -1481,9 +1626,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "IRDA_TXD"), MTK_FUNCTION(7, "TESTB_OUT10") ), - MTK_PIN(PINCTRL_PIN(146, "GPIO146"), - NULL, "mt6589", + MTK_PIN( + 146, "GPIO146", MTK_EINT_FUNCTION(2, 101), + DRV_GRP1, MTK_FUNCTION(0, "GPIO146"), MTK_FUNCTION(1, "DPI0_CK"), MTK_FUNCTION(2, "EINT101"), @@ -1492,9 +1638,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "IRDA_PDN"), MTK_FUNCTION(7, "TESTB_OUT11") ), - MTK_PIN(PINCTRL_PIN(147, "GPIO147"), - NULL, "mt6589", + MTK_PIN( + 147, "GPIO147", MTK_EINT_FUNCTION(2, 102), + DRV_GRP1, MTK_FUNCTION(0, "GPIO147"), MTK_FUNCTION(1, "DPI0_B0"), MTK_FUNCTION(2, "EINT102"), @@ -1503,9 +1650,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[57]"), MTK_FUNCTION(7, "TESTB_OUT12") ), - MTK_PIN(PINCTRL_PIN(148, "GPIO148"), - NULL, "mt6589", + MTK_PIN( + 148, "GPIO148", MTK_EINT_FUNCTION(2, 103), + DRV_GRP1, MTK_FUNCTION(0, "GPIO148"), MTK_FUNCTION(1, "DPI0_B1"), MTK_FUNCTION(2, "EINT103"), @@ -1515,9 +1663,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[58]"), MTK_FUNCTION(7, "TESTB_OUT13") ), - MTK_PIN(PINCTRL_PIN(149, "GPIO149"), - NULL, "mt6589", + MTK_PIN( + 149, "GPIO149", MTK_EINT_FUNCTION(2, 104), + DRV_GRP1, MTK_FUNCTION(0, "GPIO149"), MTK_FUNCTION(1, "DPI0_B2"), MTK_FUNCTION(2, "EINT104"), @@ -1527,9 +1676,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[59]"), MTK_FUNCTION(7, "TESTB_OUT14") ), - MTK_PIN(PINCTRL_PIN(150, "GPIO150"), - NULL, "mt6589", + MTK_PIN( + 150, "GPIO150", MTK_EINT_FUNCTION(2, 105), + DRV_GRP1, MTK_FUNCTION(0, "GPIO150"), MTK_FUNCTION(1, "DPI0_B3"), MTK_FUNCTION(2, "EINT105"), @@ -1539,9 +1689,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[60]"), MTK_FUNCTION(7, "TESTB_OUT15") ), - MTK_PIN(PINCTRL_PIN(151, "GPIO151"), - NULL, "mt6589", + MTK_PIN( + 151, "GPIO151", MTK_EINT_FUNCTION(2, 106), + DRV_GRP1, MTK_FUNCTION(0, "GPIO151"), MTK_FUNCTION(1, "DPI0_B4"), MTK_FUNCTION(2, "EINT106"), @@ -1551,9 +1702,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[61]"), MTK_FUNCTION(7, "TESTB_OUT16") ), - MTK_PIN(PINCTRL_PIN(152, "GPIO152"), - NULL, "mt6589", + MTK_PIN( + 152, "GPIO152", MTK_EINT_FUNCTION(2, 107), + DRV_GRP1, MTK_FUNCTION(0, "GPIO152"), MTK_FUNCTION(1, "DPI0_B5"), MTK_FUNCTION(2, "EINT107"), @@ -1563,9 +1715,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[62]"), MTK_FUNCTION(7, "TESTB_OUT17") ), - MTK_PIN(PINCTRL_PIN(153, "GPIO153"), - NULL, "mt6589", + MTK_PIN( + 153, "GPIO153", MTK_EINT_FUNCTION(2, 108), + DRV_GRP1, MTK_FUNCTION(0, "GPIO153"), MTK_FUNCTION(1, "DPI0_B6"), MTK_FUNCTION(2, "EINT108"), @@ -1575,9 +1728,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[63]"), MTK_FUNCTION(7, "TESTB_OUT18") ), - MTK_PIN(PINCTRL_PIN(154, "GPIO154"), - NULL, "mt6589", + MTK_PIN( + 154, "GPIO154", MTK_EINT_FUNCTION(2, 109), + DRV_GRP1, MTK_FUNCTION(0, "GPIO154"), MTK_FUNCTION(1, "DPI0_B7"), MTK_FUNCTION(2, "EINT109"), @@ -1587,9 +1741,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[0]"), MTK_FUNCTION(7, "TESTB_OUT19") ), - MTK_PIN(PINCTRL_PIN(155, "GPIO155"), - NULL, "mt6589", + MTK_PIN( + 155, "GPIO155", MTK_EINT_FUNCTION(2, 110), + DRV_GRP1, MTK_FUNCTION(0, "GPIO155"), MTK_FUNCTION(1, "DPI0_G0"), MTK_FUNCTION(2, "EINT110"), @@ -1597,9 +1752,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[1]"), MTK_FUNCTION(7, "TESTB_OUT20") ), - MTK_PIN(PINCTRL_PIN(156, "GPIO156"), - NULL, "mt6589", + MTK_PIN( + 156, "GPIO156", MTK_EINT_FUNCTION(2, 111), + DRV_GRP1, MTK_FUNCTION(0, "GPIO156"), MTK_FUNCTION(1, "DPI0_G1"), MTK_FUNCTION(2, "EINT111"), @@ -1607,9 +1763,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[56]"), MTK_FUNCTION(7, "TESTB_OUT21") ), - MTK_PIN(PINCTRL_PIN(157, "GPIO157"), - NULL, "mt6589", + MTK_PIN( + 157, "GPIO157", MTK_EINT_FUNCTION(2, 112), + DRV_GRP1, MTK_FUNCTION(0, "GPIO157"), MTK_FUNCTION(1, "DPI0_G2"), MTK_FUNCTION(2, "EINT112"), @@ -1617,9 +1774,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[2]"), MTK_FUNCTION(7, "TESTB_OUT22") ), - MTK_PIN(PINCTRL_PIN(158, "GPIO158"), - NULL, "mt6589", + MTK_PIN( + 158, "GPIO158", MTK_EINT_FUNCTION(2, 113), + DRV_GRP1, MTK_FUNCTION(0, "GPIO158"), MTK_FUNCTION(1, "DPI0_G3"), MTK_FUNCTION(2, "EINT113"), @@ -1627,9 +1785,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[3]"), MTK_FUNCTION(7, "TESTB_OUT23") ), - MTK_PIN(PINCTRL_PIN(159, "GPIO159"), - NULL, "mt6589", + MTK_PIN( + 159, "GPIO159", MTK_EINT_FUNCTION(2, 114), + DRV_GRP1, MTK_FUNCTION(0, "GPIO159"), MTK_FUNCTION(1, "DPI0_G4"), MTK_FUNCTION(2, "EINT114"), @@ -1639,9 +1798,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[53]"), MTK_FUNCTION(7, "TESTB_OUT24") ), - MTK_PIN(PINCTRL_PIN(160, "GPIO160"), - NULL, "mt6589", + MTK_PIN( + 160, "GPIO160", MTK_EINT_FUNCTION(2, 115), + DRV_GRP1, MTK_FUNCTION(0, "GPIO160"), MTK_FUNCTION(1, "DPI0_G5"), MTK_FUNCTION(2, "EINT115"), @@ -1651,9 +1811,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[54]"), MTK_FUNCTION(7, "TESTB_OUT25") ), - MTK_PIN(PINCTRL_PIN(161, "GPIO161"), - NULL, "mt6589", + MTK_PIN( + 161, "GPIO161", MTK_EINT_FUNCTION(2, 116), + DRV_GRP1, MTK_FUNCTION(0, "GPIO161"), MTK_FUNCTION(1, "DPI0_G6"), MTK_FUNCTION(2, "EINT116"), @@ -1663,9 +1824,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[4]"), MTK_FUNCTION(7, "TESTB_OUT26") ), - MTK_PIN(PINCTRL_PIN(162, "GPIO162"), - NULL, "mt6589", + MTK_PIN( + 162, "GPIO162", MTK_EINT_FUNCTION(2, 117), + DRV_GRP1, MTK_FUNCTION(0, "GPIO162"), MTK_FUNCTION(1, "DPI0_G7"), MTK_FUNCTION(2, "EINT117"), @@ -1675,9 +1837,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[5]"), MTK_FUNCTION(7, "TESTB_OUT27") ), - MTK_PIN(PINCTRL_PIN(163, "GPIO163"), - NULL, "mt6589", + MTK_PIN( + 163, "GPIO163", MTK_EINT_FUNCTION(2, 118), + DRV_GRP1, MTK_FUNCTION(0, "GPIO163"), MTK_FUNCTION(1, "DPI0_R0"), MTK_FUNCTION(2, "EINT118"), @@ -1687,9 +1850,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[6]"), MTK_FUNCTION(7, "TESTB_OUT28") ), - MTK_PIN(PINCTRL_PIN(164, "GPIO164"), - NULL, "mt6589", + MTK_PIN( + 164, "GPIO164", MTK_EINT_FUNCTION(2, 119), + DRV_GRP1, MTK_FUNCTION(0, "GPIO164"), MTK_FUNCTION(1, "DPI0_R1"), MTK_FUNCTION(2, "EINT119"), @@ -1699,9 +1863,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD1_PLL_A_FUNC_DOUT[7]"), MTK_FUNCTION(7, "TESTB_OUT29") ), - MTK_PIN(PINCTRL_PIN(165, "GPIO165"), - NULL, "mt6589", + MTK_PIN( + 165, "GPIO165", MTK_EINT_FUNCTION(2, 120), + DRV_GRP1, MTK_FUNCTION(0, "GPIO165"), MTK_FUNCTION(1, "DPI0_R2"), MTK_FUNCTION(2, "EINT120"), @@ -1710,9 +1875,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "MD2_TMS_PAD"), MTK_FUNCTION(7, "TESTB_OUT30") ), - MTK_PIN(PINCTRL_PIN(166, "GPIO166"), - NULL, "mt6589", + MTK_PIN( + 166, "GPIO166", MTK_EINT_FUNCTION(2, 121), + DRV_GRP1, MTK_FUNCTION(0, "GPIO166"), MTK_FUNCTION(1, "DPI0_R3"), MTK_FUNCTION(2, "EINT121"), @@ -1722,9 +1888,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD_ABB_AFUNC_D[55]"), MTK_FUNCTION(7, "TESTB_OUT31") ), - MTK_PIN(PINCTRL_PIN(167, "GPIO167"), - NULL, "mt6589", + MTK_PIN( + 167, "GPIO167", MTK_EINT_FUNCTION(2, 122), + DRV_GRP1, MTK_FUNCTION(0, "GPIO167"), MTK_FUNCTION(1, "DPI0_R4"), MTK_FUNCTION(2, "EINT122"), @@ -1732,9 +1899,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "CM2DAT_2X[8]"), MTK_FUNCTION(7, "TESTA_OUT0") ), - MTK_PIN(PINCTRL_PIN(168, "GPIO168"), - NULL, "mt6589", + MTK_PIN( + 168, "GPIO168", MTK_EINT_FUNCTION(2, 123), + DRV_GRP1, MTK_FUNCTION(0, "GPIO168"), MTK_FUNCTION(1, "DPI0_R5"), MTK_FUNCTION(2, "EINT123"), @@ -1744,9 +1912,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_DAI_RX_GPIO"), MTK_FUNCTION(7, "TESTA_OUT1") ), - MTK_PIN(PINCTRL_PIN(169, "GPIO169"), - NULL, "mt6589", + MTK_PIN( + 169, "GPIO169", MTK_EINT_FUNCTION(2, 124), + DRV_GRP1, MTK_FUNCTION(0, "GPIO169"), MTK_FUNCTION(1, "DPI0_R6"), MTK_FUNCTION(2, "EINT124"), @@ -1754,9 +1923,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "CM2VSYNC_2X"), MTK_FUNCTION(7, "TESTA_OUT2") ), - MTK_PIN(PINCTRL_PIN(170, "GPIO170"), - NULL, "mt6589", + MTK_PIN( + 170, "GPIO170", MTK_EINT_FUNCTION(2, 125), + DRV_GRP1, MTK_FUNCTION(0, "GPIO170"), MTK_FUNCTION(1, "DPI0_R7"), MTK_FUNCTION(2, "EINT125"), @@ -1764,9 +1934,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "CM2HSYNC_2X"), MTK_FUNCTION(7, "TESTA_OUT3") ), - MTK_PIN(PINCTRL_PIN(171, "GPIO171"), - NULL, "mt6589", + MTK_PIN( + 171, "GPIO171", MTK_EINT_FUNCTION(2, 57), + DRV_GRP1, MTK_FUNCTION(0, "GPIO171"), MTK_FUNCTION(1, "MSDC1_INSI"), MTK_FUNCTION(2, "EINT57"), @@ -1776,18 +1947,20 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[0]"), MTK_FUNCTION(7, "TESTB_OUT6") ), - MTK_PIN(PINCTRL_PIN(172, "GPIO172"), - NULL, "mt6589", + MTK_PIN( + 172, "GPIO172", MTK_EINT_FUNCTION(2, 65), + DRV_GRP1, MTK_FUNCTION(0, "GPIO172"), MTK_FUNCTION(1, "MSDC2_INSI"), MTK_FUNCTION(2, "EINT65"), MTK_FUNCTION(3, "BPI2_BUS6"), MTK_FUNCTION(7, "A_FUNC_DIN[6]") ), - MTK_PIN(PINCTRL_PIN(173, "GPIO173"), - NULL, "mt6589", + MTK_PIN( + 173, "GPIO173", MTK_EINT_FUNCTION(2, 66), + DRV_GRP1, MTK_FUNCTION(0, "GPIO173"), MTK_FUNCTION(1, "MSDC2_SDWPI"), MTK_FUNCTION(2, "EINT66"), @@ -1796,9 +1969,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "DUAL_BPI1_BUS15"), MTK_FUNCTION(7, "A_FUNC_DIN[5]") ), - MTK_PIN(PINCTRL_PIN(174, "GPIO174"), - NULL, "mt6589", + MTK_PIN( + 174, "GPIO174", MTK_EINT_FUNCTION(2, 63), + DRV_GRP5, MTK_FUNCTION(0, "GPIO174"), MTK_FUNCTION(1, "MSDC2_DAT2"), MTK_FUNCTION(2, "EINT63"), @@ -1806,9 +1980,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "DSP2_IMS"), MTK_FUNCTION(7, "A_FUNC_DIN[8]") ), - MTK_PIN(PINCTRL_PIN(175, "GPIO175"), - NULL, "mt6589", + MTK_PIN( + 175, "GPIO175", MTK_EINT_FUNCTION(2, 64), + DRV_GRP5, MTK_FUNCTION(0, "GPIO175"), MTK_FUNCTION(1, "MSDC2_DAT3"), MTK_FUNCTION(2, "EINT64"), @@ -1816,9 +1991,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "DSP2_ID"), MTK_FUNCTION(7, "A_FUNC_DIN[7]") ), - MTK_PIN(PINCTRL_PIN(176, "GPIO176"), - NULL, "mt6589", + MTK_PIN( + 176, "GPIO176", MTK_EINT_FUNCTION(2, 60), + DRV_GRP5, MTK_FUNCTION(0, "GPIO176"), MTK_FUNCTION(1, "MSDC2_CMD"), MTK_FUNCTION(2, "EINT60"), @@ -1827,9 +2003,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PCM1_WS"), MTK_FUNCTION(7, "A_FUNC_DIN[11]") ), - MTK_PIN(PINCTRL_PIN(177, "GPIO177"), - NULL, "mt6589", + MTK_PIN( + 177, "GPIO177", MTK_EINT_FUNCTION(2, 59), + DRV_GRP5, MTK_FUNCTION(0, "GPIO177"), MTK_FUNCTION(1, "MSDC2_CLK"), MTK_FUNCTION(2, "EINT59"), @@ -1838,9 +2015,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PCM1_CK"), MTK_FUNCTION(7, "A_FUNC_DIN[12]") ), - MTK_PIN(PINCTRL_PIN(178, "GPIO178"), - NULL, "mt6589", + MTK_PIN( + 178, "GPIO178", MTK_EINT_FUNCTION(2, 62), + DRV_GRP5, MTK_FUNCTION(0, "GPIO178"), MTK_FUNCTION(1, "MSDC2_DAT1"), MTK_FUNCTION(2, "EINT62"), @@ -1849,9 +2027,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PCM1_DO"), MTK_FUNCTION(7, "A_FUNC_DIN[9]") ), - MTK_PIN(PINCTRL_PIN(179, "GPIO179"), - NULL, "mt6589", + MTK_PIN( + 179, "GPIO179", MTK_EINT_FUNCTION(2, 61), + DRV_GRP5, MTK_FUNCTION(0, "GPIO179"), MTK_FUNCTION(1, "MSDC2_DAT0"), MTK_FUNCTION(2, "EINT61"), @@ -1860,9 +2039,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "PCM1_DI"), MTK_FUNCTION(7, "A_FUNC_DIN[10]") ), - MTK_PIN(PINCTRL_PIN(180, "GPIO180"), - NULL, "mt6589", + MTK_PIN( + 180, "GPIO180", MTK_EINT_FUNCTION(2, 53), + DRV_GRP5, MTK_FUNCTION(0, "GPIO180"), MTK_FUNCTION(1, "MSDC1_DAT0"), MTK_FUNCTION(2, "EINT53"), @@ -1872,9 +2052,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[1]"), MTK_FUNCTION(7, "TESTB_OUT2") ), - MTK_PIN(PINCTRL_PIN(181, "GPIO181"), - NULL, "mt6589", + MTK_PIN( + 181, "GPIO181", MTK_EINT_FUNCTION(2, 54), + DRV_GRP5, MTK_FUNCTION(0, "GPIO181"), MTK_FUNCTION(1, "MSDC1_DAT1"), MTK_FUNCTION(2, "EINT54"), @@ -1884,9 +2065,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[2]"), MTK_FUNCTION(7, "TESTB_OUT3") ), - MTK_PIN(PINCTRL_PIN(182, "GPIO182"), - NULL, "mt6589", + MTK_PIN( + 182, "GPIO182", MTK_EINT_FUNCTION(2, 58), + DRV_GRP1, MTK_FUNCTION(0, "GPIO182"), MTK_FUNCTION(1, "MSDC1_SDWPI"), MTK_FUNCTION(2, "EINT58"), @@ -1896,9 +2078,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[3]"), MTK_FUNCTION(7, "TESTB_OUT7") ), - MTK_PIN(PINCTRL_PIN(183, "GPIO183"), - NULL, "mt6589", + MTK_PIN( + 183, "GPIO183", MTK_EINT_FUNCTION(2, 52), + DRV_GRP5, MTK_FUNCTION(0, "GPIO183"), MTK_FUNCTION(1, "MSDC1_CMD"), MTK_FUNCTION(2, "EINT52"), @@ -1908,9 +2091,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[4]"), MTK_FUNCTION(7, "TESTB_OUT1") ), - MTK_PIN(PINCTRL_PIN(184, "GPIO184"), - NULL, "mt6589", + MTK_PIN( + 184, "GPIO184", MTK_EINT_FUNCTION(2, 51), + DRV_GRP5, MTK_FUNCTION(0, "GPIO184"), MTK_FUNCTION(1, "MSDC1_CLK"), MTK_FUNCTION(2, "EINT51"), @@ -1919,9 +2103,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[5]"), MTK_FUNCTION(7, "TESTB_OUT0") ), - MTK_PIN(PINCTRL_PIN(185, "GPIO185"), - NULL, "mt6589", + MTK_PIN( + 185, "GPIO185", MTK_EINT_FUNCTION(2, 55), + DRV_GRP5, MTK_FUNCTION(0, "GPIO185"), MTK_FUNCTION(1, "MSDC1_DAT2"), MTK_FUNCTION(2, "EINT55"), @@ -1931,9 +2116,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[6]"), MTK_FUNCTION(7, "TESTB_OUT4") ), - MTK_PIN(PINCTRL_PIN(186, "GPIO186"), - NULL, "mt6589", + MTK_PIN( + 186, "GPIO186", MTK_EINT_FUNCTION(2, 56), + DRV_GRP5, MTK_FUNCTION(0, "GPIO186"), MTK_FUNCTION(1, "MSDC1_DAT3"), MTK_FUNCTION(2, "EINT56"), @@ -1943,157 +2129,180 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MD2_PLL_A_FUNC_DOUT[7]"), MTK_FUNCTION(7, "TESTB_OUT5") ), - MTK_PIN(PINCTRL_PIN(187, "GPIO187"), - NULL, "mt6589", + MTK_PIN( + 187, "GPIO187", MTK_EINT_FUNCTION(2, 36), + DRV_FIXED, MTK_FUNCTION(0, "GPIO187"), MTK_FUNCTION(2, "EINT36") ), - MTK_PIN(PINCTRL_PIN(188, "GPIO188"), - NULL, "mt6589", + MTK_PIN( + 188, "GPIO188", MTK_EINT_FUNCTION(2, 35), + DRV_FIXED, MTK_FUNCTION(0, "GPIO188"), MTK_FUNCTION(2, "EINT35") ), - MTK_PIN(PINCTRL_PIN(189, "GPIO189"), - NULL, "mt6589", + MTK_PIN( + 189, "GPIO189", MTK_EINT_FUNCTION(2, 169), + DRV_FIXED, MTK_FUNCTION(0, "GPIO189"), MTK_FUNCTION(2, "EINT169") ), - MTK_PIN(PINCTRL_PIN(190, "GPIO190"), - NULL, "mt6589", + MTK_PIN( + 190, "GPIO190", MTK_EINT_FUNCTION(2, 168), + DRV_FIXED, MTK_FUNCTION(0, "GPIO190"), MTK_FUNCTION(2, "EINT168") ), - MTK_PIN(PINCTRL_PIN(191, "GPIO191"), - NULL, "mt6589", + MTK_PIN( + 191, "GPIO191", MTK_EINT_FUNCTION(2, 163), + DRV_FIXED, MTK_FUNCTION(0, "GPIO191"), MTK_FUNCTION(2, "EINT163") ), - MTK_PIN(PINCTRL_PIN(192, "GPIO192"), - NULL, "mt6589", + MTK_PIN( + 192, "GPIO192", MTK_EINT_FUNCTION(2, 162), + DRV_FIXED, MTK_FUNCTION(0, "GPIO192"), MTK_FUNCTION(2, "EINT162") ), - MTK_PIN(PINCTRL_PIN(193, "GPIO193"), - NULL, "mt6589", + MTK_PIN( + 193, "GPIO193", MTK_EINT_FUNCTION(2, 167), + DRV_FIXED, MTK_FUNCTION(0, "GPIO193"), MTK_FUNCTION(2, "EINT167") ), - MTK_PIN(PINCTRL_PIN(194, "GPIO194"), - NULL, "mt6589", + MTK_PIN( + 194, "GPIO194", MTK_EINT_FUNCTION(2, 166), + DRV_FIXED, MTK_FUNCTION(0, "GPIO194"), MTK_FUNCTION(2, "EINT166") ), - MTK_PIN(PINCTRL_PIN(195, "GPIO195"), - NULL, "mt6589", + MTK_PIN( + 195, "GPIO195", MTK_EINT_FUNCTION(2, 165), + DRV_FIXED, MTK_FUNCTION(0, "GPIO195"), MTK_FUNCTION(2, "EINT165") ), - MTK_PIN(PINCTRL_PIN(196, "GPIO196"), - NULL, "mt6589", + MTK_PIN( + 196, "GPIO196", MTK_EINT_FUNCTION(2, 164), + DRV_FIXED, MTK_FUNCTION(0, "GPIO196"), MTK_FUNCTION(2, "EINT164") ), - MTK_PIN(PINCTRL_PIN(197, "GPIO197"), - NULL, "mt6589", + MTK_PIN( + 197, "GPIO197", MTK_EINT_FUNCTION(2, 175), + DRV_FIXED, MTK_FUNCTION(0, "GPIO197"), MTK_FUNCTION(1, "CMDAT6"), MTK_FUNCTION(2, "EINT175") ), - MTK_PIN(PINCTRL_PIN(198, "GPIO198"), - NULL, "mt6589", + MTK_PIN( + 198, "GPIO198", MTK_EINT_FUNCTION(2, 174), + DRV_FIXED, MTK_FUNCTION(0, "GPIO198"), MTK_FUNCTION(1, "CMDAT7"), MTK_FUNCTION(2, "EINT174") ), - MTK_PIN(PINCTRL_PIN(199, "GPIO199"), - NULL, "mt6589", + MTK_PIN( + 199, "GPIO199", MTK_EINT_FUNCTION(2, 171), + DRV_FIXED, MTK_FUNCTION(0, "GPIO199"), MTK_FUNCTION(1, "CMDAT8"), MTK_FUNCTION(2, "EINT171") ), - MTK_PIN(PINCTRL_PIN(200, "GPIO200"), - NULL, "mt6589", + MTK_PIN( + 200, "GPIO200", MTK_EINT_FUNCTION(2, 170), + DRV_FIXED, MTK_FUNCTION(0, "GPIO200"), MTK_FUNCTION(1, "CMDAT9"), MTK_FUNCTION(2, "EINT170") ), - MTK_PIN(PINCTRL_PIN(201, "GPIO201"), - NULL, "mt6589", + MTK_PIN( + 201, "GPIO201", MTK_EINT_FUNCTION(2, 173), + DRV_FIXED, MTK_FUNCTION(0, "GPIO201"), MTK_FUNCTION(1, "CMHSYNC"), MTK_FUNCTION(2, "EINT173") ), - MTK_PIN(PINCTRL_PIN(202, "GPIO202"), - NULL, "mt6589", + MTK_PIN( + 202, "GPIO202", MTK_EINT_FUNCTION(2, 172), + DRV_FIXED, MTK_FUNCTION(0, "GPIO202"), MTK_FUNCTION(1, "CMVSYNC"), MTK_FUNCTION(2, "EINT172") ), - MTK_PIN(PINCTRL_PIN(203, "GPIO203"), - NULL, "mt6589", + MTK_PIN( + 203, "GPIO203", MTK_EINT_FUNCTION(2, 181), + DRV_FIXED, MTK_FUNCTION(0, "GPIO203"), MTK_FUNCTION(1, "CMDAT2"), MTK_FUNCTION(2, "EINT181"), MTK_FUNCTION(3, "CMCSD2") ), - MTK_PIN(PINCTRL_PIN(204, "GPIO204"), - NULL, "mt6589", + MTK_PIN( + 204, "GPIO204", MTK_EINT_FUNCTION(2, 180), + DRV_FIXED, MTK_FUNCTION(0, "GPIO204"), MTK_FUNCTION(1, "CMDAT3"), MTK_FUNCTION(2, "EINT180"), MTK_FUNCTION(3, "CMCSD3") ), - MTK_PIN(PINCTRL_PIN(205, "GPIO205"), - NULL, "mt6589", + MTK_PIN( + 205, "GPIO205", MTK_EINT_FUNCTION(2, 177), + DRV_FIXED, MTK_FUNCTION(0, "GPIO205"), MTK_FUNCTION(1, "CMDAT4"), MTK_FUNCTION(2, "EINT177") ), - MTK_PIN(PINCTRL_PIN(206, "GPIO206"), - NULL, "mt6589", + MTK_PIN( + 206, "GPIO206", MTK_EINT_FUNCTION(2, 176), + DRV_FIXED, MTK_FUNCTION(0, "GPIO206"), MTK_FUNCTION(1, "CMDAT5"), MTK_FUNCTION(2, "EINT176") ), - MTK_PIN(PINCTRL_PIN(207, "GPIO207"), - NULL, "mt6589", + MTK_PIN( + 207, "GPIO207", MTK_EINT_FUNCTION(2, 179), + DRV_FIXED, MTK_FUNCTION(0, "GPIO207"), MTK_FUNCTION(1, "CMDAT0"), MTK_FUNCTION(2, "EINT179"), MTK_FUNCTION(3, "CMCSD0") ), - MTK_PIN(PINCTRL_PIN(208, "GPIO208"), - NULL, "mt6589", + MTK_PIN( + 208, "GPIO208", MTK_EINT_FUNCTION(2, 178), + DRV_FIXED, MTK_FUNCTION(0, "GPIO208"), MTK_FUNCTION(1, "CMDAT1"), MTK_FUNCTION(2, "EINT178"), MTK_FUNCTION(3, "CMCSD1") ), - MTK_PIN(PINCTRL_PIN(209, "GPIO209"), - NULL, "mt6589", + MTK_PIN( + 209, "GPIO209", MTK_EINT_FUNCTION(2, 182), + DRV_GRP1, MTK_FUNCTION(0, "GPIO209"), MTK_FUNCTION(1, "CMPCLK"), MTK_FUNCTION(2, "EINT182"), @@ -2102,45 +2311,50 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"), MTK_FUNCTION(7, "TESTA_OUT27") ), - MTK_PIN(PINCTRL_PIN(210, "GPIO210"), - NULL, "mt6589", + MTK_PIN( + 210, "GPIO210", MTK_EINT_FUNCTION(2, 183), + DRV_GRP1, MTK_FUNCTION(0, "GPIO210"), MTK_FUNCTION(1, "CMMCLK"), MTK_FUNCTION(2, "EINT183"), MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"), MTK_FUNCTION(7, "TESTA_OUT28") ), - MTK_PIN(PINCTRL_PIN(211, "GPIO211"), - NULL, "mt6589", + MTK_PIN( + 211, "GPIO211", MTK_EINT_FUNCTION(2, 185), + DRV_GRP1, MTK_FUNCTION(0, "GPIO211"), MTK_FUNCTION(1, "CMRST"), MTK_FUNCTION(2, "EINT185"), MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"), MTK_FUNCTION(7, "TESTA_OUT30") ), - MTK_PIN(PINCTRL_PIN(212, "GPIO212"), - NULL, "mt6589", + MTK_PIN( + 212, "GPIO212", MTK_EINT_FUNCTION(2, 184), + DRV_GRP1, MTK_FUNCTION(0, "GPIO212"), MTK_FUNCTION(1, "CMPDN"), MTK_FUNCTION(2, "EINT184"), MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"), MTK_FUNCTION(7, "TESTA_OUT29") ), - MTK_PIN(PINCTRL_PIN(213, "GPIO213"), - NULL, "mt6589", + MTK_PIN( + 213, "GPIO213", MTK_EINT_FUNCTION(2, 186), + DRV_GRP1, MTK_FUNCTION(0, "GPIO213"), MTK_FUNCTION(1, "CMFLASH"), MTK_FUNCTION(2, "EINT186"), MTK_FUNCTION(3, "CM2MCLK_3X"), MTK_FUNCTION(7, "TESTA_OUT31") ), - MTK_PIN(PINCTRL_PIN(214, "GPIO214"), - NULL, "mt6589", + MTK_PIN( + 214, "GPIO214", MTK_EINT_FUNCTION(2, 93), + DRV_FIXED, MTK_FUNCTION(0, "GPIO214"), MTK_FUNCTION(1, "SDA1"), MTK_FUNCTION(2, "EINT93"), @@ -2149,9 +2363,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB"), MTK_FUNCTION(7, "A_FUNC_DIN[17]") ), - MTK_PIN(PINCTRL_PIN(215, "GPIO215"), - NULL, "mt6589", + MTK_PIN( + 215, "GPIO215", MTK_EINT_FUNCTION(2, 92), + DRV_FIXED, MTK_FUNCTION(0, "GPIO215"), MTK_FUNCTION(1, "SCL1"), MTK_FUNCTION(2, "EINT92"), @@ -2160,9 +2375,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "TS_AUX_DIN"), MTK_FUNCTION(7, "A_FUNC_DIN[18]") ), - MTK_PIN(PINCTRL_PIN(216, "GPIO216"), - NULL, "mt6589", + MTK_PIN( + 216, "GPIO216", MTK_EINT_FUNCTION(2, 95), + DRV_FIXED, MTK_FUNCTION(0, "GPIO216"), MTK_FUNCTION(1, "SDA2"), MTK_FUNCTION(2, "EINT95"), @@ -2171,9 +2387,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "TS_AUX_PWDB"), MTK_FUNCTION(7, "A_FUNC_DIN[15]") ), - MTK_PIN(PINCTRL_PIN(217, "GPIO217"), - NULL, "mt6589", + MTK_PIN( + 217, "GPIO217", MTK_EINT_FUNCTION(2, 94), + DRV_FIXED, MTK_FUNCTION(0, "GPIO217"), MTK_FUNCTION(1, "SCL2"), MTK_FUNCTION(2, "EINT94"), @@ -2182,15 +2399,17 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "TS_AUXADC_TEST_CK"), MTK_FUNCTION(7, "A_FUNC_DIN[16]") ), - MTK_PIN(PINCTRL_PIN(218, "GPIO218"), - NULL, "mt6589", + MTK_PIN( + 218, "GPIO218", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP1, MTK_FUNCTION(0, "GPIO218"), MTK_FUNCTION(1, "SRCLKENAI") ), - MTK_PIN(PINCTRL_PIN(219, "GPIO219"), - NULL, "mt6589", + MTK_PIN( + 219, "GPIO219", MTK_EINT_FUNCTION(2, 87), + DRV_GRP1, MTK_FUNCTION(0, "GPIO219"), MTK_FUNCTION(1, "URXD3"), MTK_FUNCTION(2, "EINT87"), @@ -2200,9 +2419,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PWM4"), MTK_FUNCTION(7, "MD2_EINT4") ), - MTK_PIN(PINCTRL_PIN(220, "GPIO220"), - NULL, "mt6589", + MTK_PIN( + 220, "GPIO220", MTK_EINT_FUNCTION(2, 86), + DRV_GRP1, MTK_FUNCTION(0, "GPIO220"), MTK_FUNCTION(1, "UTXD3"), MTK_FUNCTION(2, "EINT86"), @@ -2212,9 +2432,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "PWM3"), MTK_FUNCTION(7, "MD2_EINT3") ), - MTK_PIN(PINCTRL_PIN(221, "GPIO221"), - NULL, "mt6589", + MTK_PIN( + 221, "GPIO221", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, MTK_FUNCTION(0, "GPIO221"), MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"), MTK_FUNCTION(3, "I2SIN_CK"), @@ -2223,9 +2444,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "IMG_TEST_CK"), MTK_FUNCTION(7, "USB_SCL") ), - MTK_PIN(PINCTRL_PIN(222, "GPIO222"), - NULL, "mt6589", + MTK_PIN( + 222, "GPIO222", MTK_EINT_FUNCTION(2, 16), + DRV_GRP3, MTK_FUNCTION(0, "GPIO222"), MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"), MTK_FUNCTION(2, "EINT16"), @@ -2233,9 +2455,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "PCM0_WS"), MTK_FUNCTION(6, "DISP_TEST_CK") ), - MTK_PIN(PINCTRL_PIN(223, "GPIO223"), - NULL, "mt6589", + MTK_PIN( + 223, "GPIO223", MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP3, MTK_FUNCTION(0, "GPIO223"), MTK_FUNCTION(1, "MRG_I2S_PCM_RX"), MTK_FUNCTION(3, "I2SIN_DAT"), @@ -2244,9 +2467,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(6, "MFG_TEST_CK"), MTK_FUNCTION(7, "USB_SDA") ), - MTK_PIN(PINCTRL_PIN(224, "GPIO224"), - NULL, "mt6589", + MTK_PIN( + 224, "GPIO224", MTK_EINT_FUNCTION(2, 17), + DRV_GRP3, MTK_FUNCTION(0, "GPIO224"), MTK_FUNCTION(1, "MRG_I2S_PCM_TX"), MTK_FUNCTION(2, "EINT17"), @@ -2254,9 +2478,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(4, "PCM0_DO"), MTK_FUNCTION(6, "VDEC_TEST_CK") ), - MTK_PIN(PINCTRL_PIN(225, "GPIO225"), - NULL, "mt6589", + MTK_PIN( + 225, "GPIO225", MTK_EINT_FUNCTION(2, 18), + DRV_GRP3, MTK_FUNCTION(0, "GPIO225"), MTK_FUNCTION(1, "MD1_DAI_RX_GPIO"), MTK_FUNCTION(2, "EINT18"), @@ -2265,9 +2490,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "DSP2_IMS"), MTK_FUNCTION(6, "VENC_TEST_CK") ), - MTK_PIN(PINCTRL_PIN(226, "GPIO226"), - NULL, "mt6589", + MTK_PIN( + 226, "GPIO226", MTK_EINT_FUNCTION(2, 71), + DRV_GRP4, MTK_FUNCTION(0, "GPIO226"), MTK_FUNCTION(1, "MSDC3_DAT2"), MTK_FUNCTION(2, "EINT71"), @@ -2276,9 +2502,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "CLKM4"), MTK_FUNCTION(7, "A_FUNC_DIN[0]") ), - MTK_PIN(PINCTRL_PIN(227, "GPIO227"), - NULL, "mt6589", + MTK_PIN( + 227, "GPIO227", MTK_EINT_FUNCTION(2, 72), + DRV_GRP4, MTK_FUNCTION(0, "GPIO227"), MTK_FUNCTION(1, "MSDC3_DAT3"), MTK_FUNCTION(2, "EINT72"), @@ -2287,9 +2514,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "CLKM5"), MTK_FUNCTION(7, "A_FUNC_CK") ), - MTK_PIN(PINCTRL_PIN(228, "GPIO228"), - NULL, "mt6589", + MTK_PIN( + 228, "GPIO228", MTK_EINT_FUNCTION(2, 68), + DRV_GRP4, MTK_FUNCTION(0, "GPIO228"), MTK_FUNCTION(1, "MSDC3_CMD"), MTK_FUNCTION(2, "EINT68"), @@ -2298,9 +2526,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "CLKM1"), MTK_FUNCTION(7, "A_FUNC_DIN[3]") ), - MTK_PIN(PINCTRL_PIN(229, "GPIO229"), - NULL, "mt6589", + MTK_PIN( + 229, "GPIO229", MTK_EINT_FUNCTION(2, 67), + DRV_GRP4, MTK_FUNCTION(0, "GPIO229"), MTK_FUNCTION(1, "MSDC3_CLK"), MTK_FUNCTION(2, "EINT67"), @@ -2309,9 +2538,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "CLKM0"), MTK_FUNCTION(7, "A_FUNC_DIN[4]") ), - MTK_PIN(PINCTRL_PIN(230, "GPIO230"), - NULL, "mt6589", + MTK_PIN( + 230, "GPIO230", MTK_EINT_FUNCTION(2, 70), + DRV_GRP4, MTK_FUNCTION(0, "GPIO230"), MTK_FUNCTION(1, "MSDC3_DAT1"), MTK_FUNCTION(2, "EINT70"), @@ -2320,9 +2550,10 @@ static const struct mtk_desc_pin mtk_pins_mt6589[] = { MTK_FUNCTION(5, "CLKM3"), MTK_FUNCTION(7, "A_FUNC_DIN[1]") ), - MTK_PIN(PINCTRL_PIN(231, "GPIO231"), - NULL, "mt6589", + MTK_PIN( + 231, "GPIO231", MTK_EINT_FUNCTION(2, 69), + DRV_GRP4, MTK_FUNCTION(0, "GPIO231"), MTK_FUNCTION(1, "MSDC3_DAT0"), MTK_FUNCTION(2, "EINT69"), From c2eeea144f74a6b5d783f32a7816b87452105663 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 21:09:55 +0900 Subject: [PATCH 39/98] pinctrl: mediatek: mt6589: fix syntax (#25) --- drivers/pinctrl/mediatek/pinctrl-mt6589.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6589.c b/drivers/pinctrl/mediatek/pinctrl-mt6589.c index 6149199e1a38e9..2c050f973e4849 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6589.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6589.c @@ -516,7 +516,7 @@ static const struct mtk_pin_field_calc mt6589_pin_pullsel_range[] = { PIN_FIELD_CALC(0, 43, 0, 0x0400, 0x10, 0, 1, 16, 0), PIN_FIELD_CALC(44, 46, 0, 0x0990, 0x0, 8, 1, 16, 0), PIN_FIELD_CALC(47, 49, 0, 0x09b0, 0x0, 8, 1, 16, 0), - PIN_FIELD_CALC(50, 113, 0, 0x0430, 0x10, 2, 1, 16, 0) + PIN_FIELD_CALC(50, 113, 0, 0x0430, 0x10, 2, 1, 16, 0), PIN_FIELD_CALC(114, 169, 1, 0x0470, 0x10, 2, 1, 16, 0), PIN_FIELD_CALC(170, 231, 0, 0x04a0, 0x10, 10, 1, 16, 0), }; From 67c4167f9b3f29092ee1a82ff292ac49ef09b685 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 21:20:53 +0900 Subject: [PATCH 40/98] arm: configs: lenovo-blade: add networking support Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 76b5a30f33b0a8..b491f635e5e13c 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -126,6 +126,9 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y ## GPU #CONFIG_SGX=y # not ported +## Networking +CONFIG_NET=y + ## Wi-Fi / Bluetooth ## Thermal From e34734ac0b801553e0df3bd20ca8e17f84c313d5 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 22:22:55 +0900 Subject: [PATCH 41/98] arm: dts: mediatek: mt6589: add i2c and spi Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 103 +++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index b6331ba16cbe82..ef3e24e467e743 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -120,6 +120,109 @@ #clock-cells = <1>; }; + i2c0: i2c@1100d000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x1100d000 0x1000>, + <0x11000300 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C0>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c1: i2c@1100e000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x1100e000 0x1000>, + <0x11000380 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C1>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c2: i2c@1100f000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x1100f000 0x1000>, + <0x11000400 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C2>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c3: i2c@11010000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x11010000 0x1000>, + <0x11000480 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C3>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c4: i2c@11011000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x11011000 0x1000>, + <0x11000500 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C4>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c5: i2c@11012000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x11012000 0x1000>, + <0x11000580 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI0_I2C5>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + i2c6: i2c@11013000 { + compatible = "mediatek,mt6589-i2c"; + reg = <0x11013000 0x1000>, + <0x11000600 0x80>; + interrupts = ; + clocks = <&pericfg CLK_PERI1_I2C6>, + <&clk26m>; + clock-names = "main", "pmic"; + clock-div = <16>; /* maybe */ + mediatek,have-pmic; + status = "disabled"; + }; + + spi1: spi@11016000 { + compatible = "mediatek,mt6589-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x11016000 0x1000>; + interrupts = ; + clocks = <&clk26m>, + <&topckgen CLK_TOP_MUX_SPI>, + <&pericfg CLK_PERI1_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + dispsys: syscon@14000000 { compatible = "mediatek,mt6589-dispsys", "syscon"; reg = <0x14000000 0x1000>; From 61f1730d2f069bdf09cf598429d22f9f705ab5cd Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 22:23:30 +0900 Subject: [PATCH 42/98] arm: configs: lenovo-blade: add CONFIG_UNIX --- arch/arm/configs/lenovo-blade_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index b491f635e5e13c..cc5bbd581da84b 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -128,6 +128,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y ## Networking CONFIG_NET=y +CONFIG_UNIX=y ## Wi-Fi / Bluetooth From 555c30b3e1c629bd29b938a8ee244b0ceba3fc6e Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 22:34:14 +0900 Subject: [PATCH 43/98] pinctrl: mediatek: mt6589: spi1 status = "disabled"; --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index ef3e24e467e743..b44d637394ddad 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -221,6 +221,7 @@ <&topckgen CLK_TOP_MUX_SPI>, <&pericfg CLK_PERI1_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; }; dispsys: syscon@14000000 { From 94a8ef735450d34d9783c2b233a0fbbfb627d150 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 7 Mar 2026 23:38:16 +0900 Subject: [PATCH 44/98] arm: configs: lenovo-blade: add rmi4 Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index cc5bbd581da84b..1cbcfc32e1e645 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -140,6 +140,12 @@ CONFIG_UNIX=y ## Camera +## Touchpanel +CONFIG_RMI4_CORE=y +CONFIG_RMI4_I2C=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F34=y + ## PWM #CONFIG_PWM=y #CONFIG_PWM_MEDIATEK From ae369069013abcaa2c1d17ad666fccf7ee4e5b29 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 8 Mar 2026 00:22:08 +0900 Subject: [PATCH 45/98] arm: dts: mt6589: fix i2c #size-cells #address-cells Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index b44d637394ddad..1a24f72be22d86 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -131,6 +131,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c1: i2c@1100e000 { @@ -144,6 +146,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c2: i2c@1100f000 { @@ -157,6 +161,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c3: i2c@11010000 { @@ -170,6 +176,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c4: i2c@11011000 { @@ -183,6 +191,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c5: i2c@11012000 { @@ -196,6 +206,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; i2c6: i2c@11013000 { @@ -209,6 +221,8 @@ clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; }; spi1: spi@11016000 { From 3d4d7ab163cf9a45d0fa99c1c8071ae93d5c69b9 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 8 Mar 2026 00:48:44 +0900 Subject: [PATCH 46/98] arm: dts: mediatek: mt6589: fix i2c, spi Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 37 +++++++++++++++----------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 1a24f72be22d86..8fcf9e4827496f 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -126,8 +126,9 @@ <0x11000300 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C0>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -141,8 +142,9 @@ <0x11000380 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C1>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -156,8 +158,9 @@ <0x11000400 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C2>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -171,8 +174,9 @@ <0x11000480 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C3>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -186,8 +190,9 @@ <0x11000500 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C4>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -201,8 +206,9 @@ <0x11000580 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI0_I2C5>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -216,8 +222,9 @@ <0x11000600 0x80>; interrupts = ; clocks = <&pericfg CLK_PERI1_I2C6>, - <&clk26m>; - clock-names = "main", "pmic"; + <&clk26m>, + <&pericfg CLK_PERI0_APDMA>; + clock-names = "main", "pmic", "dma"; clock-div = <16>; /* maybe */ mediatek,have-pmic; status = "disabled"; @@ -231,7 +238,7 @@ #size-cells = <0>; reg = <0x11016000 0x1000>; interrupts = ; - clocks = <&clk26m>, + clocks = <&clk26m>, /* FIXME */ <&topckgen CLK_TOP_MUX_SPI>, <&pericfg CLK_PERI1_SPI1>; clock-names = "parent-clk", "sel-clk", "spi-clk"; From 540c97c4e4f2510819ae0cc9645187d9631f7d75 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 8 Mar 2026 00:51:54 +0900 Subject: [PATCH 47/98] arm: configs: lenovo-blade: i2c devices Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 1cbcfc32e1e645..9e739d4d2656ae 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -100,9 +100,14 @@ CONFIG_USB_SERIAL=y CONFIG_MMC=y CONFIG_MMC_MTK=y -## Touchscreen -#CONFIG_INPUT_TOUCHSCREEN=y -#CONFIG_TOUCHSCREEN_S7300=y # not ported +CONFIG_IIO=y +## Accelerometer +CONFIG_BMC150_ACCEL=y +CONFIG_BMC150_ACCEL_I2C=y + +## Magnetometer +CONFIG_BMC150_MAGN=y +CONFIG_BMC150_MAGN_I2C=y ## PMIC #CONFIG_MTK_PMIC_WRAP=y From af57ecdd73a10e7258ec4ebdc0a869de812408fa Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 8 Mar 2026 00:52:21 +0900 Subject: [PATCH 48/98] arm: dts: mediatek: mt6589: lenovo-blade: add i2c devices Signed-off-by: Akari Tsuyukusa --- .../boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index af86a0f261488d..d781d6ec0274ec 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -44,6 +44,22 @@ }; }; +&i2c3 { + status = "okay"; + /* TODO */ + clock-frequency = <400000>; + + accelerometer@11 { + compatible = "bosch,bma255"; + reg = <0x11>; + }; + + magnetometer@13 { + compatible = "bosch,bmm150"; + reg = <0x13>; + }; +}; + &uart0 { status = "okay"; }; From b4e1fa43f8f4937d3921c288fbbca2de3aecbacf Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 8 Mar 2026 19:25:04 +0900 Subject: [PATCH 49/98] dt-bindings: pinctrl: mediatek: fix - remove todo - fix examples --- .../bindings/pinctrl/mediatek,mt6589-pinctrl.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml index bd9cacf1be01cb..cb31377d62ec93 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml @@ -111,7 +111,6 @@ patternProperties: slew-rate: enum: [0, 1] - # TODO mediatek,pull-up-adv: description: | Pull up settings for R0. User can configure those special pins. @@ -163,9 +162,10 @@ examples: usb_pins_default: usb-pins { pins_iddig { - pinmux = ; - input-enable; - bias-pull-up; + pinmux = ; + input-enable; + bias-pull-up; + } }; }; }; From 2744102a22de6eea744b43c8dd6225eca1cfd1fa Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 9 Mar 2026 01:54:41 +0900 Subject: [PATCH 50/98] dt-bindings: pinctrl: mediatek: remove unneeded newline --- .../devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml index cb31377d62ec93..9ba59a729fa0df 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6589-pinctrl.yaml @@ -169,4 +169,3 @@ examples: }; }; }; - From a2ee22c1378f7fc1c83353b9f9763391afce53fc Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Thu, 12 Mar 2026 00:08:05 +0900 Subject: [PATCH 51/98] arm: dts: mediatek: mt6589: fix pio --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 8fcf9e4827496f..80838446da9de7 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -277,7 +277,7 @@ reg-names = "gpio", "gpio1", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 232>; + gpio-ranges = <&pio 0 0 231>; interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; @@ -483,7 +483,8 @@ pins-clk { pinmux = ; drive-strength = <2>; - bias-pull-down = ; + bias-pull-down; + mediatek,pull-down-adv = ; }; */ pins-rst { @@ -604,7 +605,8 @@ ; input-enable; drive-strength = <4>; - bias-pull-up = ; + bias-pull-up; + mediatek,pull-up-adv = ; }; pins-clk { @@ -623,13 +625,15 @@ ; input-enable; drive-strength = <4>; - bias-pull-up = ; + bias-pull-up; + mediatek,pull-up-adv = ; }; pins-clk { pinmux = ; drive-strength = <4>; - bias-pull-down = ; + bias-pull-down; + mediatek,pull-up-adv = ; }; }; @@ -678,7 +682,8 @@ pins-clk { pinmux = ; drive-strength = <2>; - bias-pull-down = ; + bias-pull-down; + mediatek,pull-down-adv = ; }; pins-rst { From 27d899c32a9f2521a2b6a505217342bd5629cadb Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Thu, 12 Mar 2026 00:17:04 +0900 Subject: [PATCH 52/98] arm: dts: mediatek: mt6589: fix pio 2 --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 80838446da9de7..7de2c6a20c3d3d 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -277,7 +277,7 @@ reg-names = "gpio", "gpio1", "eint"; gpio-controller; #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 231>; + gpio-ranges = <&pio 0 0 232>; interrupt-controller; interrupt-parent = <&gic>; #interrupt-cells = <2>; From 682929a8cab56c8a96b1cda1099958363df31e8b Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 14:31:16 +0900 Subject: [PATCH 53/98] arm: dts: mediatek: rename b8000-f Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/Makefile | 2 +- ...t6589-lenovo-blade-b8000-f.dts => mt6589-lenovo-b8000-f.dts} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename arch/arm/boot/dts/mediatek/{mt6589-lenovo-blade-b8000-f.dts => mt6589-lenovo-b8000-f.dts} (100%) diff --git a/arch/arm/boot/dts/mediatek/Makefile b/arch/arm/boot/dts/mediatek/Makefile index 11761b916ccfcf..a01103e8f90c52 100644 --- a/arch/arm/boot/dts/mediatek/Makefile +++ b/arch/arm/boot/dts/mediatek/Makefile @@ -5,7 +5,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt6582-prestigio-pmt5008-3g.dtb \ mt6589-aquaris5.dtb \ mt6589-fairphone-fp1.dtb \ - mt6589-lenovo-blade-b8000-f.dtb \ + mt6589-lenovo-b8000-f.dtb \ mt6592-evb.dtb \ mt7623a-rfb-emmc.dtb \ mt7623a-rfb-nand.dtb \ diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts similarity index 100% rename from arch/arm/boot/dts/mediatek/mt6589-lenovo-blade-b8000-f.dts rename to arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts From ed1404a37c00c0b6122252376481112f944a1b9a Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 14:33:08 +0900 Subject: [PATCH 54/98] arm: dts: mediatek: drop lenovo,blade Signed-off-by: Akari Tsuyukusa --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 - arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts | 2 +- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 4a24b68f6dcbb8..9524bd135438f0 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -39,7 +39,6 @@ properties: - enum: - fairphone,fp1 - mundoreader,bq-aquaris5 - - lenovo,blade - lenovo,blade-b8000-f - lenovo,blade-b8000-h - lenovo,blade-b6000-f diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts index 5377465225a240..6ee5d2fb394451 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts @@ -8,7 +8,7 @@ / { model = "Lenovo YOGA Tablet 10 (Wi-Fi)"; - compatible = "lenovo,blade-b8000-f", "lenovo,blade", "mediatek,mt6589"; + compatible = "lenovo,blade-b8000-f", "mediatek,mt6589"; reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index d781d6ec0274ec..07f5e7454c527a 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -9,7 +9,6 @@ / { #address-cells = <1>; #size-cells = <1>; - compatible = "lenovo,blade", "mediatek,mt6589"; chosen { linux,initrd-start = <0x82600000>; From 197392e31cfffa61cf614ab97e3fe41e6fed7318 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 14:35:04 +0900 Subject: [PATCH 55/98] arm: dts: mediatek: fix blades Signed-off-by: Akari Tsuyukusa --- Documentation/devicetree/bindings/arm/mediatek.yaml | 9 +++++---- arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 9524bd135438f0..8bf43c012f4445 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -39,10 +39,11 @@ properties: - enum: - fairphone,fp1 - mundoreader,bq-aquaris5 - - lenovo,blade-b8000-f - - lenovo,blade-b8000-h - - lenovo,blade-b6000-f - - lenovo,blade-b8000-h + - lenovo,b6000-f + - lenovo,b6000-h + - lenovo,b6000-hv + - lenovo,b8000-f + - lenovo,b8000-h - const: mediatek,mt6589 - items: - enum: diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts index 6ee5d2fb394451..3410e1b8c1bb2a 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts @@ -8,7 +8,7 @@ / { model = "Lenovo YOGA Tablet 10 (Wi-Fi)"; - compatible = "lenovo,blade-b8000-f", "mediatek,mt6589"; + compatible = "lenovo,b8000-f", "mediatek,mt6589"; reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; From 4f61208d7a9d9c871c4e2ae57612a0e248ffa9f2 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 16:02:38 +0900 Subject: [PATCH 56/98] arm: dts: mediatek: blade: change license header These files actually exist from 2025, but the patch changed it to 2026, so I'll change it to 2026. Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts | 4 ++-- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts index 3410e1b8c1bb2a..0c86525a8ea8e2 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Copyright (c) 2025 akku + * Copyright (c) 2026 Akari Tsuyukusa */ #include "mt6589-lenovo-blade.dtsi" diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 07f5e7454c527a..777b9e0f78b10b 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Copyright (c) 2025 akku + * Copyright (c) 2026 Akari Tsuyukusa */ /dts-v1/; From 88ebcc345dfa04c1c92fa784b18e764ffc06043c Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 16:04:55 +0900 Subject: [PATCH 57/98] arm: dts: mediatek: blade: better simplefb memory needed to move simplefb node to b8000.dtsi Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 777b9e0f78b10b..1885fbca248ddf 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -27,15 +27,15 @@ ranges; - mtkfb_region: memory@bf600000{ - reg = <0xbf600000 (1280 * 800 * 2 * 2)>; + framebuffer_reserved: memory@bf600000{ + reg = <0xbf600000 0xa00000>; no-map; }; }; framebuffer0: framebuffer@bf600000 { compatible = "simple-framebuffer"; - reg = <0xbf600000 (1280 * 800 * 2)>; + reg = <&framebuffer_reserved>; width = <1280>; height = <800>; stride = <(1280 * 2)>; From 489c64d6b0d6ac47cd8a902ccbf10cfc388d1628 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 14 Mar 2026 16:08:31 +0900 Subject: [PATCH 58/98] arm: dts: mediatek: fix blade framebuffer Signed-off-by: Akari Tsuyukusa --- .../boot/dts/mediatek/mt6589-lenovo-b8000-f.dts | 2 +- .../boot/dts/mediatek/mt6589-lenovo-b8000.dtsi | 17 +++++++++++++++++ .../boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 9 --------- 3 files changed, 18 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts index 0c86525a8ea8e2..c2559cb029cfbf 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000-f.dts @@ -3,7 +3,7 @@ * Copyright (c) 2026 Akari Tsuyukusa */ -#include "mt6589-lenovo-blade.dtsi" +#include "mt6589-lenovo-b8000.dtsi" #include / { diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi new file mode 100644 index 00000000000000..a7ff72c94d6c31 --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright (c) 2026 Akari Tsuyukusa + */ + +#include "mt6589-lenovo-blade.dtsi" + +/ { + framebuffer0: framebuffer@bf600000 { + compatible = "simple-framebuffer"; + reg = <&framebuffer_reserved>; + width = <1280>; + height = <800>; + stride = <(1280 * 2)>; + format = "r5g6b5"; + }; +} diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 1885fbca248ddf..b85ba97fc7edbf 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -32,15 +32,6 @@ no-map; }; }; - - framebuffer0: framebuffer@bf600000 { - compatible = "simple-framebuffer"; - reg = <&framebuffer_reserved>; - width = <1280>; - height = <800>; - stride = <(1280 * 2)>; - format = "r5g6b5"; - }; }; &i2c3 { From fd249edf6fa16050356ae695cf0c63a63d35a245 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 15 Mar 2026 20:28:58 +0900 Subject: [PATCH 59/98] arm: dts: mediatek: blade: fix fb Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi | 4 ++-- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 3 --- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi index a7ff72c94d6c31..645267e60fe9b2 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-b8000.dtsi @@ -8,10 +8,10 @@ / { framebuffer0: framebuffer@bf600000 { compatible = "simple-framebuffer"; - reg = <&framebuffer_reserved>; + memory-region = <&framebuffer_reserved>; width = <1280>; height = <800>; stride = <(1280 * 2)>; format = "r5g6b5"; }; -} +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index b85ba97fc7edbf..6589dfcf739db8 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -7,9 +7,6 @@ #include "mt6589.dtsi" / { - #address-cells = <1>; - #size-cells = <1>; - chosen { linux,initrd-start = <0x82600000>; /* DEBUG: testing clock drivers */ From d4763919468fdd409f359cda2bea3428e4ef2429 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 15 Mar 2026 20:29:19 +0900 Subject: [PATCH 60/98] arm: defconfig: lenovo-blade: add CONFIG_ARM_ARCH_TIMER Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 9e739d4d2656ae..845e9dbdb7da12 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -54,6 +54,7 @@ CONFIG_COMMON_CLK_MT6589_VENCSYS=y ## Timer CONFIG_TIMER_OF=y +CONFIG_ARM_ARCH_TIMER=y CONFIG_MTK_TIMER=y ## Watchdog From 8d6cbaa43907efe4b693fd98a1648aded3ca5ee3 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 15 Mar 2026 21:19:42 +0900 Subject: [PATCH 61/98] arm: dts: mediatek: mt6589: arm,armv7-timer is not working Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 7de2c6a20c3d3d..10c901dd7d14c4 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -294,6 +294,18 @@ clock-names = "system-clk", "rtc-clk"; }; +/* + timer-arm { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; +*/ + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; From d4f7f634fec1bd34c518dc7cc783d5b7ab5a58e8 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 15 Mar 2026 21:38:48 +0900 Subject: [PATCH 62/98] arm: dts: mediatek: mt6589: arm,armv7-timer is working with unknown config Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 10c901dd7d14c4..ce940c302fa618 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -44,6 +44,17 @@ }; + timer-arm { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , /* maybe 11 */ + ; + clock-frequency = <13000000>; + arm,cpu-registers-not-fw-configured; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -294,18 +305,6 @@ clock-names = "system-clk", "rtc-clk"; }; -/* - timer-arm { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; - clock-frequency = <13000000>; - arm,cpu-registers-not-fw-configured; - }; -*/ - sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; From 9fb3642076fc85c890381f54a6c32df429436a20 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 16 Mar 2026 20:35:44 +0900 Subject: [PATCH 63/98] arm: dts: mediatek: lenovo-blade: drop: linux,initrd-start ATAGs support fills it --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index 6589dfcf739db8..bb7cdd881cd5aa 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -8,7 +8,6 @@ / { chosen { - linux,initrd-start = <0x82600000>; /* DEBUG: testing clock drivers */ bootargs = "clk_ignore_unused"; }; From 3da4de02640dbc262eb689d1714741b8c49dcf31 Mon Sep 17 00:00:00 2001 From: rva3 Date: Mon, 16 Mar 2026 14:05:01 +0200 Subject: [PATCH 64/98] clocksource: timer-mediatek: setup GPT6 to bring up arch timer The arch timer is using GPT6 as system counter. Program GPT6 to make arch timer work. Signed-off-by: rva3 --- drivers/clocksource/timer-mediatek.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clocksource/timer-mediatek.c b/drivers/clocksource/timer-mediatek.c index 7bcb4a3f26fb0e..1bc5562b78dbe6 100644 --- a/drivers/clocksource/timer-mediatek.c +++ b/drivers/clocksource/timer-mediatek.c @@ -22,6 +22,8 @@ #define TIMER_SYNC_TICKS (3) +#define TIMER_ARCH_TIMER_SRC (6) + /* gpt */ #define GPT_IRQ_EN_REG 0x00 #define GPT_IRQ_ENABLE(val) BIT((val) - 1) @@ -335,6 +337,9 @@ static int __init mtk_gpt_init(struct device_node *node) mtk_gpt_enable_irq(&to, TIMER_CLK_EVT); + /* Configure GPT6 to feed arch timer */ + mtk_gpt_setup(&to, TIMER_ARCH_TIMER_SRC, GPT_CTRL_OP_FREERUN); + return 0; } TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_gpt_init); From b481f10f624aef5d758cc75f069f3596caf0f1c8 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 16 Mar 2026 21:38:04 +0900 Subject: [PATCH 65/98] arm: defconfig: lenovo-blade: add CONFIG_PRINTK_TIME Signed-off-by: Akari Tsuyukusa --- arch/arm/configs/lenovo-blade_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 845e9dbdb7da12..70269fdf50122a 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -189,6 +189,7 @@ CONFIG_BLK_DEV_RAM=y CONFIG_KERNEL_GZIP=y CONFIG_VMSPLIT_3G_OPT=y CONFIG_THUMB2_KERNEL=y +CONFIG_PRINTK_TIME=y ### Hacking CONFIG_ARM_APPENDED_DTB=y From eef608ad1d024a14b63ee8cb28a76d04fcb13eb5 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 17 Mar 2026 23:01:16 +0900 Subject: [PATCH 66/98] arm: dts: mediatek: mt6589: add i2c pinctrl default Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index ce940c302fa618..a089a87bf25a9c 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -702,4 +702,36 @@ bias-pull-up; }; }; + + i2c0_pins: i2c0-default { + pins-i2c0 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c1_pins: i2c1-default { + pin-i2c1 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c2_pins: i2c2-default { + pin-i2c2 { + pinmux = , + ; + bias-disable; + }; + }; + + i2c3_pins: i2c3-default { + pin-i2c3 { + pinmux = , + ; + bias-disable; + }; + }; }; From cc015badca5dd0e31c6912627d17b4b9f5f5e3e1 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 18 Mar 2026 01:02:49 +0900 Subject: [PATCH 67/98] arm: dts: mediatek: mt6589: i2c clock-div is 16 i2c->clk = mt_get_bus_freq()/16; https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/drivers/i2c/i2c.c#L1096 i2c0: i2c@1100d000 { compatible = "mediatek,mt8135-i2c", "mediatek,mt6589-i2c"; reg = <0 0x1100d000 0 0x70>, <0 0x11000300 0 0x80>; interrupts = ; clock-div = <16>; clocks = <&i2c0_ck>, <&ap_dma_ck>; clock-names = "main", "dma"; }; https://github.com/djkurtz/chromiumos-third_party-kernel-mediatek/blob/3b4ee0da3c0fdab1c8a340bc055c96336d71d9e1/arch/arm/boot/dts/mt8135.dtsi#L486-L564 Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index a089a87bf25a9c..2d0536e880faf2 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -140,7 +140,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -156,7 +156,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -172,7 +172,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -188,7 +188,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -204,7 +204,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -220,7 +220,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; @@ -236,7 +236,7 @@ <&clk26m>, <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; - clock-div = <16>; /* maybe */ + clock-div = <16>; mediatek,have-pmic; status = "disabled"; #address-cells = <1>; From 0607ff06724be7e56f865b1018210e885e3ac862 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 18 Mar 2026 01:31:23 +0900 Subject: [PATCH 68/98] arm: dts: mediatek: mt6589: i2c related Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi | 4 +++- arch/arm/boot/dts/mediatek/mt6589.dtsi | 8 ++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index bb7cdd881cd5aa..e366e3f7a3332b 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -32,8 +32,10 @@ &i2c3 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; /* TODO */ - clock-frequency = <400000>; +// clock-frequency = <100000>; accelerometer@11 { compatible = "bosch,bma255"; diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 2d0536e880faf2..7d1e7e0a6647e5 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -707,7 +707,7 @@ pins-i2c0 { pinmux = , ; - bias-disable; + bias-pull-up; }; }; @@ -715,7 +715,7 @@ pin-i2c1 { pinmux = , ; - bias-disable; + bias-pull-up; }; }; @@ -723,7 +723,7 @@ pin-i2c2 { pinmux = , ; - bias-disable; + bias-pull-up; }; }; @@ -731,7 +731,7 @@ pin-i2c3 { pinmux = , ; - bias-disable; + bias-pull-up; }; }; }; From 495420820d07392aa1c091b5d79a8508bf11264b Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 25 Mar 2026 19:36:48 +0900 Subject: [PATCH 69/98] arm: dts: mediatek: mt6589: timer --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 7d1e7e0a6647e5..b2e3183fe11929 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -49,7 +49,7 @@ interrupt-parent = <&gic>; interrupts = , , - , /* maybe 11 */ + , ; clock-frequency = <13000000>; arm,cpu-registers-not-fw-configured; From a1de54c969e119341216ec06b14c8ef02fc0aaa2 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 25 Mar 2026 20:03:44 +0900 Subject: [PATCH 70/98] arm: dts: mediatek: mt6589: rename armv7-timer node --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index b2e3183fe11929..60f6b2797e34fa 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -44,7 +44,7 @@ }; - timer-arm { + arch_timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; interrupts = , From c2faf33934f4cece50dcfc188650f7687c71d86c Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 25 Mar 2026 23:38:12 +0900 Subject: [PATCH 71/98] arm: dts: mediatek: mt6589: re-rename generic timer --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 60f6b2797e34fa..b049f440bb30e1 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -44,7 +44,7 @@ }; - arch_timer { + timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; interrupts = , From 5fe51d7055c0bc661c6183de4c659e2cca8ec34f Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 25 Mar 2026 23:40:28 +0900 Subject: [PATCH 72/98] arm: dts: mediatek: mt6589: timer interrupts use IRQ_TYPE_LEVEL_HIGH --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index b049f440bb30e1..7befc2ce25f8ff 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -47,10 +47,10 @@ timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <13000000>; arm,cpu-registers-not-fw-configured; }; From 0c6061ad16315b4631adf7801dbebd161513cae3 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 27 Mar 2026 14:20:54 +0900 Subject: [PATCH 73/98] dt-bindings: gpu: pvrsgx: add mt6589-gpu --- Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml index f5898b04381cb6..43870d1c660390 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: - allwinner,sun6i-a31-gpu # MP2 Rev 115 + - mediatek,mt6589-gpu # MP1 Rev 115 - ti,omap4470-gpu # MP1 Rev 112 - ti,omap5432-gpu # MP2 Rev 105 - ti,am5728-gpu # MP2 Rev 116 From ee1f175d1f0f82d43d07d0884c866cad7eed0422 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 27 Mar 2026 14:25:51 +0900 Subject: [PATCH 74/98] arm: dts: mediatek: mt6589: add gpu node --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 7befc2ce25f8ff..059238f82dee7d 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -256,6 +256,16 @@ status = "disabled"; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt6589-gpu", "img,powervr-sgx544"; + reg = <0x13000000 0x10000>; + interrupts = ; + clocks = <&mfgsys CLK_MFG_G3D>, + <&mfgsys CLK_MFG_MEM>, + <&mfgsys CLK_MFG_AXI>; + clock-names = "core", "mem", "sys"; + }; + dispsys: syscon@14000000 { compatible = "mediatek,mt6589-dispsys", "syscon"; reg = <0x14000000 0x1000>; From f7916706c43cd11006eb58c16b5937c112d26b01 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 21 Jun 2026 18:00:11 +0900 Subject: [PATCH 75/98] add MT6320 driver (#19) * pinctrl: mediatek: init mt6320 driver * dt-bindings: soc: mediatek: pwrap: Add compatible for MT6589 SoC * arm: dts: mediatek: mt6589: add pwrap node * arm: dts: mediatek: mt6589: add pwrap reset * arm: dts: mediatek: mt6589: add pwrap-bridge reset * wip: soc: mediatek: pwrap: add mt6589 support * wip: soc: mediatek: pwrap: fix mt6589 * wip: soc: mediatek: pwrap: mt6589 and mt6320 porting * wip: soc: mediatek: pwrap: add mt6320 regs * wip: soc: mediatek: pwrap: add mt6589 regs * soc: mediatek: pwrap: rename PWRAP_MT8135_BRIDGE_* to PWRAP_BRIDGE_* because MT6589 also have these registers * soc: mediatek: pwrap: fix dew_regs for MT6589 * soc: mediatek: pwrap: add more PERI_PWRAP_BRIDGE registers MT6589 and MT8135 have PWRAP bridge registers with the same name and address. * soc: mediatek: pwrap: fix pwrap_regs for MT6589 The unique registers of MT8135 are the same as those of MT6589, so they have been made common. PWRAP_DVFS_ADR0 to PWRAP_DVFS_WDATA7 were in the MT8173 part, but these registers are used in many SoCs, not just the MT6589. * soc: mediatek: pwrap: mt6589 cleanup * soc: mediatek: pwrap: fix MT6320 regops * mfd: mt6320: add register index based on: https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/core/include/mach/mt_pmic.h#L56-L549 * arm: dts: mediatek: mt6589-lenovo-blade: add pmic * dt-bindings: soc: mediatek: pwrap: PMIC peripherals for MT6589 * dt-bindings: mfd: mediatek: add MT6320 binding * arm: configs: lenovo-blade: enable PWAP * soc: mediatek: fix mt6589/mt6320 * clk: mediatek: reindex mt6589 clocks * dt-bindings: mfd: mediatek: move mt6320 * mfd: mt6397: Add initial support for MT6320 (maybe broken) * pinctrl: mediatek: add MT6320 support * arm: configs: lenovo-blade: add CONFIG_MFD_MT6397 * arm: dts: lenovo-blade: add MT6320 Pinctrl * dt-bindings: reset: mt6589: format * mfd: mt6397-core: add MT6320 * mfd: mt6397-core: add mt6320 includes * mfd: mt6397-core: add mt6320 rtc defs * dt-bindings: mfd: mt6397: add mediatek,mt6320-rtc * arm: dts: mediatek: mt6589-lenovo-blade: add rtc * mfd: mt6320: add irq enum * mdf: rtc-mt6397: add mt6320 support * dt-bindings: input: mediatek,pmic-keys: add mediatek,mt6320-keys * mfd: mt6397-core: add mt6320-keys * arm: dts: mediatek: mt6589-lenovo-blade: add mt6320keys * mfd: mt6320: fix syntax * mfd: mt6397-core: fix mt6320 rtc * mfd: mt6397: Properly fix CID of MT6328, MT6331 and MT6332 CIDs set for MT6328, MT6331 and MT6332 are not appropriate. Many Android downstream kernels define CID as below, MT6328: #define PMIC6328_E1_CID_CODE 0x2810 #define PMIC6328_E2_CID_CODE 0x2820 #define PMIC6328_E3_CID_CODE 0x2830 MT6331/MT6332: #define PMIC6331_E1_CID_CODE 0x3110 #define PMIC6331_E2_CID_CODE 0x3120 #define PMIC6331_E3_CID_CODE 0x3130 #define PMIC6332_E1_CID_CODE 0x3210 #define PMIC6332_E2_CID_CODE 0x3220 #define PMIC6332_E3_CID_CODE 0x3230 The current configuration incorrectly uses the revision code as the CID. Therefore, the driver cannot detect the same PMIC of different revisions. (E1/E2 for MT6328, E1/E3 for MT6331/MT6332) Based on these, the CID of MT6328, MT6331 and MT6332 should be corrected. Additionally, the incorrect MT6331/MT6332 CID overlaps with the MT6320's actual CID: #define PMIC6320_E1_CID_CODE 0x1020 #define PMIC6320_E2_CID_CODE 0x2020 This causes a conflict in the switch-case statement of mt6397-irq.c, this prevents adding support for MT6320. Link: https://github.com/parthibx24/android_kernel_mediatek_k35/blob/4853d1fd9e40563573fa6d6b32b75d571a95e2b7/drivers/misc/mediatek/power/mt6735/pmic.h#L10-L12 Link: https://github.com/meizuosc/m75/blob/80ef1d26c5d73e131d064138ed09ff5a2be2bed8/mediatek/platform/mt6595/kernel/core/include/mach/pmic_mt6331_6332_sw.h#L9-L15 Link: https://github.com/toffyjan/android_Ticwatch_S_mooneye/blob/4f2a73b26f3821afc452cdce660cdbc73daf4e4a/arch/arm/mach-mt2601/include/mach/pmic_mt6320_sw.h#L29-L30 Signed-off-by: Akari Tsuyukusa * mfd: mt6320: fix * arm: dts: mediatek: split mt6320 * arm: dts: mediatek: mt6320: add license header * arm: configs: lenovo-blade: add CONFIG_POWER_RESET_MT6323 * arm: dts: mediatek: mt6320: fix fix * arm: dts: mediatek: mt6320: fix fix fix * arm: configs: lenovo-blade: add CONFIG_PINCTRL_MT6320 * pinctrl: mt6320: Add pinfunc header file for mt6320 * dt-bindings: mfd: mt6397: add mediatek,mt6320-regulator * mfd: mt6397-core: add mt6320-regulator * arm: configs: lenovo-blade: add needed * Input: mtk-pmic-keys: add mt6320 support * WIP: MT6320 regulator * regulator: mt6320: add header * regulator: mt6320: replace based on mt6323 * wip: regulator: mt6320: early porting * regulator: mt6320: todo note * soc: mediatek: mtk-pmic-wrap: drop pwrap_mt6589_init_soc_specific same as pwrap_mt8135_init_soc_specific, only watchdog timeout is different Signed-off-by: Akari Tsuyukusa * regulator: mt6320: by Claude * regulator: mt6320: Claude 2 * regulator: mt6320: Claude 3 Assisted-by: DeepSeek V4 Pro Assisted-by: Claude Sonnet 4.6 Signed-off-by: Akari Tsuyukusa --------- Signed-off-by: Akari Tsuyukusa --- .../bindings/input/mediatek,pmic-keys.yaml | 1 + .../bindings/mfd/mediatek,mt6397.yaml | 3 + .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 + .../regulator/mediatek,mt6320-regulator.yaml | 33 + .../bindings/soc/mediatek/mediatek,pwrap.yaml | 3 +- arch/arm/boot/dts/mediatek/mt6320.dtsi | 44 ++ .../dts/mediatek/mt6589-lenovo-blade.dtsi | 1 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 15 + arch/arm/configs/lenovo-blade_defconfig | 18 +- drivers/input/keyboard/mtk-pmic-keys.c | 15 + drivers/mfd/mt6397-core.c | 47 +- drivers/mfd/mt6397-irq.c | 8 + drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/pinctrl-mt6320.c | 65 ++ drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h | 368 ++++++++++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6320-regulator.c | 663 ++++++++++++++++++ drivers/rtc/rtc-mt6397.c | 1 + drivers/soc/mediatek/mtk-pmic-wrap.c | 292 ++++++-- include/dt-bindings/pinctrl/mt6320-pinfunc.h | 215 ++++++ include/dt-bindings/reset/mt6589-resets.h | 1 + include/linux/mfd/mt6320/core.h | 42 ++ include/linux/mfd/mt6320/registers.h | 505 +++++++++++++ include/linux/mfd/mt6397/core.h | 7 +- include/linux/regulator/mt6320-regulator.h | 57 ++ 26 files changed, 2354 insertions(+), 68 deletions(-) create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml create mode 100644 arch/arm/boot/dts/mediatek/mt6320.dtsi create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6320.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h create mode 100644 drivers/regulator/mt6320-regulator.c create mode 100644 include/dt-bindings/pinctrl/mt6320-pinfunc.h create mode 100644 include/linux/mfd/mt6320/core.h create mode 100644 include/linux/mfd/mt6320/registers.h create mode 100644 include/linux/regulator/mt6320-regulator.h diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b5f..970e1f6de3102a 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -24,6 +24,7 @@ description: | properties: compatible: enum: + - mediatek,mt6320-keys - mediatek,mt6323-keys - mediatek,mt6328-keys - mediatek,mt6331-keys diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 6a89b479d10fad..e1d581688d6a6a 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -34,6 +34,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320 - mediatek,mt6323 - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332. - mediatek,mt6328 @@ -64,6 +65,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320-rtc - mediatek,mt6323-rtc - mediatek,mt6331-rtc - mediatek,mt6358-rtc @@ -88,6 +90,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320-regulator - mediatek,mt6323-regulator - mediatek,mt6328-regulator - mediatek,mt6358-regulator diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index b9680b896f12f8..4c224d8be154ab 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6320-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml new file mode 100644 index 00000000000000..fb4cb5d1b0a24c --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6320-regulator.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6320-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6320 Regulator + +maintainers: + - Akari Tsuyukusa + +description: + Regulator function of MT6320 PMIC. + +properties: + compatible: + items: + - const: mediatek,mt6320-regulator + +patternProperties: + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + mt6320_regulators: regulators { + compatible = "mediatek,mt6320-regulator"; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 4737e5f45d5410..1162d3f96f101a 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -19,7 +19,7 @@ description: IP Pairing - On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + On MT6589 and MT8135 the pins of some SoC internal peripherals can be on the PMIC. The signals of these pins are routed over the SPI bus using the pwrap bridge. In the binding description below the properties needed for bridging are marked with "IP Pairing". These are optional on SoCs which do not support @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt2701-pwrap + - mediatek,mt6589-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap - mediatek,mt6795-pwrap diff --git a/arch/arm/boot/dts/mediatek/mt6320.dtsi b/arch/arm/boot/dts/mediatek/mt6320.dtsi new file mode 100644 index 00000000000000..3f2ae84f36fadc --- /dev/null +++ b/arch/arm/boot/dts/mediatek/mt6320.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2026 Akari Tsuyukusa + */ + +#include + +&pwrap { + pmic: mt6320 { + compatible = "mediatek,mt6320"; + + interrupt-parent = <&pio>; + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + pio6320: pinctrl { + compatible = "mediatek,mt6320-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + }; + + power-controller { + compatible = "mediatek,mt6323-pwrc"; + }; + + rtc { + compatible = "mediatek,mt6320-rtc"; + }; + + mt6320keys: keys { + compatible = "mediatek,mt6320-keys"; + + power { + linux,keycodes = ; + wakeup-source; + }; + + home { + linux,keycodes = ; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi index e366e3f7a3332b..a8fb11e3e3ac39 100644 --- a/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589-lenovo-blade.dtsi @@ -5,6 +5,7 @@ /dts-v1/; #include "mt6589.dtsi" +#include "mt6320.dtsi" / { chosen { diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 059238f82dee7d..9fe45d8a869743 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include / { @@ -315,6 +316,20 @@ clock-names = "system-clk", "rtc-clk"; }; + pwrap: pwrap@1000f000 { + compatible = "mediatek,mt6589-pwrap"; + reg = <0x1000f000 0x1000>, + <0x11017000 0x1000>; + reg-names = "pwrap", "pwrap-bridge"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_PMICSPI>, + <&infracfg CLK_INFRA_PMICWRAP>; + clock-names = "spi", "wrap"; + resets = <&infracfg MT6589_INFRA_PMIC_WRAP_RST>, + <&pericfg MT6589_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names = "pwrap", "pwrap-bridge"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq"; diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 70269fdf50122a..77d7bbd7b0191f 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -81,6 +81,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_MTK=y CONFIG_EINT_MTK=y CONFIG_PINCTRL_MT6589=y +CONFIG_PINCTRL_MT6320=y ## GPIO @@ -111,14 +112,21 @@ CONFIG_BMC150_MAGN=y CONFIG_BMC150_MAGN_I2C=y ## PMIC -#CONFIG_MTK_PMIC_WRAP=y +CONFIG_MTK_PMIC_WRAP=y +CONFIG_MFD_MT6397=y +CONFIG_REGULATOR_MT6320=y -## Power ? -#CONFIG_POWER_RESET=y +## Power +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_MT6323=y ## Reset #CONFIG_RESET_CONTROLLER +## Input +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_MTK_PMIC=y + ## Battery ## Regulator @@ -158,8 +166,8 @@ CONFIG_RMI4_F34=y #CONFIG_PWM_MTK_DISP=y ## RTC -#CONFIG_RTC_CLASS=y -#CONFIG_RTC_DRV_MT7622=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_MT6397=y ## Android #CONFIG_ANDROID_BINDER_IPC=y diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboard/mtk-pmic-keys.c index 061d48350df661..f8339b1211311e 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -56,6 +57,17 @@ struct mtk_pmic_regs { u32 rst_lprst_mask; /* Long-press reset timeout bitmask */ }; +static const struct mtk_pmic_regs mt6320_regs = { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6320_CHRSTATUS, + 0x8, MT6320_INT_RSV, 0x10, MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] = + MTK_PMIC_KEYS_REGS(MT6320_OCSTATUS2, + 0x10, MT6320_INT_RSV, 0x8, MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg = MT6320_TOP_RST_MISC, + .rst_lprst_mask = MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6397_regs = { .keys_regs[MTK_PMIC_PWRKEY_INDEX] = MTK_PMIC_KEYS_REGS(MT6397_CHRSTATUS, @@ -282,6 +294,9 @@ static DEFINE_SIMPLE_DEV_PM_OPS(mtk_pmic_keys_pm_ops, mtk_pmic_keys_suspend, static const struct of_device_id of_mtk_pmic_keys_match_tbl[] = { { + .compatible = "mediatek,mt6320-keys", + .data = &mt6320_regs, + }, { .compatible = "mediatek,mt6397-keys", .data = &mt6397_regs, }, { diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 5f8ed898890783..db2e1a954aee1c 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -19,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -27,6 +29,9 @@ #include #include +#define MT6320_RTC_BASE 0xe000 +#define MT6320_RTC_SIZE 0x3f + #define MT6323_RTC_BASE 0x8000 #define MT6323_RTC_SIZE 0x40 @@ -45,6 +50,11 @@ #define MT6323_PWRC_BASE 0x8000 #define MT6323_PWRC_SIZE 0x40 +static const struct resource mt6320_rtc_resources[] = { + DEFINE_RES_MEM(MT6320_RTC_BASE, MT6320_RTC_SIZE), + DEFINE_RES_IRQ(MT6320_IRQ_RTC), +}; + static const struct resource mt6323_rtc_resources[] = { DEFINE_RES_MEM(MT6323_RTC_BASE, MT6323_RTC_SIZE), DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC), @@ -70,6 +80,11 @@ static const struct resource mt6397_rtc_resources[] = { DEFINE_RES_IRQ(MT6397_IRQ_RTC), }; +static const struct resource mt6320_keys_resources[] = { + DEFINE_RES_IRQ_NAMED(MT6320_IRQ_PWRKEY, "powerkey"), + DEFINE_RES_IRQ_NAMED(MT6320_IRQ_HOMEKEY, "homekey"), +}; + static const struct resource mt6358_keys_resources[] = { DEFINE_RES_IRQ_NAMED(MT6358_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6358_IRQ_HOMEKEY, "homekey"), @@ -123,6 +138,23 @@ static const struct resource mt6323_pwrc_resources[] = { DEFINE_RES_MEM(MT6323_PWRC_BASE, MT6323_PWRC_SIZE), }; +static const struct mfd_cell mt6320_devs[] = { + { + .name = "mt6320-rtc", + .num_resources = ARRAY_SIZE(mt6320_rtc_resources), + .resources = mt6320_rtc_resources, + .of_compatible = "mediatek,mt6320-rtc", + }, { + .name = "mt6320-regulator", + .of_compatible = "mediatek,mt6320-regulator" + }, { + .name = "mtk-pmic-keys", + .num_resources = ARRAY_SIZE(mt6320_keys_resources), + .resources = mt6320_keys_resources, + .of_compatible = "mediatek,mt6320-keys", + }, +}; + static const struct mfd_cell mt6323_devs[] = { { .name = "mt6323-rtc", @@ -287,6 +319,14 @@ struct chip_data { int (*irq_init)(struct mt6397_chip *chip); }; +static const struct chip_data mt6320_core = { + .cid_addr = MT6320_CID, + .cid_shift = 0, + .cells = mt6320_devs, + .cell_size = ARRAY_SIZE(mt6320_devs), + .irq_init = mt6397_irq_init, +}; + static const struct chip_data mt6323_core = { .cid_addr = MT6323_CID, .cid_shift = 0, @@ -297,7 +337,7 @@ static const struct chip_data mt6323_core = { static const struct chip_data mt6328_core = { .cid_addr = MT6328_HWCID, - .cid_shift = 0, + .cid_shift = 8, .cells = mt6328_devs, .cell_size = ARRAY_SIZE(mt6328_devs), .irq_init = mt6397_irq_init, @@ -313,7 +353,7 @@ static const struct chip_data mt6357_core = { static const struct chip_data mt6331_mt6332_core = { .cid_addr = MT6331_HWCID, - .cid_shift = 0, + .cid_shift = 8, .cells = mt6331_mt6332_devs, .cell_size = ARRAY_SIZE(mt6331_mt6332_devs), .irq_init = mt6397_irq_init, @@ -399,6 +439,9 @@ static int mt6397_probe(struct platform_device *pdev) static const struct of_device_id mt6397_of_match[] = { { + .compatible = "mediatek,mt6320", + .data = &mt6320_core, + }, { .compatible = "mediatek,mt6323", .data = &mt6323_core, }, { diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index badc614b434527..aa913a496fd976 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -176,6 +178,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) mutex_init(&chip->irqlock); switch (chip->chip_id) { + case MT6320_CHIP_ID: + chip->int_con[0] = MT6320_INT_CON0; + chip->int_con[1] = MT6320_INT_CON1; + chip->int_status[0] = MT6320_INT_STATUS0; + chip->int_status[1] = MT6320_INT_STATUS1; + break; case MT6323_CHIP_ID: chip->int_con[0] = MT6323_INT_CON0; chip->int_con[1] = MT6323_INT_CON1; diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index b2d5637f4d1423..6c54b3ec44c594 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -307,6 +307,13 @@ config PINCTRL_MT8516 select PINCTRL_MTK # For PMIC +config PINCTRL_MT6320 + bool "MediaTek MT6320 pin control" + depends on MFD_MT6397 || COMPILE_TEST + depends on OF + default MFD_MT6397 + select PINCTRL_MTK + config PINCTRL_MT6397 bool "MediaTek MT6397 pin control" depends on MFD_MT6397 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6320.c b/drivers/pinctrl/mediatek/pinctrl-mt6320.c new file mode 100644 index 00000000000000..319190676ad4f4 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt6320.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015 MediaTek Inc. + * Author: Hongzhou.Yang + * + * Copyright (c) 2026 Akari Tsuyukusa + * + * MediaTek MT6320 PMIC Pinctrl Driver based on pinctrl-mt6397.c + */ + +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6320.h" + +#define MT6320_PIN_REG_BASE 0xc000 + +static const struct mtk_pinctrl_devdata mt6320_pinctrl_data = { + .pins = mtk_pins_mt6320, + .npins = ARRAY_SIZE(mtk_pins_mt6320), + .dir_offset = (MT6320_PIN_REG_BASE + 0x000), + .ies_offset = MTK_PINCTRL_NOT_SUPPORT, + .smt_offset = MTK_PINCTRL_NOT_SUPPORT, + .pullen_offset = (MT6320_PIN_REG_BASE + 0x020), + .pullsel_offset = (MT6320_PIN_REG_BASE + 0x040), + .dout_offset = (MT6320_PIN_REG_BASE + 0x080), + .din_offset = (MT6320_PIN_REG_BASE + 0x0a0), + .pinmux_offset = (MT6320_PIN_REG_BASE + 0x0c0), + .type1_start = 49, + .type1_end = 49, + .port_shf = 3, + .port_mask = 0x3, + .port_align = 2, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, +}; + +static int mt6320_pinctrl_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320; + + mt6320 = dev_get_drvdata(pdev->dev.parent); + return mtk_pctrl_init(pdev, &mt6320_pinctrl_data, mt6320->regmap); +} + +static const struct of_device_id mt6320_pctrl_match[] = { + { .compatible = "mediatek,mt6320-pinctrl", }, + { }, +}; + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt6320_pinctrl_probe, + .driver = { + .name = "mediatek-mt6320-pinctrl", + .of_match_table = mt6320_pctrl_match, + }, +}; + +builtin_platform_driver(mtk_pinctrl_driver); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h new file mode 100644 index 00000000000000..1525f3f88c387e --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6320.h @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Akari Tsuyukusa + */ + +#ifndef __PINCTRL_MTK_MT6320_H +#define __PINCTRL_MTK_MT6320_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6320[] = { + MTK_PIN(PINCTRL_PIN(0, "GPIO0"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "INT") + ), + MTK_PIN(PINCTRL_PIN(1, "GPIO1"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SRCVOLTEN") + ), + MTK_PIN(PINCTRL_PIN(2, "GPIO2"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SRCLKEN_PERI") + ), + MTK_PIN(PINCTRL_PIN(3, "GPIO3"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SRCLKEN_MD2") + ), + MTK_PIN(PINCTRL_PIN(4, "GPIO4"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "RTC_32K1V8") + ), + MTK_PIN(PINCTRL_PIN(5, "GPIO5"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "WRAP_EVENT") + ), + MTK_PIN(PINCTRL_PIN(6, "GPIO6"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI_CLK") + ), + MTK_PIN(PINCTRL_PIN(7, "GPIO7"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI_CSN") + ), + MTK_PIN(PINCTRL_PIN(8, "GPIO8"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SPI_MOSI") + ), + MTK_PIN(PINCTRL_PIN(9, "GPIO9"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SPI_MISO") + ), + MTK_PIN(PINCTRL_PIN(10, "GPIO10"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "ADC_CK") + ), + MTK_PIN(PINCTRL_PIN(11, "GPIO11"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "ADC_WS") + ), + MTK_PIN(PINCTRL_PIN(12, "GPIO12"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "ADC_DAT") + ), + MTK_PIN(PINCTRL_PIN(13, "GPIO13"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "DAC_CK") + ), + MTK_PIN(PINCTRL_PIN(14, "GPIO14"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "DAC_WS") + ), + MTK_PIN(PINCTRL_PIN(15, "GPIO15"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "DAC_DAT") + ), + MTK_PIN(PINCTRL_PIN(16, "GPIO16"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 10), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "COL0_USBDL"), + MTK_FUNCTION(2, "EINT10"), + MTK_FUNCTION(3, "PWM1_3X") + ), + MTK_PIN(PINCTRL_PIN(17, "GPIO17"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 11), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "COL1"), + MTK_FUNCTION(2, "EINT11"), + MTK_FUNCTION(3, "SCL0_2X") + ), + MTK_PIN(PINCTRL_PIN(18, "GPIO18"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 12), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "COL2"), + MTK_FUNCTION(2, "EINT12"), + MTK_FUNCTION(3, "SDA0_2X") + ), + MTK_PIN(PINCTRL_PIN(19, "GPIO19"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 13), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "COL3"), + MTK_FUNCTION(2, "EINT13"), + MTK_FUNCTION(3, "SCL1_2X") + ), + MTK_PIN(PINCTRL_PIN(20, "GPIO20"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 14), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "COL4"), + MTK_FUNCTION(2, "EINT14"), + MTK_FUNCTION(3, "SDA1_2X") + ), + MTK_PIN(PINCTRL_PIN(21, "GPIO21"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 15), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "COL5"), + MTK_FUNCTION(2, "EINT15"), + MTK_FUNCTION(3, "SCL2_2X") + ), + MTK_PIN(PINCTRL_PIN(22, "GPIO22"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 16), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "COL6"), + MTK_FUNCTION(2, "EINT16"), + MTK_FUNCTION(3, "SDA2_2X"), + MTK_FUNCTION(4, "GPIO32K_0"), + MTK_FUNCTION(5, "GPIO26M_0") + ), + MTK_PIN(PINCTRL_PIN(23, "GPIO23"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 17), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "COL7"), + MTK_FUNCTION(2, "EINT17"), + MTK_FUNCTION(3, "PWM2_3X"), + MTK_FUNCTION(4, "GPIO32K_1"), + MTK_FUNCTION(5, "GPIO26M_1") + ), + MTK_PIN(PINCTRL_PIN(24, "GPIO24"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 18), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "ROW0"), + MTK_FUNCTION(2, "EINT18"), + MTK_FUNCTION(3, "SCL0_3X") + ), + MTK_PIN(PINCTRL_PIN(25, "GPIO25"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 19), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "ROW1"), + MTK_FUNCTION(2, "EINT19"), + MTK_FUNCTION(3, "SDA0_3X") + ), + MTK_PIN(PINCTRL_PIN(26, "GPIO26"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 20), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "ROW2"), + MTK_FUNCTION(2, "EINT20"), + MTK_FUNCTION(3, "SCL1_3X") + ), + MTK_PIN(PINCTRL_PIN(27, "GPIO27"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 21), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "ROW3"), + MTK_FUNCTION(2, "EINT21"), + MTK_FUNCTION(3, "SDA1_3X") + ), + MTK_PIN(PINCTRL_PIN(28, "GPIO28"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 22), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "ROW4"), + MTK_FUNCTION(2, "EINT22"), + MTK_FUNCTION(3, "SCL2_3X") + ), + MTK_PIN(PINCTRL_PIN(29, "GPIO29"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 23), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "ROW5"), + MTK_FUNCTION(2, "EINT23"), + MTK_FUNCTION(3, "SDA2_3X") + ), + MTK_PIN(PINCTRL_PIN(30, "GPIO30"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 24), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "ROW6"), + MTK_FUNCTION(2, "EINT24"), + MTK_FUNCTION(3, "PWM3_3X"), + MTK_FUNCTION(4, "GPIO32K_2"), + MTK_FUNCTION(5, "GPIO26M_2") + ), + MTK_PIN(PINCTRL_PIN(31, "GPIO31"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 3), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "ROW7"), + MTK_FUNCTION(2, "EINT3"), + MTK_FUNCTION(4, "GPIO32K_3"), + MTK_FUNCTION(5, "GPIO26M_3") + ), + MTK_PIN(PINCTRL_PIN(32, "GPIO32"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 4), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "PWM1"), + MTK_FUNCTION(2, "EINT4"), + MTK_FUNCTION(4, "GPIO32K_4"), + MTK_FUNCTION(5, "GPIO26M_4") + ), + MTK_PIN(PINCTRL_PIN(33, "GPIO33"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 5), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "PWM2"), + MTK_FUNCTION(2, "EINT5"), + MTK_FUNCTION(4, "GPIO32K_5"), + MTK_FUNCTION(5, "GPIO26M_5") + ), + MTK_PIN(PINCTRL_PIN(34, "GPIO34"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 6), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "PWM3"), + MTK_FUNCTION(2, "EINT6"), + MTK_FUNCTION(3, "COL0"), + MTK_FUNCTION(4, "GPIO32K_6"), + MTK_FUNCTION(5, "GPIO26M_6") + ), + MTK_PIN(PINCTRL_PIN(35, "GPIO35"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 7), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(2, "EINT7"), + MTK_FUNCTION(3, "PWM1_2X") + ), + MTK_PIN(PINCTRL_PIN(36, "GPIO36"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 8), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(2, "EINT8") + ), + MTK_PIN(PINCTRL_PIN(37, "GPIO37"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 9), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "EINT9"), + MTK_FUNCTION(3, "PWM2_2X") + ), + MTK_PIN(PINCTRL_PIN(38, "GPIO38"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 0), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "EINT0") + ), + MTK_PIN(PINCTRL_PIN(39, "GPIO39"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 1), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(2, "EINT1"), + MTK_FUNCTION(3, "PWM3_2X") + ), + MTK_PIN(PINCTRL_PIN(40, "GPIO40"), + NULL, "mt6320", + MTK_EINT_FUNCTION(2, 2), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(2, "EINT2") + ), + MTK_PIN(PINCTRL_PIN(41, "GPIO41"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "SIM1_AP_SCLK") + ), + MTK_PIN(PINCTRL_PIN(42, "GPIO42"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "SIM1_AP_SRST") + ), + MTK_PIN(PINCTRL_PIN(43, "GPIO43"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "SIM2_AP_SCLK") + ), + MTK_PIN(PINCTRL_PIN(44, "GPIO44"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "SIM2_AP_SRST") + ), + MTK_PIN(PINCTRL_PIN(45, "GPIO45"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "SIMLS1_SCLK") + ), + MTK_PIN(PINCTRL_PIN(46, "GPIO46"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "SIMLS1_SRST") + ), + MTK_PIN(PINCTRL_PIN(47, "GPIO47"), + NULL, "mt6320", + MTK_EINT_FUNCTION(5, 10), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SIMLS2_SCLK"), + MTK_FUNCTION(5, "EINT10") + ), + MTK_PIN(PINCTRL_PIN(48, "GPIO48"), + NULL, "mt6320", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SIMLS2_SRST") + ), +}; + +#endif /* __PINCTRL_MTK_MT6320_H */ diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 6d8988387da459..442484847fa93e 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -864,6 +864,15 @@ config REGULATOR_MT6315 This driver supports the control of different power rails of device through regulator interface. +config REGULATOR_MT6320 + tristate "MediaTek MT6320 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6320 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6323 tristate "MediaTek MT6323 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index c0bc7a0f4e6709..e75a5565813f0c 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -103,6 +103,7 @@ obj-$(CONFIG_REGULATOR_MP886X) += mp886x.o obj-$(CONFIG_REGULATOR_MPQ7920) += mpq7920.o obj-$(CONFIG_REGULATOR_MT6311) += mt6311-regulator.o obj-$(CONFIG_REGULATOR_MT6315) += mt6315-regulator.o +obj-$(CONFIG_REGULATOR_MT6320) += mt6320-regulator.o obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o obj-$(CONFIG_REGULATOR_MT6331) += mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) += mt6332-regulator.o diff --git a/drivers/regulator/mt6320-regulator.c b/drivers/regulator/mt6320-regulator.c new file mode 100644 index 00000000000000..5531f742fb3d40 --- /dev/null +++ b/drivers/regulator/mt6320-regulator.c @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2026 Akari Tsuyukusa + * + * based on mt6320-regulator.c + * Copyright (c) 2016 MediaTek Inc. + * Author: Chen Zhong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MT6320_LDO_MODE_NORMAL 0 +#define MT6320_LDO_MODE_LP 1 + +/* + * MT6320 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators. + * BUCKs: BIT(13) within CON7. LDOs: BIT(15) within enable_reg. + * @vselon_reg: CON10 — BUCK voltage register used in HW-control mode. + * @vselctrl_reg: CON5 — selects SW vs HW voltage control for BUCKs. + * @vselctrl_mask: BIT(1) — VOSEL_CTRL bit in vselctrl_reg (all BUCKs). + * @modeset_reg: Register for Normal/Low-Power mode selection. + * @modeset_mask: Mask for the mode bit in modeset_reg. + */ +struct mt6320_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +/* + * BUCK register map (all addresses confirmed from upmu_hw.h CON definitions) + * -------------------------------------------------------------------------- + * CON2 CON5 CON7 CON9 CON10 + * modeset vselctrl enable+status vosel_sw voselon + * VPROC 0x020A 0x0210 0x0214 0x0218 0x021A + * VSRAM 0x0230 0x0236 0x023A 0x023E 0x0240 + * VCORE 0x025C 0x0262 0x0266 0x026A 0x026C + * VM 0x0282 0x0288 0x028C 0x0290 0x0292 + * VIO18 0x0304 0x030A 0x030E 0x0312 0x0314 + * VPA 0x032A 0x0330 0x0334 0x0338 0x033A + * VRF18 0x0354 0x035A 0x035E 0x0362 0x0364 + * VRF18_2 0x037E 0x0384 0x0388 0x038C 0x038E + * + * CON7 dual purpose: EN=BIT(0) (enable), qi=BIT(13) (HW status readback) + * CON5: VOSEL_CTRL=BIT(1) + * CON2: MODESET=BIT(8) (confirmed from PMIC_RG_Vxxx_MODESET_SHIFT=8) + * + * LDO register map (all confirmed from upmu_hw.h + upmu_common.c) + * ---------------------------------------------------------------- + * enable_reg = ANALDO_CONn or DIGLDO_CONn (see individual entries) + * EN bit = PMIC_RG_Vxxx_EN_SHIFT (each confirmed) + * modeset_reg = same as enable_reg (LP_SEL=BIT(0) in same register) + * vosel_reg = separate CON register per LDO + * vosel_mask = pre-shifted: raw_mask << shift + */ + +#define MT6320_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ + vosel, vosel_mask, voselon, vosel_ctrl, modesetreg) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_range_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = (max - min)/step + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .qi = BIT(13), \ + .vselon_reg = voselon, \ + .vselctrl_reg = vosel_ctrl, \ + .vselctrl_mask = BIT(1), \ + .modeset_reg = modesetreg, \ + .modeset_mask = BIT(8), \ +} + +/* + * MT6320_LDO — variable-voltage LDO with volt_table + * + * modeset_reg = enable_reg (LP_SEL=BIT(0) is in the same CON register as EN, + * confirmed for every LDO from upmu_common.c upmu_set_Vxxx_lp_sel()). + * modeset_mask = BIT(0). + */ +#define MT6320_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ + vosel_mask) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_table_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + }, \ + .qi = BIT(15), \ + .modeset_reg = enreg, \ + .modeset_mask = BIT(0), \ +} + +/* + * MT6320_REG_FIXED — fixed-voltage LDO + * + * Same LP_SEL=BIT(0) logic as MT6320_LDO. + * VTCXO_1 and VRTC have no LP_SEL in upmu_common.c; + * those two use modeset_reg=0/modeset_mask=0 via MT6320_REG_FIXED_NOLP. + */ +#define MT6320_REG_FIXED(match, vreg, enreg, enbit, volt) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .qi = BIT(15), \ + .modeset_reg = enreg, \ + .modeset_mask = BIT(0), \ +} + +#define MT6320_REG_FIXED_NOLP(match, vreg, enreg, enbit, volt) \ +[MT6320_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .ops = &mt6320_volt_fixed_ops, \ + .type = REGULATOR_VOLTAGE, \ + .id = MT6320_ID_##vreg, \ + .owner = THIS_MODULE, \ + .n_voltages = 1, \ + .enable_reg = enreg, \ + .enable_mask = BIT(enbit), \ + .min_uV = volt, \ + }, \ + .qi = BIT(15), \ + .modeset_reg = 0, \ + .modeset_mask = 0, \ +} + +/* + * BUCK voltage ranges + * ------------------- + * All vosel masks confirmed from PMIC_Vxxx_VOSEL_MASK in upmu_hw.h. + * Base voltages confirmed by back-calculating from real hardware readings. + * + * buck_volt_range1: 700 mV, 6.25 mV/step, 7-bit (mask=0x7F) + * VPROC: vosel=0x50 -> 700+80*6.25=1200 mV ✓ (real: 1200 mV) + * VSRAM: vosel=0x5A -> 700+90*6.25=1262.5 mV ✓ (real: 1262 mV, display truncated) + * VCORE: vosel=0x38 -> 700+56*6.25=1050 mV ✓ (real: 1050 mV) + * VM: vosel=0x52 -> 700+82*6.25=1212.5 mV ✓ (real: 1212 mV, display truncated) + * Applies to: VPROC, VSRAM, VCORE, VM + * + * buck_volt_range2: 500 mV, 50 mV/step, 6-bit (mask=0x3F) + * VPA: vosel=0 -> 500 mV ✓ (real: 500 mV = minimum) + * Applies to: VPA + * + * buck_volt_range3: 1500 mV, 20 mV/step, 5-bit (mask=0x1F) + * Confirmed from show_BUCK_VIO18_VOLTAGE() in pmic_mt6320.c: + * ret_value = 1500 + (reg_val * 20) + * Cross-check: real reading=1800 mV -> reg_val=(1800-1500)/20=15=0x0F ✓ + * Range: 1500 mV (vosel=0x00) to 2120 mV (vosel=0x1F) + * Applies to: VIO18 + * + * buck_volt_range4: 1050 mV, 25 mV/step, 5-bit (mask=0x1F) + * Confirmed by pmic_vrf18_2_usage_protection() in pmic_mt6320.c: + * gpu_status_bit=1 -> val=0x1F -> 1050 + 31*25 = 1825 mV (RF mode) ✓ + * gpu_status_bit=0 -> val=0x04 -> 1050 + 4*25 = 1150 mV (GPU OD mode) + * vosel=0x00 gives 1050 mV (GPU OD minimum per datasheet). + * VRF18 (1st RF) shares the same CON9 structure; it always operates at + * vosel=0x1F=1825 mV and never uses GPU OD mode. + * Applies to: VRF18, VRF18_2 + */ +static const struct linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000), +}; + +static const struct linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1050000, 0, 0x1f, 25000), +}; + +/* + * LDO voltage tables + * ------------------ + * All tables confirmed from dct_pmic_XXX_sel() in pmic_mt6320.c. + * Real hardware readings are noted where available. + * + * ldo_volt_table1: VMC — vosel BIT(4) + * Real: 3300 mV (vosel=1) + */ +static const unsigned int ldo_volt_table1[] = { + 1800000, 3300000, +}; + +/* + * ldo_volt_table2: VMCH, VEMC_3V3 — vosel BIT(7) + * Real: VMCH=3300 mV (vosel=1), VEMC_3V3=3300 mV (vosel=1) + */ +static const unsigned int ldo_volt_table2[] = { + 3000000, 3300000, +}; + +/* + * ldo_volt_table3: VEMC_1V8, VGP1-VGP6, VSIM1, VSIM2, VIBR — vosel [7:5] + * Real: VGP1=2800, VGP2=2800, VGP3=2800, VGP4=2800, VGP5=2800, VGP6=1800, + * VSIM1=1200, VSIM2=1200, VIBR=2800, VEMC_1V8=1800 mV + */ +static const unsigned int ldo_volt_table3[] = { + 1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000, +}; + +/* + * ldo_volt_table4: VAST — vosel [14:13] (descending) + * Real: 1200 mV (vosel=0) + */ +static const unsigned int ldo_volt_table4[] = { + 1200000, 1100000, 1000000, 900000, +}; + +/* + * ldo_volt_table5: VRF28_1, VRF28_2, VTCXO_2 — vosel BIT(3) + * Real: VRF28_1=2800, VRF28_2=1800, VTCXO_2=2800 mV + * Note: datasheet lists VRF28_1/2 output as 2.85 V; downstream and real + * hardware show 2800 mV for vosel=1. Using 2850 mV as per datasheet spec. + */ +static const unsigned int ldo_volt_table5[] = { + 1800000, 2850000, +}; + +/* + * ldo_volt_table6: VA — vosel BIT(6) + * Real: 1800 mV (vosel=0) + */ +static const unsigned int ldo_volt_table6[] = { + 1800000, 2500000, +}; + +/* + * ldo_volt_table7: VCAMA — vosel [7:6] = 0xC0 + * Real: 2800 mV (vosel=3) + */ +static const unsigned int ldo_volt_table7[] = { + 1500000, 1800000, 2500000, 2800000, +}; + +static int mt6320_get_status(struct regulator_dev *rdev) +{ + int ret; + u32 regval; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + ret = regmap_read(rdev->regmap, info->desc.enable_reg, ®val); + if (ret != 0) { + dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret); + return ret; + } + + return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF; +} + +static int mt6320_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + int ret, val = 0; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n", + info->desc.name); + return -EINVAL; + } + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val = MT6320_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val = MT6320_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<= ffs(info->modeset_mask) - 1; + + ret = regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + return ret; +} + +static unsigned int mt6320_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6320_regulator_info *info = rdev_get_drvdata(rdev); + + if (!info->modeset_mask) { + dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n", + info->desc.name); + return -EINVAL; + } + + ret = regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &= info->modeset_mask; + val >>= ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode = REGULATOR_MODE_STANDBY; + else + mode = REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6320_volt_range_ops = { + .list_voltage = regulator_list_voltage_linear_range, + .map_voltage = regulator_map_voltage_linear_range, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, + .set_mode = mt6320_ldo_set_mode, + .get_mode = mt6320_ldo_get_mode, +}; + +static const struct regulator_ops mt6320_volt_table_ops = { + .list_voltage = regulator_list_voltage_table, + .map_voltage = regulator_map_voltage_iterate, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, + .set_mode = mt6320_ldo_set_mode, + .get_mode = mt6320_ldo_get_mode, +}; + +static const struct regulator_ops mt6320_volt_fixed_ops = { + .list_voltage = regulator_list_voltage_linear, + .enable = regulator_enable_regmap, + .disable = regulator_disable_regmap, + .is_enabled = regulator_is_enabled_regmap, + .get_status = mt6320_get_status, + .set_mode = mt6320_ldo_set_mode, + .get_mode = mt6320_ldo_get_mode, +}; + +/* The array is indexed by id (MT6320_ID_XXX) */ +static struct mt6320_regulator_info mt6320_regulators[] = { + /* + * BUCKs + * ----- + * All addresses confirmed from upmu_hw.h VPROC_CONn etc. + * enable_reg = CON7 EN=BIT(0), qi=BIT(13) + * vselctrl = CON5 VOSEL_CTRL=BIT(1) + * vosel_sw = CON9 + * voselon = CON10 + * modeset = CON2 MODESET=BIT(8) + */ + + /* VPROC CPU 0.7-1.493 V (6.25 mV/step, mask=0x7F) */ + MT6320_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250, + buck_volt_range1, + 0x0214, /* CON7: enable + status */ + 0x0218, 0x7f, /* CON9: vosel_sw */ + 0x021A, /* CON10: voselon */ + 0x0210, /* CON5: vselctrl */ + 0x020A), /* CON2: modeset */ + + /* VSRAM Memory 0.7-1.493 V (6.25 mV/step, mask=0x7F) */ + MT6320_BUCK("buck_vsram", VSRAM, 700000, 1493750, 6250, + buck_volt_range1, + 0x023A, 0x023E, 0x7f, 0x0240, 0x0236, 0x0230), + + /* VCORE MDSYS/Infra 0.7-1.493 V (6.25 mV/step, mask=0x7F) */ + MT6320_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250, + buck_volt_range1, + 0x0266, 0x026A, 0x7f, 0x026C, 0x0262, 0x025C), + + /* VM 1.2-1.493 V (6.25 mV/step, mask=0x7F) */ + MT6320_BUCK("buck_vm", VM, 700000, 1493750, 6250, + buck_volt_range1, + 0x028C, 0x0290, 0x7f, 0x0292, 0x0288, 0x0282), + + /* VIO18 IO App. 1.5-2.12 V (20 mV/step, mask=0x1F, real: vosel=0x0F=1800 mV) */ + MT6320_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000, + buck_volt_range3, + 0x030E, 0x0312, 0x1f, 0x0314, 0x030A, 0x0304), + + /* VPA 3GPA 0.5-3.65 V (50 mV/step, mask=0x3F) */ + MT6320_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + buck_volt_range2, + 0x0334, 0x0338, 0x3f, 0x033A, 0x0330, 0x032A), + + /* VRF18 1st RF 1.825 V nominal (25 mV/step, mask=0x1F, vosel=0x1F=1825 mV) */ + MT6320_BUCK("buck_vrf18", VRF18, 1050000, 1825000, 25000, + buck_volt_range4, + 0x035E, 0x0362, 0x1f, 0x0364, 0x035A, 0x0354), + + /* + * VRF18_2 2nd RF / GPU OD (25 mV/step, mask=0x1F) + * vosel=0x1F -> 1825 mV (RF mode, confirmed from real hardware + usage_protection) + * vosel=0x04 -> 1150 mV (GPU OD mode, set by pmic_vrf18_2_usage_protection) + * vosel=0x00 -> 1050 mV (GPU OD minimum per datasheet) + */ + MT6320_BUCK("buck_vrf18_2", VRF18_2, 1050000, 1825000, 25000, + buck_volt_range4, + 0x0388, 0x038C, 0x1f, 0x038E, 0x0384, 0x037E), + + /* + * Analog LDOs + * ----------- + * enable_reg = ANALDO_CONn (confirmed from upmu_hw.h) + * EN bit = confirmed from PMIC_RG_Vxxx_EN_SHIFT + * LP_SEL = BIT(0) in same enable_reg (confirmed from upmu_common.c) + * vosel_reg = separate ANALDO_CONn + * vosel_mask = pre-shifted (raw_mask << shift) + * + * VRF28_1 / VRF28_2: datasheet 2.85 V; downstream uses same vosel + * encoding (0=1800/1=2850). Real hardware reads back 2800 mV for + * vosel=1 due to display truncation; 2850 mV is the correct spec value. + */ + + /* VRF28_1 MDSYS 1.8/2.85 V (ANALDO_CON0=0x0400, EN=BIT(12)) */ + MT6320_LDO("ldo_vrf28", VRF28, ldo_volt_table5, + 0x0400, 12, 0x0412, BIT(3)), + + /* + * VTCXO_1 MDSYS 2.8 V fixed (ANALDO_CON1=0x0402, EN=BIT(10)) + * No LP_SEL function in upmu_common.c for VTCXO_1 (ON_CTRL-managed). + */ + MT6320_REG_FIXED_NOLP("ldo_vtcxo", VTCXO, 0x0402, 10, 2800000), + + /* VA 1.8/2.5 V (ANALDO_CON2=0x0404, EN=BIT(14)) */ + MT6320_LDO("ldo_va", VA, ldo_volt_table6, + 0x0404, 14, 0x0410, BIT(6)), + + /* VA28 2.8 V fixed (ANALDO_CON3=0x0406, EN=BIT(14)) */ + MT6320_REG_FIXED("ldo_va28", VA28, 0x0406, 14, 2800000), + + /* VCAMA 1.5/1.8/2.5/2.8 V (ANALDO_CON4=0x0408, EN=BIT(15)) */ + MT6320_LDO("ldo_vcama", VCAMA, ldo_volt_table7, + 0x0408, 15, 0x0414, 0x3 << 6), + + /* VRF28_2 General 1.8/2.85 V (ANALDO_CON13=0x041A, EN=BIT(12)) */ + MT6320_LDO("ldo_vrf28_2", VRF28_2, ldo_volt_table5, + 0x041A, 12, 0x0418, BIT(3)), + + /* VTCXO_2 MDSYS 1.8/2.8 V (ANALDO_CON14=0x041C, EN=BIT(10)) */ + MT6320_LDO("ldo_vtcxo_2", VTCXO_2, ldo_volt_table5, + 0x041C, 10, 0x0416, BIT(3)), + + /* + * Digital LDOs + * ------------ + * enable_reg = DIGLDO_CONn (confirmed from upmu_hw.h) + * EN bit = confirmed from PMIC_RG_Vxxx_EN_SHIFT / PMIC_Vxxx_EN_SHIFT + * LP_SEL = BIT(0) in same enable_reg (confirmed from upmu_common.c) + * vosel_reg = separate DIGLDO_CONn + * vosel_mask = pre-shifted (raw_mask << shift) + */ + + /* VIO28 2.8 V fixed (DIGLDO_CON0=0x0420, EN=BIT(14)) */ + MT6320_REG_FIXED("ldo_vio28", VIO28, 0x0420, 14, 2800000), + + /* VUSB 3.3 V fixed (DIGLDO_CON2=0x0422, EN=BIT(14)) */ + MT6320_REG_FIXED("ldo_vusb", VUSB, 0x0422, 14, 3300000), + + /* VMC1 T-Card 1.8/3.3 V (DIGLDO_CON3=0x0424, EN=BIT(12)) */ + MT6320_LDO("ldo_vmc1", VMC1, ldo_volt_table1, + 0x0424, 12, 0x044A, BIT(4)), + + /* VMCH1 T-Card 3.0/3.3 V (DIGLDO_CON5=0x0426, EN=BIT(14)) */ + MT6320_LDO("ldo_vmch1", VMCH1, ldo_volt_table2, + 0x0426, 14, 0x044C, BIT(7)), + + /* VEMC_3V3 eMMC Core 3.0/3.3 V (DIGLDO_CON6=0x0428, EN=BIT(14)) */ + MT6320_LDO("ldo_vemc_3v3", VEMC_3V3, ldo_volt_table2, + 0x0428, 14, 0x044E, BIT(7)), + + /* VEMC_1V8 eMMC 1.2-3.3 V (DIGLDO_CON37=0x0462, EN=BIT(14)) */ + MT6320_LDO("ldo_vemc_1v8", VEMC_1V8, ldo_volt_table3, + 0x0462, 14, 0x0464, 0x7 << 5), + + /* VGP1 VCAMD 1.2-3.3 V (DIGLDO_CON7=0x042A, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp1", VGP1, ldo_volt_table3, + 0x042A, 15, 0x0450, 0x7 << 5), + + /* VGP2 VCAM_IO 1.2-3.3 V (DIGLDO_CON8=0x042C, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp2", VGP2, ldo_volt_table3, + 0x042C, 15, 0x0452, 0x7 << 5), + + /* VGP3 VCAM_AF 1.2-3.3 V (DIGLDO_CON9=0x042E, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp3", VGP3, ldo_volt_table3, + 0x042E, 15, 0x0454, 0x7 << 5), + + /* VGP4 CTP/CMMB 1.2-3.3 V (DIGLDO_CON10=0x0430, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp4", VGP4, ldo_volt_table3, + 0x0430, 15, 0x0456, 0x7 << 5), + + /* VGP5 CTP/CMMB 1.2-3.3 V (DIGLDO_CON11=0x0432, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp5", VGP5, ldo_volt_table3, + 0x0432, 15, 0x0458, 0x7 << 5), + + /* VGP6 CTP/CMMB 1.2-3.3 V (DIGLDO_CON12=0x0434, EN=BIT(15)) */ + MT6320_LDO("ldo_vgp6", VGP6, ldo_volt_table3, + 0x0434, 15, 0x045A, 0x7 << 5), + + /* VSIM1 1.2-3.3 V (DIGLDO_CON13=0x0436, EN=BIT(15)) */ + MT6320_LDO("ldo_vsim1", VSIM1, ldo_volt_table3, + 0x0436, 15, 0x045C, 0x7 << 5), + + /* VSIM2 1.2-3.3 V (DIGLDO_CON14=0x0438, EN=BIT(15)) */ + MT6320_LDO("ldo_vsim2", VSIM2, ldo_volt_table3, + 0x0438, 15, 0x045E, 0x7 << 5), + + /* VIBR Vibrator 1.2-3.3 V (DIGLDO_CON39=0x0466, EN=BIT(15)) */ + MT6320_LDO("ldo_vibr", VIBR, ldo_volt_table3, + 0x0466, 15, 0x0468, 0x7 << 5), + + /* + * VRTC RTC Block 2.8 V fixed (DIGLDO_CON15=0x043A, EN=BIT(8)) + * No LP_SEL function in upmu_common.c for VRTC. + */ + MT6320_REG_FIXED_NOLP("ldo_vrtc", VRTC, 0x043A, 8, 2800000), + + /* + * VAST MT6168 0.9-1.2 V (DIGLDO_CON20=0x0444, EN=BIT(12)) + * enable_reg and vosel_reg share the same address (DIGLDO_CON20). + * LP_SEL=BIT(0) also in DIGLDO_CON20. + */ + MT6320_LDO("ldo_vast", VAST, ldo_volt_table4, + 0x0444, 12, 0x0444, 0x3 << 13), +}; + +static int mt6320_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320 = dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i = 0; i < MT6320_MAX_REGULATOR; i++) { + if (mt6320_regulators[i].vselctrl_reg) { + if (regmap_read(mt6320->regmap, + mt6320_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6320_regulators[i].vselctrl_mask) { + mt6320_regulators[i].desc.vsel_reg = + mt6320_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6320_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6320 = dev_get_drvdata(pdev->dev.parent); + struct regulator_config config = {}; + struct regulator_dev *rdev; + int i; + u32 reg_value; + + /* Query buck controller to select activated voltage register part */ + if (mt6320_set_buck_vosel_reg(pdev)) + return -EIO; + + /* Read PMIC chip revision */ + if (regmap_read(mt6320->regmap, MT6320_CID, ®_value) < 0) { + dev_err(&pdev->dev, "Failed to read Chip ID\n"); + return -EIO; + } + dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value); + + for (i = 0; i < MT6320_MAX_REGULATOR; i++) { + config.dev = &pdev->dev; + config.driver_data = &mt6320_regulators[i]; + config.regmap = mt6320->regmap; + rdev = devm_regulator_register(&pdev->dev, + &mt6320_regulators[i].desc, &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6320_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + return 0; +} + +static const struct platform_device_id mt6320_platform_ids[] = { + {"mt6320-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6320_platform_ids); + +static struct platform_driver mt6320_regulator_driver = { + .driver = { + .name = "mt6320-regulator", + .probe_type = PROBE_PREFER_ASYNCHRONOUS, + }, + .probe = mt6320_regulator_probe, + .id_table = mt6320_platform_ids, +}; + +module_platform_driver(mt6320_regulator_driver); + +MODULE_AUTHOR("Akari Tsuyukusa "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6320 PMIC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/rtc/rtc-mt6397.c b/drivers/rtc/rtc-mt6397.c index 692c00ff544b22..8170eeb33e7eb8 100644 --- a/drivers/rtc/rtc-mt6397.c +++ b/drivers/rtc/rtc-mt6397.c @@ -331,6 +331,7 @@ static const struct mtk_rtc_data mt6397_rtc_data = { }; static const struct of_device_id mt6397_rtc_of_match[] = { + { .compatible = "mediatek,mt6320-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6323-rtc", .data = &mt6397_rtc_data }, { .compatible = "mediatek,mt6357-rtc", .data = &mt6358_rtc_data }, { .compatible = "mediatek,mt6358-rtc", .data = &mt6358_rtc_data }, diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c index 0bcd8582637550..6089ab790dfb8f 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -17,15 +17,31 @@ #define PWRAP_POLL_DELAY_US 10 #define PWRAP_POLL_TIMEOUT_US 10000 -#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 -#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 -#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 -#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 -#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 -#define PWRAP_MT8135_BRIDGE_INT_EN 0x38 -#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 -#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 -#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 +/* MT6589 and MT8135 specific PWARP Bridge registers */ +#define PWRAP_BRIDGE_IARB_INIT 0x0 +#define PWRAP_BRIDGE_IORD_ARB_EN 0x4 +#define PWRAP_BRIDGE_IARB_STA0 0x8 +#define PWRAP_BRIDGE_IARB_STA1 0xc +#define PWRAP_BRIDGE_WACS3_EN 0x10 +#define PWRAP_BRIDGE_INIT_DONE3 0x14 +#define PWRAP_BRIDGE_WACS3_CMD 0x18 +#define PWRAP_BRIDGE_WACS3_RDATA 0x1c +#define PWRAP_BRIDGE_WACS3_VLDCLR 0x20 +#define PWRAP_BRIDGE_WACS4_EN 0x24 +#define PWRAP_BRIDGE_INIT_DONE4 0x28 +#define PWRAP_BRIDGE_WACS4_CMD 0x2c +#define PWRAP_BRIDGE_WACS4_RDATA 0x30 +#define PWRAP_BRIDGE_WACS4_VLDCLR 0x34 +#define PWRAP_BRIDGE_INT_EN 0x38 +#define PWRAP_BRIDGE_INT_FLG_RAW 0x3c +#define PWRAP_BRIDGE_INT_FLG 0x40 +#define PWRAP_BRIDGE_INT_CLR 0x44 +#define PWRAP_BRIDGE_TIMER_EN 0x48 +#define PWRAP_BRIDGE_TIMER_STA 0x4c +#define PWRAP_BRIDGE_WDT_UNIT 0x50 +#define PWRAP_BRIDGE_WDT_SRC_EN 0x54 +#define PWRAP_BRIDGE_WDT_FLG 0x58 +#define PWRAP_BRIDGE_DEBUG_INT_SEL 0x5c /* macro for wrapper status */ #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) @@ -100,6 +116,24 @@ enum dew_regs { PWRAP_DEW_CIPHER_MODE, PWRAP_DEW_CIPHER_SWRST, + /* MT6320 only regs */ + PWRAP_DEW_CIPHER_IV0, + PWRAP_DEW_CIPHER_IV1, + PWRAP_DEW_CIPHER_IV2, + PWRAP_DEW_CIPHER_IV3, + PWRAP_DEW_CIPHER_IV4, + PWRAP_DEW_CIPHER_IV5, + + /* MT6320 and MT6397 only regs */ + PWRAP_DEW_EVENT_OUT_EN, + PWRAP_DEW_EVENT_SRC_EN, + PWRAP_DEW_EVENT_SRC, + PWRAP_DEW_EVENT_FLAG, + PWRAP_DEW_MON_FLAG_SEL, + PWRAP_DEW_EVENT_TEST, + PWRAP_DEW_CIPHER_LOAD, + PWRAP_DEW_CIPHER_START, + /* MT6323 only regs */ PWRAP_DEW_CIPHER_EN, PWRAP_DEW_RDDMY_NO, @@ -142,16 +176,34 @@ enum dew_regs { PWRAP_DEW_RG_WDATA_MASK, PWRAP_DEW_RG_SPI_RECORD_CLR, PWRAP_DEW_RG_CMD_ALERT_CLR, +}; - /* MT6397 only regs */ - PWRAP_DEW_EVENT_OUT_EN, - PWRAP_DEW_EVENT_SRC_EN, - PWRAP_DEW_EVENT_SRC, - PWRAP_DEW_EVENT_FLAG, - PWRAP_DEW_MON_FLAG_SEL, - PWRAP_DEW_EVENT_TEST, - PWRAP_DEW_CIPHER_LOAD, - PWRAP_DEW_CIPHER_START, +static const u32 mt6320_regs[] = { + [PWRAP_DEW_EVENT_OUT_EN] = 0x0000, + [PWRAP_DEW_DIO_EN] = 0x0002, + [PWRAP_DEW_EVENT_SRC_EN] = 0x0004, + [PWRAP_DEW_EVENT_SRC] = 0x0006, + [PWRAP_DEW_EVENT_FLAG] = 0x0008, + [PWRAP_DEW_READ_TEST] = 0x000a, + [PWRAP_DEW_WRITE_TEST] = 0x000c, + [PWRAP_DEW_CRC_EN] = 0x000e, + [PWRAP_DEW_CRC_VAL] = 0x0010, + [PWRAP_DEW_MON_GRP_SEL] = 0x0012, + [PWRAP_DEW_MON_FLAG_SEL] = 0x0014, + [PWRAP_DEW_EVENT_TEST] = 0x0016, + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0018, + [PWRAP_DEW_CIPHER_IV_SEL] = 0x001a, + [PWRAP_DEW_CIPHER_LOAD] = 0x001c, + [PWRAP_DEW_CIPHER_START] = 0x001e, + [PWRAP_DEW_CIPHER_RDY] = 0x0020, + [PWRAP_DEW_CIPHER_MODE] = 0x0022, + [PWRAP_DEW_CIPHER_SWRST] = 0x0024, + [PWRAP_DEW_CIPHER_IV0] = 0x0026, + [PWRAP_DEW_CIPHER_IV1] = 0x0028, + [PWRAP_DEW_CIPHER_IV2] = 0x002a, + [PWRAP_DEW_CIPHER_IV3] = 0x002c, + [PWRAP_DEW_CIPHER_IV4] = 0x002e, + [PWRAP_DEW_CIPHER_IV5] = 0x0030, }; static const u32 mt6323_regs[] = { @@ -386,6 +438,22 @@ enum pwrap_regs { PWRAP_EINT_STA1_ADR, PWRAP_SWINF_2_WDATA_31_0, PWRAP_SWINF_2_RDATA_31_0, + PWRAP_DVFS_ADR0, + PWRAP_DVFS_WDATA0, + PWRAP_DVFS_ADR1, + PWRAP_DVFS_WDATA1, + PWRAP_DVFS_ADR2, + PWRAP_DVFS_WDATA2, + PWRAP_DVFS_ADR3, + PWRAP_DVFS_WDATA3, + PWRAP_DVFS_ADR4, + PWRAP_DVFS_WDATA4, + PWRAP_DVFS_ADR5, + PWRAP_DVFS_WDATA5, + PWRAP_DVFS_ADR6, + PWRAP_DVFS_WDATA6, + PWRAP_DVFS_ADR7, + PWRAP_DVFS_WDATA7, /* MT2701 only regs */ PWRAP_ADC_CMD_ADDR, @@ -394,6 +462,24 @@ enum pwrap_regs { PWRAP_ADC_RDATA_ADDR1, PWRAP_ADC_RDATA_ADDR2, + /* MT6589 only regs */ + PWRAP_CIPHER_IV0, + PWRAP_CIPHER_IV1, + PWRAP_CIPHER_IV2, + + /* MT6589 and MT8135 only regs */ + PWRAP_CSHEXT, + PWRAP_EVENT_IN_EN, + PWRAP_EVENT_DST_EN, + PWRAP_RRARB_INIT, + PWRAP_RRARB_EN, + PWRAP_RRARB_STA0, + PWRAP_RRARB_STA1, + PWRAP_EVENT_STA, + PWRAP_EVENT_STACLR, + PWRAP_CIPHER_LOAD, + PWRAP_CIPHER_START, + /* MT7622 only regs */ PWRAP_STA, PWRAP_CLR, @@ -422,38 +508,9 @@ enum pwrap_regs { PWRAP_DVFS_STEP_CTRL2, PWRAP_SPI2_CTRL, - /* MT8135 only regs */ - PWRAP_CSHEXT, - PWRAP_EVENT_IN_EN, - PWRAP_EVENT_DST_EN, - PWRAP_RRARB_INIT, - PWRAP_RRARB_EN, - PWRAP_RRARB_STA0, - PWRAP_RRARB_STA1, - PWRAP_EVENT_STA, - PWRAP_EVENT_STACLR, - PWRAP_CIPHER_LOAD, - PWRAP_CIPHER_START, - /* MT8173 only regs */ PWRAP_RDDMY, PWRAP_SI_CK_CON, - PWRAP_DVFS_ADR0, - PWRAP_DVFS_WDATA0, - PWRAP_DVFS_ADR1, - PWRAP_DVFS_WDATA1, - PWRAP_DVFS_ADR2, - PWRAP_DVFS_WDATA2, - PWRAP_DVFS_ADR3, - PWRAP_DVFS_WDATA3, - PWRAP_DVFS_ADR4, - PWRAP_DVFS_WDATA4, - PWRAP_DVFS_ADR5, - PWRAP_DVFS_WDATA5, - PWRAP_DVFS_ADR6, - PWRAP_DVFS_WDATA6, - PWRAP_DVFS_ADR7, - PWRAP_DVFS_WDATA7, PWRAP_SPMINF_STA, PWRAP_CIPHER_EN, @@ -569,6 +626,98 @@ static const int mt2701_regs[] = { [PWRAP_ADC_RDATA_ADDR2] = 0x154, }; +static const int mt6589_regs[] = { + [PWRAP_MUX_SEL] = 0x0, + [PWRAP_WRAP_EN] = 0x4, + [PWRAP_DIO_EN] = 0x8, + [PWRAP_SIDLY] = 0xc, + [PWRAP_CSHEXT] = 0x10, + [PWRAP_CSHEXT_WRITE] = 0x14, + [PWRAP_CSHEXT_READ] = 0x18, + [PWRAP_CSLEXT_START] = 0x1c, + [PWRAP_CSLEXT_END] = 0x20, + [PWRAP_STAUPD_PRD] = 0x24, + [PWRAP_STAUPD_GRPEN] = 0x28, + [PWRAP_STAUPD_MAN_TRIG] = 0x2c, + [PWRAP_STAUPD_STA] = 0x30, + [PWRAP_EVENT_IN_EN] = 0x34, + [PWRAP_EVENT_DST_EN] = 0x38, + [PWRAP_WRAP_STA] = 0x3c, + [PWRAP_RRARB_INIT] = 0x40, + [PWRAP_RRARB_EN] = 0x44, + [PWRAP_RRARB_STA0] = 0x48, + [PWRAP_RRARB_STA1] = 0x4c, + [PWRAP_HARB_INIT] = 0x50, + [PWRAP_HARB_HPRIO] = 0x54, + [PWRAP_HIPRIO_ARB_EN] = 0x58, + [PWRAP_HARB_STA0] = 0x5c, + [PWRAP_HARB_STA1] = 0x60, + [PWRAP_MAN_EN] = 0x64, + [PWRAP_MAN_CMD] = 0x68, + [PWRAP_MAN_RDATA] = 0x6c, + [PWRAP_MAN_VLDCLR] = 0x70, + [PWRAP_WACS0_EN] = 0x74, + [PWRAP_INIT_DONE0] = 0x78, + [PWRAP_WACS0_CMD] = 0x7c, + [PWRAP_WACS0_RDATA] = 0x80, + [PWRAP_WACS0_VLDCLR] = 0x84, + [PWRAP_WACS1_EN] = 0x88, + [PWRAP_INIT_DONE1] = 0x8c, + [PWRAP_WACS1_CMD] = 0x90, + [PWRAP_WACS1_RDATA] = 0x94, + [PWRAP_WACS1_VLDCLR] = 0x98, + [PWRAP_WACS2_EN] = 0x9c, + [PWRAP_INIT_DONE2] = 0xa0, + [PWRAP_WACS2_CMD] = 0xa4, + [PWRAP_WACS2_RDATA] = 0xa8, + [PWRAP_WACS2_VLDCLR] = 0xac, + [PWRAP_INT_EN] = 0xb0, + [PWRAP_INT_FLG_RAW] = 0xb4, + [PWRAP_INT_FLG] = 0xb8, + [PWRAP_INT_CLR] = 0xbc, + [PWRAP_SIG_ADR] = 0xc0, + [PWRAP_SIG_MODE] = 0xc4, + [PWRAP_SIG_VALUE] = 0xc8, + [PWRAP_SIG_ERRVAL] = 0xcc, + [PWRAP_CRC_EN] = 0xd0, + [PWRAP_EVENT_STA] = 0xd4, + [PWRAP_EVENT_STACLR] = 0xd8, + [PWRAP_TIMER_EN] = 0xdc, + [PWRAP_TIMER_STA] = 0xe0, + [PWRAP_WDT_UNIT] = 0xe4, + [PWRAP_WDT_SRC_EN] = 0xe8, + [PWRAP_WDT_FLG] = 0xec, + [PWRAP_DEBUG_INT_SEL] = 0xf0, + [PWRAP_DVFS_ADR0] = 0xf4, + [PWRAP_DVFS_WDATA0] = 0xf8, + [PWRAP_DVFS_ADR1] = 0xfc, + [PWRAP_DVFS_WDATA1] = 0x100, + [PWRAP_DVFS_ADR2] = 0x104, + [PWRAP_DVFS_WDATA2] = 0x108, + [PWRAP_DVFS_ADR3] = 0x10c, + [PWRAP_DVFS_WDATA3] = 0x110, + [PWRAP_DVFS_ADR4] = 0x114, + [PWRAP_DVFS_WDATA4] = 0x118, + [PWRAP_DVFS_ADR5] = 0x11c, + [PWRAP_DVFS_WDATA5] = 0x120, + [PWRAP_DVFS_ADR6] = 0x124, + [PWRAP_DVFS_WDATA6] = 0x128, + [PWRAP_DVFS_ADR7] = 0x12c, + [PWRAP_DVFS_WDATA7] = 0x130, + [PWRAP_CIPHER_KEY_SEL] = 0x134, + [PWRAP_CIPHER_IV_SEL] = 0x138, + [PWRAP_CIPHER_LOAD] = 0x13c, + [PWRAP_CIPHER_START] = 0x140, + [PWRAP_CIPHER_RDY] = 0x144, + [PWRAP_CIPHER_MODE] = 0x148, + [PWRAP_CIPHER_SWRST] = 0x14c, + [PWRAP_CIPHER_IV0] = 0x150, + [PWRAP_CIPHER_IV1] = 0x154, + [PWRAP_CIPHER_IV2] = 0x158, + [PWRAP_DCM_EN] = 0x15c, + [PWRAP_DCM_DBC_PRD] = 0x160, +}; + static const int mt6765_regs[] = { [PWRAP_MUX_SEL] = 0x0, [PWRAP_WRAP_EN] = 0x4, @@ -1301,6 +1450,7 @@ static const int mt8186_regs[] = { }; enum pmic_type { + PMIC_MT6320, PMIC_MT6323, PMIC_MT6331, PMIC_MT6332, @@ -1314,6 +1464,7 @@ enum pmic_type { enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6589, PWRAP_MT6765, PWRAP_MT6779, PWRAP_MT6795, @@ -1750,6 +1901,7 @@ static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp) case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); @@ -1834,6 +1986,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); switch (wrp->master->type) { + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); pwrap_writel(wrp, 1, PWRAP_CIPHER_START); @@ -1866,6 +2019,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); switch (wrp->slave->type) { + case PMIC_MT6320: case PMIC_MT6397: pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1); @@ -1960,13 +2114,13 @@ static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp) /* enable pwrap events and pwrap bridge in AP side */ pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); - writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); - writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); - writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); + writel(0x7f, wrp->bridge_base + PWRAP_BRIDGE_IORD_ARB_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS3_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS4_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WDT_UNIT); + writel(0xffff, wrp->bridge_base + PWRAP_BRIDGE_WDT_SRC_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_TIMER_EN); + writel(0x7ff, wrp->bridge_base + PWRAP_BRIDGE_INT_EN); /* enable PMIC event out and sources */ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], @@ -2110,7 +2264,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) return ret; } - if (wrp->master->type == PWRAP_MT8135) + if (wrp->master->type == PWRAP_MT8135 || + wrp->master->type == PWRAP_MT6589) pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); @@ -2131,8 +2286,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE3); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE4); } return 0; @@ -2186,6 +2341,14 @@ static const struct pwrap_slv_regops pwrap_regops32 = { .regmap = &pwrap_regmap_config32, }; +static const struct pwrap_slv_type pmic_mt6320 = { + .dew_regs = mt6320_regs, + .type = PMIC_MT6320, + .regops = &pwrap_regops16, + .caps = PWRAP_SLV_CAP_SPI | PWRAP_DEW_DIO_EN | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6323 = { .dew_regs = mt6323_regs, .type = PMIC_MT6323, @@ -2248,6 +2411,7 @@ static const struct pwrap_slv_type pmic_mt6397 = { }; static const struct of_device_id of_slave_match_tbl[] = { + { .compatible = "mediatek,mt6320", .data = &pmic_mt6320 }, { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 }, { .compatible = "mediatek,mt6331", .data = &pmic_mt6331 }, { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 }, @@ -2277,6 +2441,19 @@ static const struct pmic_wrapper_type pwrap_mt2701 = { .init_soc_specific = pwrap_mt2701_init_soc_specific, }; +static const struct pmic_wrapper_type pwrap_mt6589 = { + .regs = mt6589_regs, + .type = PWRAP_MT6589, + .arb_en_all = 0x1ff, + .int_en_all = 0x7ffffffd, + .int1_en_all = 0, + .spi_w = PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src = PWRAP_WDT_SRC_MASK_ALL, + .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock = pwrap_common_init_reg_clock, + .init_soc_specific = pwrap_mt8135_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6765 = { .regs = mt6765_regs, .type = PWRAP_MT6765, @@ -2446,6 +2623,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = { static const struct of_device_id of_pwrap_match_tbl[] = { { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 }, + { .compatible = "mediatek,mt6589-pwrap", .data = &pwrap_mt6589 }, { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 }, { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 }, { .compatible = "mediatek,mt6795-pwrap", .data = &pwrap_mt6795 }, diff --git a/include/dt-bindings/pinctrl/mt6320-pinfunc.h b/include/dt-bindings/pinctrl/mt6320-pinfunc.h new file mode 100644 index 00000000000000..173a11f12b9183 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt6320-pinfunc.h @@ -0,0 +1,215 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DTS_MT6320_PINFUNC_H +#define __DTS_MT6320_PINFUNC_H + +#include + + +#define MT6320_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6320_PIN_0_GPIO0__FUNC_INT (MTK_PIN_NO(0) | 1) + +#define MT6320_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6320_PIN_1_GPIO1__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1) + +#define MT6320_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6320_PIN_2_GPIO2__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1) + +#define MT6320_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6320_PIN_3_GPIO3__FUNC_SRCLKEN_MD2 (MTK_PIN_NO(3) | 1) + +#define MT6320_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6320_PIN_4_GPIO4__FUNC_RTC_32K1V8 (MTK_PIN_NO(4) | 1) + +#define MT6320_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6320_PIN_5_GPIO5__FUNC_WRAP_EVENT (MTK_PIN_NO(5) | 1) + +#define MT6320_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6320_PIN_6_GPIO6__FUNC_SPI_CLK (MTK_PIN_NO(6) | 1) + +#define MT6320_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT6320_PIN_7_GPIO7__FUNC_SPI_CSN (MTK_PIN_NO(7) | 1) + +#define MT6320_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT6320_PIN_8_GPIO8__FUNC_SPI_MOSI (MTK_PIN_NO(8) | 1) + +#define MT6320_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT6320_PIN_9_GPIO9__FUNC_SPI_MISO (MTK_PIN_NO(9) | 1) + +#define MT6320_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT6320_PIN_10_GPIO10__FUNC_ADC_CK (MTK_PIN_NO(10) | 1) + +#define MT6320_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT6320_PIN_11_GPIO11__FUNC_ADC_WS (MTK_PIN_NO(11) | 1) + +#define MT6320_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT6320_PIN_12_GPIO12__FUNC_ADC_DAT (MTK_PIN_NO(12) | 1) + +#define MT6320_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT6320_PIN_13_GPIO13__FUNC_DAC_CK (MTK_PIN_NO(13) | 1) + +#define MT6320_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT6320_PIN_14_GPIO14__FUNC_DAC_WS (MTK_PIN_NO(14) | 1) + +#define MT6320_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT6320_PIN_15_GPIO15__FUNC_DAC_DAT (MTK_PIN_NO(15) | 1) + +#define MT6320_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT6320_PIN_16_GPIO16__FUNC_COL0_USBDL (MTK_PIN_NO(16) | 1) +#define MT6320_PIN_16_GPIO16__FUNC_EINT10 (MTK_PIN_NO(16) | 2) +#define MT6320_PIN_16_GPIO16__FUNC_PWM1_3X (MTK_PIN_NO(16) | 3) + +#define MT6320_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT6320_PIN_17_GPIO17__FUNC_COL1 (MTK_PIN_NO(17) | 1) +#define MT6320_PIN_17_GPIO17__FUNC_EINT11 (MTK_PIN_NO(17) | 2) +#define MT6320_PIN_17_GPIO17__FUNC_SCL0_2X (MTK_PIN_NO(17) | 3) + +#define MT6320_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT6320_PIN_18_GPIO18__FUNC_COL2 (MTK_PIN_NO(18) | 1) +#define MT6320_PIN_18_GPIO18__FUNC_EINT12 (MTK_PIN_NO(18) | 2) +#define MT6320_PIN_18_GPIO18__FUNC_SDA0_2X (MTK_PIN_NO(18) | 3) + +#define MT6320_PIN_19_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT6320_PIN_19_GPIO19__FUNC_COL3 (MTK_PIN_NO(19) | 1) +#define MT6320_PIN_19_GPIO19__FUNC_EINT13 (MTK_PIN_NO(19) | 2) +#define MT6320_PIN_19_GPIO19__FUNC_SCL1_2X (MTK_PIN_NO(19) | 3) + +#define MT6320_PIN_20_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT6320_PIN_20_GPIO20__FUNC_COL4 (MTK_PIN_NO(20) | 1) +#define MT6320_PIN_20_GPIO20__FUNC_EINT14 (MTK_PIN_NO(20) | 2) +#define MT6320_PIN_20_GPIO20__FUNC_SDA1_2X (MTK_PIN_NO(20) | 3) + +#define MT6320_PIN_21_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT6320_PIN_21_GPIO21__FUNC_COL5 (MTK_PIN_NO(21) | 1) +#define MT6320_PIN_21_GPIO21__FUNC_EINT15 (MTK_PIN_NO(21) | 2) +#define MT6320_PIN_21_GPIO21__FUNC_SCL2_2X (MTK_PIN_NO(21) | 3) + +#define MT6320_PIN_22_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT6320_PIN_22_GPIO22__FUNC_COL6 (MTK_PIN_NO(22) | 1) +#define MT6320_PIN_22_GPIO22__FUNC_EINT16 (MTK_PIN_NO(22) | 2) +#define MT6320_PIN_22_GPIO22__FUNC_SDA2_2X (MTK_PIN_NO(22) | 3) +#define MT6320_PIN_22_GPIO22__FUNC_GPIO32K_0 (MTK_PIN_NO(22) | 4) +#define MT6320_PIN_22_GPIO22__FUNC_GPIO26M_0 (MTK_PIN_NO(22) | 5) + +#define MT6320_PIN_23_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT6320_PIN_23_GPIO23__FUNC_COL7 (MTK_PIN_NO(23) | 1) +#define MT6320_PIN_23_GPIO23__FUNC_EINT17 (MTK_PIN_NO(23) | 2) +#define MT6320_PIN_23_GPIO23__FUNC_PWM2_3X (MTK_PIN_NO(23) | 3) +#define MT6320_PIN_23_GPIO23__FUNC_GPIO32K_1 (MTK_PIN_NO(23) | 4) +#define MT6320_PIN_23_GPIO23__FUNC_GPIO26M_1 (MTK_PIN_NO(23) | 5) + +#define MT6320_PIN_24_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT6320_PIN_24_GPIO24__FUNC_ROW0 (MTK_PIN_NO(24) | 1) +#define MT6320_PIN_24_GPIO24__FUNC_EINT18 (MTK_PIN_NO(24) | 2) +#define MT6320_PIN_24_GPIO24__FUNC_SCL0_3X (MTK_PIN_NO(24) | 3) + +#define MT6320_PIN_25_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT6320_PIN_25_GPIO25__FUNC_ROW1 (MTK_PIN_NO(25) | 1) +#define MT6320_PIN_25_GPIO25__FUNC_EINT19 (MTK_PIN_NO(25) | 2) +#define MT6320_PIN_25_GPIO25__FUNC_SDA0_3X (MTK_PIN_NO(25) | 3) + +#define MT6320_PIN_26_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT6320_PIN_26_GPIO26__FUNC_ROW2 (MTK_PIN_NO(26) | 1) +#define MT6320_PIN_26_GPIO26__FUNC_EINT20 (MTK_PIN_NO(26) | 2) +#define MT6320_PIN_26_GPIO26__FUNC_SCL1_3X (MTK_PIN_NO(26) | 3) + +#define MT6320_PIN_27_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT6320_PIN_27_GPIO27__FUNC_ROW3 (MTK_PIN_NO(27) | 1) +#define MT6320_PIN_27_GPIO27__FUNC_EINT21 (MTK_PIN_NO(27) | 2) +#define MT6320_PIN_27_GPIO27__FUNC_SDA1_3X (MTK_PIN_NO(27) | 3) + +#define MT6320_PIN_28_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT6320_PIN_28_GPIO28__FUNC_ROW4 (MTK_PIN_NO(28) | 1) +#define MT6320_PIN_28_GPIO28__FUNC_EINT22 (MTK_PIN_NO(28) | 2) +#define MT6320_PIN_28_GPIO28__FUNC_SCL2_3X (MTK_PIN_NO(28) | 3) + +#define MT6320_PIN_29_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT6320_PIN_29_GPIO29__FUNC_ROW5 (MTK_PIN_NO(29) | 1) +#define MT6320_PIN_29_GPIO29__FUNC_EINT23 (MTK_PIN_NO(29) | 2) +#define MT6320_PIN_29_GPIO29__FUNC_SDA2_3X (MTK_PIN_NO(29) | 3) + +#define MT6320_PIN_30_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT6320_PIN_30_GPIO30__FUNC_ROW6 (MTK_PIN_NO(30) | 1) +#define MT6320_PIN_30_GPIO30__FUNC_EINT24 (MTK_PIN_NO(30) | 2) +#define MT6320_PIN_30_GPIO30__FUNC_PWM3_3X (MTK_PIN_NO(30) | 3) +#define MT6320_PIN_30_GPIO30__FUNC_GPIO32K_2 (MTK_PIN_NO(30) | 4) +#define MT6320_PIN_30_GPIO30__FUNC_GPIO26M_2 (MTK_PIN_NO(30) | 5) + +#define MT6320_PIN_31_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT6320_PIN_31_GPIO31__FUNC_ROW7 (MTK_PIN_NO(31) | 1) +#define MT6320_PIN_31_GPIO31__FUNC_EINT3 (MTK_PIN_NO(31) | 2) +#define MT6320_PIN_31_GPIO31__FUNC_GPIO32K_3 (MTK_PIN_NO(31) | 4) +#define MT6320_PIN_31_GPIO31__FUNC_GPIO26M_3 (MTK_PIN_NO(31) | 5) + +#define MT6320_PIN_32_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT6320_PIN_32_GPIO32__FUNC_PWM1 (MTK_PIN_NO(32) | 1) +#define MT6320_PIN_32_GPIO32__FUNC_EINT4 (MTK_PIN_NO(32) | 2) +#define MT6320_PIN_32_GPIO32__FUNC_GPIO32K_4 (MTK_PIN_NO(32) | 4) +#define MT6320_PIN_32_GPIO32__FUNC_GPIO26M_4 (MTK_PIN_NO(32) | 5) + +#define MT6320_PIN_33_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT6320_PIN_33_GPIO33__FUNC_PWM2 (MTK_PIN_NO(33) | 1) +#define MT6320_PIN_33_GPIO33__FUNC_EINT5 (MTK_PIN_NO(33) | 2) +#define MT6320_PIN_33_GPIO33__FUNC_GPIO32K_5 (MTK_PIN_NO(33) | 4) +#define MT6320_PIN_33_GPIO33__FUNC_GPIO26M_5 (MTK_PIN_NO(33) | 5) + +#define MT6320_PIN_34_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT6320_PIN_34_GPIO34__FUNC_PWM3 (MTK_PIN_NO(34) | 1) +#define MT6320_PIN_34_GPIO34__FUNC_EINT6 (MTK_PIN_NO(34) | 2) +#define MT6320_PIN_34_GPIO34__FUNC_COL0 (MTK_PIN_NO(34) | 3) +#define MT6320_PIN_34_GPIO34__FUNC_GPIO32K_6 (MTK_PIN_NO(34) | 4) +#define MT6320_PIN_34_GPIO34__FUNC_GPIO26M_6 (MTK_PIN_NO(34) | 5) + +#define MT6320_PIN_35_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT6320_PIN_35_GPIO35__FUNC_SCL0 (MTK_PIN_NO(35) | 1) +#define MT6320_PIN_35_GPIO35__FUNC_EINT7 (MTK_PIN_NO(35) | 2) +#define MT6320_PIN_35_GPIO35__FUNC_PWM1_2X (MTK_PIN_NO(35) | 3) + +#define MT6320_PIN_36_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT6320_PIN_36_GPIO36__FUNC_SDA0 (MTK_PIN_NO(36) | 1) +#define MT6320_PIN_36_GPIO36__FUNC_EINT8 (MTK_PIN_NO(36) | 2) + +#define MT6320_PIN_37_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT6320_PIN_37_GPIO37__FUNC_SCL1 (MTK_PIN_NO(37) | 1) +#define MT6320_PIN_37_GPIO37__FUNC_EINT9 (MTK_PIN_NO(37) | 2) +#define MT6320_PIN_37_GPIO37__FUNC_PWM2_2X (MTK_PIN_NO(37) | 3) + +#define MT6320_PIN_38_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT6320_PIN_38_GPIO38__FUNC_SDA1 (MTK_PIN_NO(38) | 1) +#define MT6320_PIN_38_GPIO38__FUNC_EINT0 (MTK_PIN_NO(38) | 2) + +#define MT6320_PIN_39_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT6320_PIN_39_GPIO39__FUNC_SCL2 (MTK_PIN_NO(39) | 1) +#define MT6320_PIN_39_GPIO39__FUNC_EINT1 (MTK_PIN_NO(39) | 2) +#define MT6320_PIN_39_GPIO39__FUNC_PWM3_2X (MTK_PIN_NO(39) | 3) + +#define MT6320_PIN_40_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT6320_PIN_40_GPIO40__FUNC_SDA2 (MTK_PIN_NO(40) | 1) +#define MT6320_PIN_40_GPIO40__FUNC_EINT2 (MTK_PIN_NO(40) | 2) + +#define MT6320_PIN_41_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT6320_PIN_41_GPIO41__FUNC_SIM1_AP_SCLK (MTK_PIN_NO(41) | 1) + +#define MT6320_PIN_42_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT6320_PIN_42_GPIO42__FUNC_SIM1_AP_SRST (MTK_PIN_NO(42) | 1) + +#define MT6320_PIN_43_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT6320_PIN_43_GPIO43__FUNC_SIM2_AP_SCLK (MTK_PIN_NO(43) | 1) + +#define MT6320_PIN_44_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT6320_PIN_44_GPIO44__FUNC_SIM2_AP_SRST (MTK_PIN_NO(44) | 1) + +#define MT6320_PIN_45_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT6320_PIN_45_GPIO45__FUNC_SIMLS1_SCLK (MTK_PIN_NO(45) | 1) + +#define MT6320_PIN_46_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT6320_PIN_46_GPIO46__FUNC_SIMLS1_SRST (MTK_PIN_NO(46) | 1) + +#define MT6320_PIN_47_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT6320_PIN_47_GPIO47__FUNC_SIMLS2_SCLK (MTK_PIN_NO(47) | 1) +#define MT6320_PIN_47_GPIO47__FUNC_EINT10 (MTK_PIN_NO(47) | 5) + +#define MT6320_PIN_48_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT6320_PIN_48_GPIO48__FUNC_SIMLS2_SRST (MTK_PIN_NO(48) | 1) + +#endif /* __DTS_MT6320_PINFUNC_H */ diff --git a/include/dt-bindings/reset/mt6589-resets.h b/include/dt-bindings/reset/mt6589-resets.h index 54570146ba8bfd..f7960ac04203b5 100644 --- a/include/dt-bindings/reset/mt6589-resets.h +++ b/include/dt-bindings/reset/mt6589-resets.h @@ -34,6 +34,7 @@ #define MT6589_PERI_I2C6_SW_RST 28 #define MT6589_PERI_USB_SW_RST 29 #define MT6589_PERI_SPI0_SW_RST 33 +#define MT6589_PERI_PWRAP_BRIDGE_SW_RST 34 /* INFRA */ #define MT6589_INFRA_EMI_REG_RST 0 diff --git a/include/linux/mfd/mt6320/core.h b/include/linux/mfd/mt6320/core.h new file mode 100644 index 00000000000000..c75c21dd016158 --- /dev/null +++ b/include/linux/mfd/mt6320/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 Akari Tsuyukusa + */ + +#ifndef __MFD_MT6320_CORE_H__ +#define __MFD_MT6320_CORE_H__ + +enum mt6320_irq_numbers { + MT6320_IRQ_SPKL_AB = 0, + MT6320_IRQ_SPKR_AB, + MT6320_IRQ_SPKL, + MT6320_IRQ_SPKR, + MT6320_IRQ_BAT_L, + MT6320_IRQ_BAT_H, + MT6320_IRQ_FG_BAT_L, + MT6320_IRQ_FG_BAT_H, + MT6320_IRQ_WATCHDOG, + MT6320_IRQ_PWRKEY, + MT6320_IRQ_THR_L, + MT6320_IRQ_THR_H, + MT6320_IRQ_VBATON_UNDET, + MT6320_IRQ_BVALID_DET, + MT6320_IRQ_CHRDET, + MT6320_IRQ_OV, + MT6320_IRQ_LDO = 16, + MT6320_IRQ_HOMEKEY, + MT6320_IRQ_ACCDET, + MT6320_IRQ_AUDIO, + MT6320_IRQ_RTC, + MT6320_IRQ_VPROC = 24, + MT6320_IRQ_VSRAM, + MT6320_IRQ_VCORE, + MT6320_IRQ_VM, + MT6320_IRQ_VIO18, + MT6320_IRQ_VPA, + MT6320_IRQ_VRF18, + MT6320_IRQ_VRF18_2, + MT6320_IRQ_NR, +}; + +#endif /* __MFD_MT6320_CORE_H__ */ diff --git a/include/linux/mfd/mt6320/registers.h b/include/linux/mfd/mt6320/registers.h new file mode 100644 index 00000000000000..32b7a862b8a10d --- /dev/null +++ b/include/linux/mfd/mt6320/registers.h @@ -0,0 +1,505 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (C) 2014 BQ + * Copyright (C) 2026 Akari Tsuyukusa + * + * MT6320 Register Map based on bq Aquaris 5 kernel + */ + +#ifndef __MFD_MT6320_REGISTERS_H__ +#define ___MFD_MT6320_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6320_CHR_CON0 0x0000 +#define MT6320_CHR_CON1 0x0002 +#define MT6320_CHR_CON2 0x0004 +#define MT6320_CHR_CON3 0x0006 +#define MT6320_CHR_CON4 0x0008 +#define MT6320_CHR_CON5 0x000a +#define MT6320_CHR_CON6 0x000c +#define MT6320_CHR_CON7 0x000e +#define MT6320_CHR_CON8 0x0010 +#define MT6320_CHR_CON9 0x0012 +#define MT6320_CHR_CON10 0x0014 +#define MT6320_CHR_CON11 0x0016 +#define MT6320_CHR_CON12 0x0018 +#define MT6320_CHR_CON13 0x001a +#define MT6320_CHR_CON14 0x001c +#define MT6320_CHR_CON15 0x001e +#define MT6320_CHR_CON16 0x0020 +#define MT6320_CHR_CON17 0x0022 +#define MT6320_CHR_CON18 0x0024 +#define MT6320_CHR_CON19 0x0026 +#define MT6320_CHR_CON20 0x0028 +#define MT6320_CHR_CON21 0x002a +#define MT6320_CHR_CON22 0x002c +#define MT6320_CHR_CON23 0x002e +#define MT6320_CHR_CON24 0x0030 +#define MT6320_CHR_CON25 0x0032 +#define MT6320_CHR_CON26 0x0034 +#define MT6320_CHR_CON27 0x0036 +#define MT6320_CHR_CON28 0x0038 +#define MT6320_CHR_CON29 0x003a +#define MT6320_CID 0x0100 +#define MT6320_TOP_CKPDN 0x0102 +#define MT6320_TOP_CKPDN2 0x0108 +#define MT6320_TOP_GPIO_CKPDN 0x010e +#define MT6320_TOP_RST_CON 0x0114 +#define MT6320_WRP_CKPDN 0x011a +#define MT6320_WRP_RST_CON 0x0120 +#define MT6320_TOP_RST_MISC 0x0126 +#define MT6320_TOP_CKCON1 0x0128 +#define MT6320_TOP_CKCON2 0x012a +#define MT6320_TOP_CKTST1 0x012c +#define MT6320_TOP_CKTST2 0x012e +#define MT6320_OC_DEG_EN 0x0130 +#define MT6320_OC_CTL0 0x0132 +#define MT6320_OC_CTL1 0x0134 +#define MT6320_OC_CTL2 0x0136 +#define MT6320_INT_RSV 0x0138 +#define MT6320_TEST_CON0 0x013a +#define MT6320_TEST_CON1 0x013c +#define MT6320_STATUS0 0x013e +#define MT6320_STATUS1 0x0140 +#define MT6320_PGSTATUS 0x0142 +#define MT6320_CHRSTATUS 0x0144 +#define MT6320_OCSTATUS0 0x0146 +#define MT6320_OCSTATUS1 0x0148 +#define MT6320_OCSTATUS2 0x014a +#define MT6320_SIMLS_CON 0x014c +#define MT6320_TEST_OUT_L 0x014e +#define MT6320_TEST_OUT_H 0x0150 +#define MT6320_TDSEL_CON 0x0152 +#define MT6320_RDSEL_CON 0x0154 +#define MT6320_GPIO_SMT_CON0 0x0156 +#define MT6320_GPIO_SMT_CON1 0x0158 +#define MT6320_GPIO_SMT_CON2 0x015a +#define MT6320_GPIO_SMT_CON3 0x015c +#define MT6320_DRV_CON0 0x015e +#define MT6320_DRV_CON1 0x0160 +#define MT6320_DRV_CON2 0x0162 +#define MT6320_DRV_CON3 0x0164 +#define MT6320_DRV_CON4 0x0166 +#define MT6320_DRV_CON5 0x0168 +#define MT6320_DRV_CON6 0x016a +#define MT6320_DRV_CON7 0x016c +#define MT6320_DRV_CON8 0x016e +#define MT6320_DRV_CON9 0x0170 +#define MT6320_DRV_CON10 0x0172 +#define MT6320_DRV_CON11 0x0174 +#define MT6320_DRV_CON12 0x0176 +#define MT6320_INT_CON0 0x0178 +#define MT6320_INT_CON1 0x017e +#define MT6320_INT_STATUS0 0x0184 +#define MT6320_INT_STATUS1 0x0186 +#define MT6320_FQMTR_CON0 0x0188 +#define MT6320_FQMTR_CON1 0x018a +#define MT6320_FQMTR_CON2 0x018c +#define MT6320_EFUSE_CON0 0x018e +#define MT6320_EFUSE_CON1 0x0190 +#define MT6320_EFUSE_CON2 0x0192 +#define MT6320_EFUSE_CON3 0x0194 +#define MT6320_EFUSE_CON4 0x0196 +#define MT6320_EFUSE_CON5 0x0198 +#define MT6320_EFUSE_CON6 0x019a +#define MT6320_EFUSE_VAL_0_15 0x019c +#define MT6320_EFUSE_VAL_16_31 0x019e +#define MT6320_EFUSE_VAL_32_47 0x01a0 +#define MT6320_EFUSE_VAL_48_63 0x01a2 +#define MT6320_EFUSE_VAL_64_79 0x01a4 +#define MT6320_EFUSE_VAL_80_95 0x01a6 +#define MT6320_EFUSE_VAL_96_111 0x01a8 +#define MT6320_EFUSE_VAL_112_127 0x01aa +#define MT6320_EFUSE_VAL_128_143 0x01ac +#define MT6320_EFUSE_VAL_144_159 0x01ae +#define MT6320_EFUSE_VAL_160_175 0x01b0 +#define MT6320_EFUSE_VAL_176_191 0x01b2 +#define MT6320_EFUSE_DOUT_0_15 0x01b4 +#define MT6320_EFUSE_DOUT_16_31 0x01b6 +#define MT6320_EFUSE_DOUT_32_47 0x01b8 +#define MT6320_EFUSE_DOUT_48_63 0x01ba +#define MT6320_EFUSE_DOUT_64_79 0x01bc +#define MT6320_EFUSE_DOUT_80_95 0x01be +#define MT6320_EFUSE_DOUT_96_111 0x01c0 +#define MT6320_EFUSE_DOUT_112_127 0x01c2 +#define MT6320_EFUSE_DOUT_128_143 0x01c4 +#define MT6320_EFUSE_DOUT_144_159 0x01c6 +#define MT6320_EFUSE_DOUT_160_175 0x01c8 +#define MT6320_EFUSE_DOUT_176_191 0x01ca +#define MT6320_SPI_CON 0x01cc +#define MT6320_BUCK_CON0 0x0200 +#define MT6320_BUCK_CON1 0x0202 +#define MT6320_BUCK_CON2 0x0204 +#define MT6320_VPROC_CON0 0x0206 +#define MT6320_VPROC_CON1 0x0208 +#define MT6320_VPROC_CON2 0x020a +#define MT6320_VPROC_CON3 0x020c +#define MT6320_VPROC_CON4 0x020e +#define MT6320_VPROC_CON5 0x0210 +#define MT6320_VPROC_CON6 0x0212 +#define MT6320_VPROC_CON7 0x0214 +#define MT6320_VPROC_CON8 0x0216 +#define MT6320_VPROC_CON9 0x0218 +#define MT6320_VPROC_CON10 0x021a +#define MT6320_VPROC_CON11 0x021c +#define MT6320_VPROC_CON12 0x021e +#define MT6320_VPROC_CON13 0x0220 +#define MT6320_VPROC_CON14 0x0222 +#define MT6320_VPROC_CON15 0x0224 +#define MT6320_VPROC_CON16 0x0226 +#define MT6320_VPROC_CON17 0x0228 +#define MT6320_VPROC_CON18 0x022a +#define MT6320_VSRAM_CON0 0x022c +#define MT6320_VSRAM_CON1 0x022e +#define MT6320_VSRAM_CON2 0x0230 +#define MT6320_VSRAM_CON3 0x0232 +#define MT6320_VSRAM_CON4 0x0234 +#define MT6320_VSRAM_CON5 0x0236 +#define MT6320_VSRAM_CON6 0x0238 +#define MT6320_VSRAM_CON7 0x023a +#define MT6320_VSRAM_CON8 0x023c +#define MT6320_VSRAM_CON9 0x023e +#define MT6320_VSRAM_CON10 0x0240 +#define MT6320_VSRAM_CON11 0x0242 +#define MT6320_VSRAM_CON12 0x0244 +#define MT6320_VSRAM_CON13 0x0246 +#define MT6320_VSRAM_CON14 0x0248 +#define MT6320_VSRAM_CON15 0x024a +#define MT6320_VSRAM_CON16 0x024c +#define MT6320_VSRAM_CON17 0x024e +#define MT6320_VSRAM_CON18 0x0250 +#define MT6320_VSRAM_CON19 0x0252 +#define MT6320_VSRAM_CON20 0x0254 +#define MT6320_VSRAM_CON21 0x0256 +#define MT6320_VCORE_CON0 0x0258 +#define MT6320_VCORE_CON1 0x025a +#define MT6320_VCORE_CON2 0x025c +#define MT6320_VCORE_CON3 0x025e +#define MT6320_VCORE_CON4 0x0260 +#define MT6320_VCORE_CON5 0x0262 +#define MT6320_VCORE_CON6 0x0264 +#define MT6320_VCORE_CON7 0x0266 +#define MT6320_VCORE_CON8 0x0268 +#define MT6320_VCORE_CON9 0x026a +#define MT6320_VCORE_CON10 0x026c +#define MT6320_VCORE_CON11 0x026e +#define MT6320_VCORE_CON12 0x0270 +#define MT6320_VCORE_CON13 0x0272 +#define MT6320_VCORE_CON14 0x0274 +#define MT6320_VCORE_CON15 0x0276 +#define MT6320_VCORE_CON16 0x0278 +#define MT6320_VCORE_CON17 0x027a +#define MT6320_VCORE_CON18 0x027c +#define MT6320_VM_CON0 0x027e +#define MT6320_VM_CON1 0x0280 +#define MT6320_VM_CON2 0x0282 +#define MT6320_VM_CON3 0x0284 +#define MT6320_VM_CON4 0x0286 +#define MT6320_VM_CON5 0x0288 +#define MT6320_VM_CON6 0x028a +#define MT6320_VM_CON7 0x028c +#define MT6320_VM_CON8 0x028e +#define MT6320_VM_CON9 0x0290 +#define MT6320_VM_CON10 0x0292 +#define MT6320_VM_CON11 0x0294 +#define MT6320_VM_CON12 0x0296 +#define MT6320_VM_CON13 0x0298 +#define MT6320_VM_CON14 0x029a +#define MT6320_VM_CON15 0x029c +#define MT6320_VM_CON16 0x029e +#define MT6320_VM_CON17 0x02a0 +#define MT6320_VM_CON18 0x02a2 +#define MT6320_VIO18_CON0 0x0300 +#define MT6320_VIO18_CON1 0x0302 +#define MT6320_VIO18_CON2 0x0304 +#define MT6320_VIO18_CON3 0x0306 +#define MT6320_VIO18_CON4 0x0308 +#define MT6320_VIO18_CON5 0x030a +#define MT6320_VIO18_CON6 0x030c +#define MT6320_VIO18_CON7 0x030e +#define MT6320_VIO18_CON8 0x0310 +#define MT6320_VIO18_CON9 0x0312 +#define MT6320_VIO18_CON10 0x0314 +#define MT6320_VIO18_CON11 0x0316 +#define MT6320_VIO18_CON12 0x0318 +#define MT6320_VIO18_CON13 0x031a +#define MT6320_VIO18_CON14 0x031c +#define MT6320_VIO18_CON15 0x031e +#define MT6320_VIO18_CON16 0x0320 +#define MT6320_VIO18_CON17 0x0322 +#define MT6320_VIO18_CON18 0x0324 +#define MT6320_VPA_CON0 0x0326 +#define MT6320_VPA_CON1 0x0328 +#define MT6320_VPA_CON2 0x032a +#define MT6320_VPA_CON3 0x032c +#define MT6320_VPA_CON4 0x032e +#define MT6320_VPA_CON5 0x0330 +#define MT6320_VPA_CON6 0x0332 +#define MT6320_VPA_CON7 0x0334 +#define MT6320_VPA_CON8 0x0336 +#define MT6320_VPA_CON9 0x0338 +#define MT6320_VPA_CON10 0x033a +#define MT6320_VPA_CON11 0x033c +#define MT6320_VPA_CON12 0x033e +#define MT6320_VPA_CON13 0x0340 +#define MT6320_VPA_CON14 0x0342 +#define MT6320_VPA_CON15 0x0344 +#define MT6320_VPA_CON16 0x0346 +#define MT6320_VPA_CON17 0x0348 +#define MT6320_VPA_CON18 0x034a +#define MT6320_VPA_CON19 0x034c +#define MT6320_VPA_CON20 0x034e +#define MT6320_VRF18_CON0 0x0350 +#define MT6320_VRF18_CON1 0x0352 +#define MT6320_VRF18_CON2 0x0354 +#define MT6320_VRF18_CON3 0x0356 +#define MT6320_VRF18_CON4 0x0358 +#define MT6320_VRF18_CON5 0x035a +#define MT6320_VRF18_CON6 0x035c +#define MT6320_VRF18_CON7 0x035e +#define MT6320_VRF18_CON8 0x0360 +#define MT6320_VRF18_CON9 0x0362 +#define MT6320_VRF18_CON10 0x0364 +#define MT6320_VRF18_CON11 0x0366 +#define MT6320_VRF18_CON12 0x0368 +#define MT6320_VRF18_CON13 0x036a +#define MT6320_VRF18_CON14 0x036c +#define MT6320_VRF18_CON15 0x036e +#define MT6320_VRF18_CON16 0x0370 +#define MT6320_VRF18_CON17 0x0372 +#define MT6320_VRF18_CON18 0x0374 +#define MT6320_VRF18_CON19 0x0376 +#define MT6320_VRF18_CON20 0x0378 +#define MT6320_VRF18_2_CON0 0x037a +#define MT6320_VRF18_2_CON1 0x037c +#define MT6320_VRF18_2_CON2 0x037e +#define MT6320_VRF18_2_CON3 0x0380 +#define MT6320_VRF18_2_CON4 0x0382 +#define MT6320_VRF18_2_CON5 0x0384 +#define MT6320_VRF18_2_CON6 0x0386 +#define MT6320_VRF18_2_CON7 0x0388 +#define MT6320_VRF18_2_CON8 0x038a +#define MT6320_VRF18_2_CON9 0x038c +#define MT6320_VRF18_2_CON10 0x038e +#define MT6320_VRF18_2_CON11 0x0390 +#define MT6320_VRF18_2_CON12 0x0392 +#define MT6320_VRF18_2_CON13 0x0394 +#define MT6320_VRF18_2_CON14 0x0396 +#define MT6320_VRF18_2_CON15 0x0398 +#define MT6320_VRF18_2_CON16 0x039a +#define MT6320_VRF18_2_CON17 0x039c +#define MT6320_VRF18_2_CON18 0x039e +#define MT6320_BUCK_K_CON0 0x03a0 +#define MT6320_BUCK_K_CON1 0x03a2 +#define MT6320_ANALDO_CON0 0x0400 +#define MT6320_ANALDO_CON1 0x0402 +#define MT6320_ANALDO_CON2 0x0404 +#define MT6320_ANALDO_CON3 0x0406 +#define MT6320_ANALDO_CON4 0x0408 +#define MT6320_ANALDO_CON5 0x040a +#define MT6320_ANALDO_CON6 0x040c +#define MT6320_ANALDO_CON7 0x040e +#define MT6320_ANALDO_CON8 0x0410 +#define MT6320_ANALDO_CON9 0x0412 +#define MT6320_ANALDO_CON10 0x0414 +#define MT6320_ANALDO_CON11 0x0416 +#define MT6320_ANALDO_CON12 0x0418 +#define MT6320_ANALDO_CON13 0x041a +#define MT6320_ANALDO_CON14 0x041c +#define MT6320_ANALDO_CON15 0x041e +#define MT6320_DIGLDO_CON0 0x0420 +#define MT6320_DIGLDO_CON2 0x0422 +#define MT6320_DIGLDO_CON3 0x0424 +#define MT6320_DIGLDO_CON5 0x0426 +#define MT6320_DIGLDO_CON6 0x0428 +#define MT6320_DIGLDO_CON7 0x042a +#define MT6320_DIGLDO_CON8 0x042c +#define MT6320_DIGLDO_CON9 0x042e +#define MT6320_DIGLDO_CON10 0x0430 +#define MT6320_DIGLDO_CON11 0x0432 +#define MT6320_DIGLDO_CON12 0x0434 +#define MT6320_DIGLDO_CON13 0x0436 +#define MT6320_DIGLDO_CON14 0x0438 +#define MT6320_DIGLDO_CON15 0x043a +#define MT6320_DIGLDO_CON16 0x043c +#define MT6320_DIGLDO_CON17 0x043e +#define MT6320_DIGLDO_CON18 0x0440 +#define MT6320_DIGLDO_CON19 0x0442 +#define MT6320_DIGLDO_CON20 0x0444 +#define MT6320_DIGLDO_CON21 0x0446 +#define MT6320_DIGLDO_CON23 0x0448 +#define MT6320_DIGLDO_CON24 0x044a +#define MT6320_DIGLDO_CON26 0x044c +#define MT6320_DIGLDO_CON27 0x044e +#define MT6320_DIGLDO_CON28 0x0450 +#define MT6320_DIGLDO_CON29 0x0452 +#define MT6320_DIGLDO_CON30 0x0454 +#define MT6320_DIGLDO_CON31 0x0456 +#define MT6320_DIGLDO_CON32 0x0458 +#define MT6320_DIGLDO_CON33 0x045a +#define MT6320_DIGLDO_CON34 0x045c +#define MT6320_DIGLDO_CON35 0x045e +#define MT6320_DIGLDO_CON36 0x0460 +#define MT6320_DIGLDO_CON37 0x0462 +#define MT6320_DIGLDO_CON38 0x0464 +#define MT6320_DIGLDO_CON39 0x0466 +#define MT6320_DIGLDO_CON40 0x0468 +#define MT6320_DIGLDO_CON41 0x046a +#define MT6320_DIGLDO_CON42 0x046c +#define MT6320_DIGLDO_CON43 0x046e +#define MT6320_DIGLDO_CON44 0x0470 +#define MT6320_STRUP_CON0 0x0500 +#define MT6320_STRUP_CON2 0x0502 +#define MT6320_STRUP_CON3 0x0504 +#define MT6320_STRUP_CON4 0x0506 +#define MT6320_STRUP_CON5 0x0508 +#define MT6320_STRUP_CON6 0x050a +#define MT6320_STRUP_CON7 0x050c +#define MT6320_STRUP_CON8 0x050e +#define MT6320_STRUP_CON9 0x0510 +#define MT6320_AUXADC_ADC0 0x0512 +#define MT6320_AUXADC_ADC1 0x0514 +#define MT6320_AUXADC_ADC2 0x0516 +#define MT6320_AUXADC_ADC3 0x0518 +#define MT6320_AUXADC_ADC4 0x051a +#define MT6320_AUXADC_ADC5 0x051c +#define MT6320_AUXADC_ADC6 0x051e +#define MT6320_AUXADC_ADC7 0x0520 +#define MT6320_AUXADC_ADC8 0x0522 +#define MT6320_AUXADC_ADC9 0x0524 +#define MT6320_AUXADC_ADC10 0x0526 +#define MT6320_AUXADC_ADC11 0x0528 +#define MT6320_AUXADC_ADC12 0x052a +#define MT6320_AUXADC_ADC13 0x052c +#define MT6320_AUXADC_ADC14 0x052e +#define MT6320_AUXADC_ADC15 0x0530 +#define MT6320_AUXADC_ADC16 0x0532 +#define MT6320_AUXADC_ADC17 0x0534 +#define MT6320_AUXADC_ADC18 0x0536 +#define MT6320_AUXADC_ADC19 0x0538 +#define MT6320_AUXADC_ADC20 0x053a +#define MT6320_AUXADC_ADC21 0x053c +#define MT6320_AUXADC_ADC22 0x053e +#define MT6320_AUXADC_CON0 0x0540 +#define MT6320_AUXADC_CON1 0x0542 +#define MT6320_AUXADC_CON2 0x0544 +#define MT6320_AUXADC_CON3 0x0546 +#define MT6320_AUXADC_CON4 0x0548 +#define MT6320_AUXADC_CON5 0x054a +#define MT6320_AUXADC_CON6 0x054c +#define MT6320_AUXADC_CON7 0x054e +#define MT6320_AUXADC_CON8 0x0550 +#define MT6320_AUXADC_CON9 0x0552 +#define MT6320_AUXADC_CON10 0x0554 +#define MT6320_AUXADC_CON11 0x0556 +#define MT6320_AUXADC_CON12 0x0558 +#define MT6320_AUXADC_CON13 0x055a +#define MT6320_AUXADC_CON14 0x055c +#define MT6320_FLASH_CON0 0x055e +#define MT6320_FLASH_CON1 0x0560 +#define MT6320_FLASH_CON2 0x0562 +#define MT6320_KPLED_CON0 0x0564 +#define MT6320_KPLED_CON1 0x0566 +#define MT6320_KPLED_CON2 0x0568 +#define MT6320_ISINKS_CON0 0x056a +#define MT6320_ISINKS_CON1 0x056c +#define MT6320_ISINKS_CON2 0x056e +#define MT6320_ISINKS_CON3 0x0570 +#define MT6320_ISINKS_CON4 0x0572 +#define MT6320_ISINKS_CON5 0x0574 +#define MT6320_ISINKS_CON6 0x0576 +#define MT6320_ISINKS_CON7 0x0578 +#define MT6320_ISINKS_CON8 0x057a +#define MT6320_ISINKS_CON9 0x057c +#define MT6320_ISINKS_CON10 0x057e +#define MT6320_ISINKS_CON11 0x0580 +#define MT6320_ACCDET_CON0 0x0582 +#define MT6320_ACCDET_CON1 0x0584 +#define MT6320_ACCDET_CON2 0x0586 +#define MT6320_ACCDET_CON3 0x0588 +#define MT6320_ACCDET_CON4 0x058a +#define MT6320_ACCDET_CON5 0x058c +#define MT6320_ACCDET_CON6 0x058e +#define MT6320_ACCDET_CON7 0x0590 +#define MT6320_ACCDET_CON8 0x0592 +#define MT6320_ACCDET_CON9 0x0594 +#define MT6320_ACCDET_CON10 0x0596 +#define MT6320_ACCDET_CON11 0x0598 +#define MT6320_ACCDET_CON12 0x059a +#define MT6320_ACCDET_CON13 0x059c +#define MT6320_ACCDET_CON14 0x059e +#define MT6320_ACCDET_CON15 0x05a0 +#define MT6320_ACCDET_CON16 0x05a2 +#define MT6320_SPK_CON0 0x0600 +#define MT6320_SPK_CON1 0x0602 +#define MT6320_SPK_CON2 0x0604 +#define MT6320_SPK_CON3 0x0606 +#define MT6320_SPK_CON4 0x0608 +#define MT6320_SPK_CON5 0x060a +#define MT6320_SPK_CON6 0x060c +#define MT6320_SPK_CON7 0x060e +#define MT6320_SPK_CON8 0x0610 +#define MT6320_SPK_CON9 0x0612 +#define MT6320_SPK_CON10 0x0614 +#define MT6320_SPK_CON11 0x0616 +#define MT6320_FGADC_CON0 0x0618 +#define MT6320_FGADC_CON1 0x061a +#define MT6320_FGADC_CON2 0x061c +#define MT6320_FGADC_CON3 0x061e +#define MT6320_FGADC_CON4 0x0620 +#define MT6320_FGADC_CON5 0x0622 +#define MT6320_FGADC_CON6 0x0624 +#define MT6320_FGADC_CON7 0x0626 +#define MT6320_FGADC_CON8 0x0628 +#define MT6320_FGADC_CON9 0x062a +#define MT6320_FGADC_CON10 0x062c +#define MT6320_FGADC_CON11 0x062e +#define MT6320_FGADC_CON12 0x0630 +#define MT6320_FGADC_CON13 0x0632 +#define MT6320_FGADC_CON14 0x0634 +#define MT6320_FGADC_CON15 0x0636 +#define MT6320_FGADC_CON16 0x0638 +#define MT6320_FGADC_CON17 0x063a +#define MT6320_FGADC_CON18 0x063c +#define MT6320_FGADC_CON19 0x063e +#define MT6320_RTC_MIX_CON0 0x0640 +#define MT6320_RTC_MIX_CON1 0x0642 +#define MT6320_AUDDAC_CON0 0x0700 +#define MT6320_AUDBUF_CFG0 0x0702 +#define MT6320_AUDBUF_CFG1 0x0704 +#define MT6320_AUDBUF_CFG2 0x0706 +#define MT6320_AUDBUF_CFG3 0x0708 +#define MT6320_AUDBUF_CFG4 0x070a +#define MT6320_IBIASDIST_CFG0 0x070c +#define MT6320_AUDACCDEPOP_CFG0 0x070e +#define MT6320_AUD_IV_CFG0 0x0710 +#define MT6320_AUDCLKGEN_CFG0 0x0712 +#define MT6320_AUDLDO_CFG0 0x0714 +#define MT6320_AUDLDO_CFG1 0x0716 +#define MT6320_AUDNVREGGLB_CFG0 0x0718 +#define MT6320_AUD_NCP0 0x071a +#define MT6320_AUDPREAMP_CON0 0x071c +#define MT6320_AUDADC_CON0 0x071e +#define MT6320_AUDADC_CON1 0x0720 +#define MT6320_AUDADC_CON2 0x0722 +#define MT6320_AUDADC_CON3 0x0724 +#define MT6320_AUDADC_CON4 0x0726 +#define MT6320_AUDADC_CON5 0x0728 +#define MT6320_AUDADC_CON6 0x072a +#define MT6320_AUDDIGMI_CON0 0x072c +#define MT6320_AUDLSBUF_CON0 0x072e +#define MT6320_AUDLSBUF_CON1 0x0730 +#define MT6320_AUDENCSPARE_CON0 0x0732 +#define MT6320_AUDENCCLKSQ_CON0 0x0734 +#define MT6320_AUDPREAMPGAIN_CON0 0x0736 +#define MT6320_ZCD_CON0 0x0738 +#define MT6320_ZCD_CON1 0x073a +#define MT6320_ZCD_CON2 0x073c +#define MT6320_ZCD_CON3 0x073e +#define MT6320_ZCD_CON4 0x0740 +#define MT6320_ZCD_CON5 0x0742 +#define MT6320_NCP_CLKDIV_CON0 0x0744 +#define MT6320_NCP_CLKDIV_CON1 0x0746 + +#endif /* __MFD_MT6320_REGISTERS_H__ */ diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h index b774c3a4bb62e5..dadffd3669591d 100644 --- a/include/linux/mfd/mt6397/core.h +++ b/include/linux/mfd/mt6397/core.h @@ -11,10 +11,11 @@ #include enum chip_id { + MT6320_CHIP_ID = 0x20, MT6323_CHIP_ID = 0x23, - MT6328_CHIP_ID = 0x30, - MT6331_CHIP_ID = 0x20, - MT6332_CHIP_ID = 0x20, + MT6328_CHIP_ID = 0x28, + MT6331_CHIP_ID = 0x31, + MT6332_CHIP_ID = 0x32, MT6357_CHIP_ID = 0x57, MT6358_CHIP_ID = 0x58, MT6359_CHIP_ID = 0x59, diff --git a/include/linux/regulator/mt6320-regulator.h b/include/linux/regulator/mt6320-regulator.h new file mode 100644 index 00000000000000..52214dc080545c --- /dev/null +++ b/include/linux/regulator/mt6320-regulator.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 Akari Tsuyukusa + * + * based on MT6589 v3.4.67 downstream kernel + * Copyright (c) 2014 BQ + * Copyright (c) 2014 MediaTek Inc. + */ + +#ifndef __LINUX_REGULATOR_MT6320_H +#define __LINUX_REGULATOR_MT6320_H + +enum { + /* Buck */ + MT6320_ID_VPROC, + MT6320_ID_VSRAM, + MT6320_ID_VCORE, + MT6320_ID_VM, + MT6320_ID_VIO18, + MT6320_ID_VPA, + MT6320_ID_VRF18, + MT6320_ID_VRF18_2, + + /* Digital LDO */ + MT6320_ID_VIO28, + MT6320_ID_VUSB, + MT6320_ID_VMC1, + MT6320_ID_VMCH1, + MT6320_ID_VEMC_3V3, + MT6320_ID_VEMC_1V8, + MT6320_ID_VGP1, + MT6320_ID_VGP2, + MT6320_ID_VGP3, + MT6320_ID_VGP4, + MT6320_ID_VGP5, + MT6320_ID_VGP6, + MT6320_ID_VSIM1, + MT6320_ID_VSIM2, + MT6320_ID_VIBR, + MT6320_ID_VRTC, + MT6320_ID_VAST, + + /* Analog LDO */ + MT6320_ID_VRF28, + MT6320_ID_VRF28_2, + MT6320_ID_VTCXO, + MT6320_ID_VTCXO_2, + MT6320_ID_VA, + MT6320_ID_VA28, + MT6320_ID_VCAMA, + + MT6320_ID_RG_MAX, +}; + +#define MT6320_MAX_REGULATOR MT6320_ID_RG_MAX + +#endif /* __LINUX_REGULATOR_MT6320_H */ From 74d86e34eb61b2e66ce8d5f0f24abde31599a13f Mon Sep 17 00:00:00 2001 From: Custom Firmware Date: Thu, 21 May 2026 23:54:21 +0300 Subject: [PATCH 76/98] i2c: mediatek: support dual APDMA channel layout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some MediaTek SoCs split their I2C APDMA into two physically separate channels per bus, each with its own register block using TX-side offsets regardless of direction. mt6572 is one such SoC. The existing driver assumes a single unified APDMA channel where RX and TX live at RX_*/TX_* offsets within the same block, which is correct for the SoCs already in mainline but cannot reach the RX channel on dual-channel SoCs. Add a per-SoC compatible flag dma_separate_rx plus a second ioremap pointer pdmabase_rx for the RX channel. When the flag is clear (every currently supported SoC), pdmabase_rx aliases pdmabase and the RX-direction offsets collapse back to OFFSET_RX_MEM_ADDR / OFFSET_RX_LEN / OFFSET_RX_4G_MODE — byte-for-byte identical writes to the pre-patch code path. No behaviour change for unified-DMA SoCs. When the flag is set, the driver ioremaps the third reg entry as the RX channel and routes RX writes through that block using OFFSET_TX_* offsets (the RX channel uses the same TX-style register layout in its own block). DMA_START_EN is issued on the RX channel for read transfers; the TX channel still starts WR/WRRD paths as before. No SoC opts into this layout in this commit. Co-developed-by: rva3 [rva3: fix DMA enable for WRRD] Signed-off-by: rva3 Signed-off-by: Custom Firmware --- drivers/i2c/busses/i2c-mt65xx.c | 52 ++++++++++++++++++++++++++------- 1 file changed, 42 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index ab456c3717db18..fbb9bbf38f57e2 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -267,6 +267,7 @@ struct mtk_i2c_compatible { unsigned char dma_sync: 1; unsigned char ltiming_adjust: 1; unsigned char apdma_sync: 1; + unsigned char dma_separate_rx: 1; unsigned char max_dma_support; }; @@ -291,7 +292,10 @@ struct mtk_i2c { /* set in i2c probe */ void __iomem *base; /* i2c base addr */ - void __iomem *pdmabase; /* dma base address*/ + void __iomem *pdmabase; /* dma base address (TX channel) */ + void __iomem *pdmabase_rx; /* RX dma base; aliases pdmabase + * when dma_separate_rx is 0 + */ struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ bool have_pmic; /* can use i2c pins from PMIC */ bool use_push_pull; /* IO config push-pull mode */ @@ -1008,6 +1012,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, u8 *dma_wr_buf = NULL; dma_addr_t rpaddr = 0; dma_addr_t wpaddr = 0; + void __iomem *rxbase = i2c->pdmabase_rx; + unsigned int rx_mem_off = i2c->dev_comp->dma_separate_rx ? + OFFSET_TX_MEM_ADDR : OFFSET_RX_MEM_ADDR; + unsigned int rx_len_off = i2c->dev_comp->dma_separate_rx ? + OFFSET_TX_LEN : OFFSET_RX_LEN; + unsigned int rx_4g_off = i2c->dev_comp->dma_separate_rx ? + OFFSET_TX_4G_MODE : OFFSET_RX_4G_MODE; int ret; i2c->irq_stat = 0; @@ -1086,8 +1097,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, /* Prepare buffer data to start transfer */ if (i2c->op == I2C_MASTER_RD) { - writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); - writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON); + writel(I2C_DMA_INT_FLAG_NONE, rxbase + OFFSET_INT_FLAG); + writel(I2C_DMA_CON_RX | dma_sync, rxbase + OFFSET_CON); dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1); if (!dma_rd_buf) @@ -1103,11 +1114,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, if (i2c->dev_comp->max_dma_support > 32) { reg_4g_mode = upper_32_bits(rpaddr); - writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); + writel(reg_4g_mode, rxbase + rx_4g_off); } - writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); - writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN); + writel((u32)rpaddr, rxbase + rx_mem_off); + writel(msgs->len, rxbase + rx_len_off); } else if (i2c->op == I2C_MASTER_WR) { writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG); writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON); @@ -1175,16 +1186,28 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs, writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE); reg_4g_mode = upper_32_bits(rpaddr); - writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE); + writel(reg_4g_mode, rxbase + rx_4g_off); } writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR); - writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR); + writel((u32)rpaddr, rxbase + rx_mem_off); writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN); - writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN); + writel((msgs + 1)->len, rxbase + rx_len_off); + + if (i2c->dev_comp->dma_separate_rx) + writel(I2C_DMA_CON_RX, rxbase + OFFSET_CON); } - writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); + if (i2c->op == I2C_MASTER_RD) { + writel(I2C_DMA_START_EN, rxbase + OFFSET_EN); + } else if (i2c->op == I2C_MASTER_WR) { + writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); + } else { + /* I2C_MASTER_WRRD */ + writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN); + if (i2c->dev_comp->dma_separate_rx) + writel(I2C_DMA_START_EN, rxbase + OFFSET_EN); + } if (!i2c->auto_restart) { start_reg = I2C_TRANSAC_START; @@ -1395,6 +1418,15 @@ static int mtk_i2c_probe(struct platform_device *pdev) init_completion(&i2c->msg_complete); i2c->dev_comp = of_device_get_match_data(&pdev->dev); + + if (i2c->dev_comp->dma_separate_rx) { + i2c->pdmabase_rx = devm_platform_ioremap_resource(pdev, 2); + if (IS_ERR(i2c->pdmabase_rx)) + return PTR_ERR(i2c->pdmabase_rx); + } else { + i2c->pdmabase_rx = i2c->pdmabase; + } + i2c->adap.dev.of_node = pdev->dev.of_node; i2c->dev = &pdev->dev; i2c->adap.dev.parent = &pdev->dev; From 62f7c592726df8f6594fc07d50e6d82a1e89928f Mon Sep 17 00:00:00 2001 From: rva3 Date: Sat, 23 May 2026 18:07:12 +0300 Subject: [PATCH 77/98] i2c: mediatek: fix WRRD for SoCs without auto_restart option MediaTek mt65xx family SoCs have no auto restart, however, they still support the WRRD mode in the hardware. Because auto_restart is set to 0, the WRRD mode will be never enabled, leading to read errors using i2cget with explicit register. Fix this by removing auto_restart check from the WRRD enable path. Signed-off-by: rva3 --- drivers/i2c/busses/i2c-mt65xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c index fbb9bbf38f57e2..3baa16a6dfcbef 100644 --- a/drivers/i2c/busses/i2c-mt65xx.c +++ b/drivers/i2c/busses/i2c-mt65xx.c @@ -1275,7 +1275,7 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap, i2c->auto_restart = i2c->dev_comp->auto_restart; /* checking if we can skip restart and optimize using WRRD mode */ - if (i2c->auto_restart && num == 2) { + if (num == 2) { if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) && msgs[0].addr == msgs[1].addr) { i2c->auto_restart = 0; From 0804433541c858748470a8be6a51410b1acacde6 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sun, 21 Jun 2026 22:55:35 +0900 Subject: [PATCH 78/98] mfd: mt6320: fix include guard Signed-off-by: Akari Tsuyukusa --- include/linux/mfd/mt6320/registers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mfd/mt6320/registers.h b/include/linux/mfd/mt6320/registers.h index 32b7a862b8a10d..88e7dacad1178b 100644 --- a/include/linux/mfd/mt6320/registers.h +++ b/include/linux/mfd/mt6320/registers.h @@ -8,7 +8,7 @@ */ #ifndef __MFD_MT6320_REGISTERS_H__ -#define ___MFD_MT6320_REGISTERS_H__ +#define __MFD_MT6320_REGISTERS_H__ /* PMIC Registers */ #define MT6320_CHR_CON0 0x0000 From 71995d803e0242d187ea60708594ad13334053c4 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 22 Jun 2026 00:49:09 +0900 Subject: [PATCH 79/98] add scpsys driver (#18) * pmdomain: mediatek: scpsys: init mt6589 support * arm: dts: mediatek: mt6589: fix scpsys address * Revert "arm: dts: mediatek: mt6589: fix scpsys address" This reverts commit f295374a0f69d4f9512da72f48f452c641033961. * Revert "pmdomain: mediatek: scpsys: init mt6589 support" This reverts commit 4db11bb51fc79c5a2d83d0dc735f310a99855e2a. * dt-bindings: power: mediatek: add mt6589 scpsys Signed-off-by: Akari Tsuyukusa * arm: defconfig: lenovo-blade: add CONFIG_MTK_SCPSYS_PM_DOMAINS Signed-off-by: Akari Tsuyukusa * dt-bindings: power: add mt6589 header Signed-off-by: Akari Tsuyukusa * dt-bindings: power: mt6589 fix Signed-off-by: Akari Tsuyukusa * pmdomain: mediatek: Add MT6589 support (wip?) because bp_cfg are not configured Signed-off-by: Akari Tsuyukusa * arm: dts: mediatek: mt6589: add scpsys Signed-off-by: Akari Tsuyukusa * pmdomain: mediatek: remove MTK_SCPD_NO_SRAM Signed-off-by: Akari Tsuyukusa * pmdomain: mediatek: mt6589: fill topaxi protection Signed-off-by: Akari Tsuyukusa * pmdomain: mediatek: mt6589: cleanup Signed-off-by: Akari Tsuyukusa --------- Signed-off-by: Akari Tsuyukusa --- .../power/mediatek,power-controller.yaml | 1 + arch/arm/boot/dts/mediatek/mt6589.dtsi | 68 ++++++++++ arch/arm/configs/lenovo-blade_defconfig | 3 + drivers/pmdomain/mediatek/mt6589-pm-domains.h | 117 ++++++++++++++++++ drivers/pmdomain/mediatek/mtk-pm-domains.c | 5 + drivers/pmdomain/mediatek/mtk-pm-domains.h | 2 + include/dt-bindings/power/mt6589-power.h | 16 +++ 7 files changed, 212 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt6589-pm-domains.h create mode 100644 include/dt-bindings/power/mt6589-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 9c7cc632abee25..b73d05000acc05 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: + - mediatek,mt6589-power-controller - mediatek,mt6735-power-controller - mediatek,mt6795-power-controller - mediatek,mt6893-power-controller diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 9fe45d8a869743..ac1c1da24eff39 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -114,6 +115,73 @@ #reset-cells = <1>; }; + scpsys: syscon@10006000 { + compatible = "syscon", "simple-mfd"; + reg = <0x10006000 0x1000>; + #power-domain-cells = <1>; + + spm: power-controller { + compatible = "mediatek,mt6589-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT6589_POWER_DOMAIN_MD1 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_MD2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_DPY { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_DIS { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_DISP>; + clock-names = "disp"; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_MFG { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_MFG>, + <&topckgen CLK_TOP_MUX_SMI_MFG_AS>; + clock-names = "mfg", "mfg_as"; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_ISP { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_IFR { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_VEN { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_VENC>; + clock-names = "venc"; + #power-domain-cells = <0>; + }; + + power-domain@MT6589_POWER_DOMAIN_VDE { + reg = ; + clocks = <&topckgen CLK_TOP_MUX_VDEC>; + clock-names = "vdec"; + #power-domain-cells = <0>; + }; + }; + }; + mfgsys: syscon@10206000 { compatible = "mediatek,mt6589-mfgsys", "syscon"; reg = <0x10206000 0x1000>; diff --git a/arch/arm/configs/lenovo-blade_defconfig b/arch/arm/configs/lenovo-blade_defconfig index 77d7bbd7b0191f..f0389f5a9aa32c 100644 --- a/arch/arm/configs/lenovo-blade_defconfig +++ b/arch/arm/configs/lenovo-blade_defconfig @@ -123,6 +123,9 @@ CONFIG_POWER_RESET_MT6323=y ## Reset #CONFIG_RESET_CONTROLLER +## Power Management +CONFIG_MTK_SCPSYS_PM_DOMAINS=y + ## Input CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_MTK_PMIC=y diff --git a/drivers/pmdomain/mediatek/mt6589-pm-domains.h b/drivers/pmdomain/mediatek/mt6589-pm-domains.h new file mode 100644 index 00000000000000..53553f1932e596 --- /dev/null +++ b/drivers/pmdomain/mediatek/mt6589-pm-domains.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6589_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT6589_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT6589 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { + [MT6589_POWER_DOMAIN_MD1] = { + .name = "md1", + .sta_mask = PWR_STATUS_MD1, + .ctl_offs = SPM_MD1_PWR_CON, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = 0, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(0x5300), + }, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_MD2] = { + .name = "md2", + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = SPM_CONN_PWR_CON, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = 0, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(0xac00), + }, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_DPY] = { + .name = "dpy", + .sta_mask = PWR_STATUS_DDRPHY, + .ctl_offs = 0x0240, + .caps = MTK_SCPD_ALWAYS_ON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_DIS] = { + .name = "dis", + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_MFG] = { + .name = "mfg", + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = BIT(8), + .sram_pdn_ack_bits = BIT(12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .bp_cfg = { + BUS_PROT_INFRA_UPDATE_TOPAXI(0x0020), + }, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_ISP] = { + .name = "isp", + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_IFR] = { + .name = "ifr", + .sta_mask = PWR_STATUS_INFRASYS, + .ctl_offs = 0x0234, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .caps = MTK_SCPD_ALWAYS_ON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_VEN] = { + .name = "ven", + .sta_mask = BIT(7), + .ctl_offs = SPM_VEN_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, + [MT6589_POWER_DOMAIN_VDE] = { + .name = "vde", + .sta_mask = BIT(8), + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, + }, +}; + +static const struct scpsys_soc_data mt6589_scpsys_data = { + .domains_data = scpsys_domain_data_mt6589, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6589), +}; + +#endif /* __SOC_MEDIATEK_MT6589_PM_DOMAINS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.c b/drivers/pmdomain/mediatek/mtk-pm-domains.c index a58ed7e2d9a479..39eef0da1a46f6 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.c +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.c @@ -16,6 +16,7 @@ #include #include +#include "mt6589-pm-domains.h" #include "mt6735-pm-domains.h" #include "mt6795-pm-domains.h" #include "mt6893-pm-domains.h" @@ -616,6 +617,10 @@ static void scpsys_domain_cleanup(struct scpsys *scpsys) } static const struct of_device_id scpsys_of_match[] = { + { + .compatible = "mediatek,mt6589-power-controller", + .data = &mt6589_scpsys_data, + }, { .compatible = "mediatek,mt6735-power-controller", .data = &mt6735_scpsys_data, diff --git a/drivers/pmdomain/mediatek/mtk-pm-domains.h b/drivers/pmdomain/mediatek/mtk-pm-domains.h index 7085fa2976e98b..eed246209ec283 100644 --- a/drivers/pmdomain/mediatek/mtk-pm-domains.h +++ b/drivers/pmdomain/mediatek/mtk-pm-domains.h @@ -33,9 +33,11 @@ #define PWR_STATUS_MD1 BIT(0) #define PWR_STATUS_CONN BIT(1) +#define PWR_STATUS_DDRPHY BIT(2) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) #define PWR_STATUS_ISP BIT(5) +#define PWR_STATUS_INFRASYS BIT(6) #define PWR_STATUS_VDEC BIT(7) #define PWR_STATUS_VENC_LT BIT(20) #define PWR_STATUS_VENC BIT(21) diff --git a/include/dt-bindings/power/mt6589-power.h b/include/dt-bindings/power/mt6589-power.h new file mode 100644 index 00000000000000..14d2c941015543 --- /dev/null +++ b/include/dt-bindings/power/mt6589-power.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_MT6589_POWER_H +#define _DT_BINDINGS_POWER_MT6589_POWER_H + +#define MT6589_POWER_DOMAIN_MD1 0 +#define MT6589_POWER_DOMAIN_MD2 1 +#define MT6589_POWER_DOMAIN_DPY 2 +#define MT6589_POWER_DOMAIN_DIS 3 +#define MT6589_POWER_DOMAIN_MFG 4 +#define MT6589_POWER_DOMAIN_ISP 5 +#define MT6589_POWER_DOMAIN_IFR 6 +#define MT6589_POWER_DOMAIN_VEN 7 +#define MT6589_POWER_DOMAIN_VDE 8 + +#endif /* _DT_BINDINGS_POWER_MT6589_POWER_H */ From 416038fa0ded80e00aeb856c2da8d920d4e618e8 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 22 Jun 2026 10:32:46 +0900 Subject: [PATCH 80/98] arm: dts: mediatek: mt6589: add infracfg to scpsys --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index ac1c1da24eff39..3354e252e0f8ba 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -129,11 +129,13 @@ power-domain@MT6589_POWER_DOMAIN_MD1 { reg = ; #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; }; power-domain@MT6589_POWER_DOMAIN_MD2 { reg = ; #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; }; power-domain@MT6589_POWER_DOMAIN_DPY { @@ -154,6 +156,7 @@ <&topckgen CLK_TOP_MUX_SMI_MFG_AS>; clock-names = "mfg", "mfg_as"; #power-domain-cells = <0>; + mediatek,infracfg = <&infracfg>; }; power-domain@MT6589_POWER_DOMAIN_ISP { From d79009b1bae39dbec054bdfb2786351991cd3c01 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 22 Jun 2026 15:28:45 +0900 Subject: [PATCH 81/98] pmdomain: mediatek: mt6589: fix mfg bp_cfg Link: https://github.com/bq/aquaris-5/blob/bc1d0d0e35c969670e2d869001be944ad0c9c5e5/mediatek/platform/mt6589/kernel/core/mt_spm_mtcmos.c#L343 Assisted-by: Gemini 3.5 Flash --- drivers/pmdomain/mediatek/mt6589-pm-domains.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/pmdomain/mediatek/mt6589-pm-domains.h b/drivers/pmdomain/mediatek/mt6589-pm-domains.h index 53553f1932e596..e0b055154f4008 100644 --- a/drivers/pmdomain/mediatek/mt6589-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt6589-pm-domains.h @@ -10,6 +10,13 @@ * MT6589 power domain support */ +#define MT6589_BUS_PROT_INFRA_SI0_CTL_INV(_mask) \ + _BUS_PROT(_mask, 0x0200, 0x0200, 0, 0, \ + BUS_PROT_COMPONENT_INFRA | \ + BUS_PROT_REG_UPDATE | \ + BUS_PROT_INVERTED | \ + BUS_PROT_IGNORE_CLR_ACK) + static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { [MT6589_POWER_DOMAIN_MD1] = { .name = "md1", @@ -33,6 +40,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { .caps = MTK_SCPD_KEEP_DEFAULT_OFF, .bp_cfg = { BUS_PROT_INFRA_UPDATE_TOPAXI(0xac00), + BUS_PROT_INFRA_SI0_CTL_INV(0x0400), }, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, From 19a5ddd00f3bb09abbd956afb127cbdaea87b7bf Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 22 Jun 2026 15:29:53 +0900 Subject: [PATCH 82/98] pmdomain: mediatek: mt6589: fix... --- drivers/pmdomain/mediatek/mt6589-pm-domains.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mt6589-pm-domains.h b/drivers/pmdomain/mediatek/mt6589-pm-domains.h index e0b055154f4008..53cbddd1709706 100644 --- a/drivers/pmdomain/mediatek/mt6589-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt6589-pm-domains.h @@ -40,7 +40,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { .caps = MTK_SCPD_KEEP_DEFAULT_OFF, .bp_cfg = { BUS_PROT_INFRA_UPDATE_TOPAXI(0xac00), - BUS_PROT_INFRA_SI0_CTL_INV(0x0400), }, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, @@ -71,6 +70,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { .caps = MTK_SCPD_KEEP_DEFAULT_OFF, .bp_cfg = { BUS_PROT_INFRA_UPDATE_TOPAXI(0x0020), + BUS_PROT_INFRA_SI0_CTL_INV(0x0400), }, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, From 552eeb274fe7810f86ae82736c6d78a3aeac0c6a Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Mon, 22 Jun 2026 18:44:16 +0900 Subject: [PATCH 83/98] pmdomain: mediatek: mt6589: fix... 2 Signed-off-by: Akari Tsuyukusa --- drivers/pmdomain/mediatek/mt6589-pm-domains.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/mediatek/mt6589-pm-domains.h b/drivers/pmdomain/mediatek/mt6589-pm-domains.h index 53cbddd1709706..958b6fa3520d14 100644 --- a/drivers/pmdomain/mediatek/mt6589-pm-domains.h +++ b/drivers/pmdomain/mediatek/mt6589-pm-domains.h @@ -10,7 +10,7 @@ * MT6589 power domain support */ -#define MT6589_BUS_PROT_INFRA_SI0_CTL_INV(_mask) \ +#define MT6589_BUS_PROT_INFRA_SI0_CTL(_mask) \ _BUS_PROT(_mask, 0x0200, 0x0200, 0, 0, \ BUS_PROT_COMPONENT_INFRA | \ BUS_PROT_REG_UPDATE | \ @@ -70,7 +70,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt6589[] = { .caps = MTK_SCPD_KEEP_DEFAULT_OFF, .bp_cfg = { BUS_PROT_INFRA_UPDATE_TOPAXI(0x0020), - BUS_PROT_INFRA_SI0_CTL_INV(0x0400), + MT6589_BUS_PROT_INFRA_SI0_CTL(0x0400), }, .pwr_sta_offs = SPM_PWR_STATUS, .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, From cfc2a5c383865909d592e656d893e4b34c747303 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 23 Jun 2026 14:24:50 +0900 Subject: [PATCH 84/98] clk: mediatek: mt6589: fix typo, ops, copyright Signed-off-by:Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 6 +++-- drivers/clk/mediatek/clk-mt6589-aud.c | 2 +- drivers/clk/mediatek/clk-mt6589-disp.c | 2 +- drivers/clk/mediatek/clk-mt6589-img.c | 4 ++-- drivers/clk/mediatek/clk-mt6589-infracfg.c | 4 ++-- drivers/clk/mediatek/clk-mt6589-mfg.c | 2 +- drivers/clk/mediatek/clk-mt6589-pericfg.c | 6 ++--- drivers/clk/mediatek/clk-mt6589-topckgen.c | 16 ++++++------- drivers/clk/mediatek/clk-mt6589-vdec.c | 25 +++----------------- drivers/clk/mediatek/clk-mt6589-venc.c | 10 ++------ include/dt-bindings/clock/mt6589-clk.h | 4 ++-- 11 files changed, 29 insertions(+), 52 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c index 714670194270b7..653d25bffacea7 100644 --- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa * * Based on clk-mt2712-apmixedsys.c * Copyright (c) 2017 MediaTek Inc. @@ -117,6 +117,8 @@ static int clk_mt6589_apmixed_probe(struct platform_device *pdev) goto unregister_plls; } + platform_set_drvdata(pdev, clk_data); + return 0; unregister_plls: @@ -150,7 +152,7 @@ static struct platform_driver clk_mt6589_apmixed_drv = { .of_match_table = of_match_clk_mt6589_apmixed, }, }; -module_platform_driver(clk_mt6589_apmixed_drv) +module_platform_driver(clk_mt6589_apmixed_drv); MODULE_DESCRIPTION("MediaTek MT6589 apmixedsys clocks driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/clk/mediatek/clk-mt6589-aud.c b/drivers/clk/mediatek/clk-mt6589-aud.c index 3d322475f1961d..47a8adcb6cf504 100644 --- a/drivers/clk/mediatek/clk-mt6589-aud.c +++ b/drivers/clk/mediatek/clk-mt6589-aud.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include diff --git a/drivers/clk/mediatek/clk-mt6589-disp.c b/drivers/clk/mediatek/clk-mt6589-disp.c index cc01fb141194c1..17f13cc72750b5 100644 --- a/drivers/clk/mediatek/clk-mt6589-disp.c +++ b/drivers/clk/mediatek/clk-mt6589-disp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include diff --git a/drivers/clk/mediatek/clk-mt6589-img.c b/drivers/clk/mediatek/clk-mt6589-img.c index 77e21fd1dbda97..444a8f42de5f23 100644 --- a/drivers/clk/mediatek/clk-mt6589-img.c +++ b/drivers/clk/mediatek/clk-mt6589-img.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -26,7 +26,7 @@ static const struct mtk_gate_regs img_cg_regs = { static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMAGE_LARB3_SMI, "image_larb3_smi", "smi_sel", 0), /* maybe */ GATE_IMG(CLK_IMAGE_LARB4_SMI, "image_larb4_smi", "smi_sel", 2), /* maybe */ - GATE_IMG(CLK_IMAGE_COMMN_SMI, "image_commn_smi", "smi_sel", 4), /* maybe */ + GATE_IMG(CLK_IMAGE_COMMN_SMI, "image_common_smi", "smi_sel", 4), /* maybe */ GATE_IMG(CLK_IMAGE_CAM_SMI, "image_cam_smi", "smi_sel", 5), /* maybe */ GATE_IMG(CLK_IMAGE_CAM_CAM, "image_cam_cam", "cam_sel", 6), GATE_IMG(CLK_IMAGE_SEN_TG, "image_sen_tg", "camtg_sel", 7), diff --git a/drivers/clk/mediatek/clk-mt6589-infracfg.c b/drivers/clk/mediatek/clk-mt6589-infracfg.c index f16bd9167bb241..d292b446536b87 100644 --- a/drivers/clk/mediatek/clk-mt6589-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6589-infracfg.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -41,7 +41,7 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA(CLK_INFRA_SMI, "infra_smi", "smi_sel", 1), /* maybe */ GATE_INFRA(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 2), /* maybe, is it infra_mfg_bus? */ GATE_INFRA(CLK_INFRA_AUDIO, "infra_audio", "audintbus_sel", 5), - GATE_INFRA(CLK_INFRA_DEVAPC, "infra_devapc", "axi_sel", 6), /* is it infra cec (setclr_inv)? maybe correct parent */ + GATE_MTK(CLK_INFRA_CEC, "infra_cec", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr_inv), /* or devapc */ GATE_INFRA(CLK_INFRA_MFGAXI, "infra_mfgaxi", "axi_sel", 7), /* maybe */ GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), /* or axi_sel, maybe */ GATE_INFRA(CLK_INFRA_MD1MCUAXI, "infra_md1mcuaxi", "axi_sel", 9), /* maybe */ diff --git a/drivers/clk/mediatek/clk-mt6589-mfg.c b/drivers/clk/mediatek/clk-mt6589-mfg.c index 27ce3deac0637d..99ccf09a86829e 100644 --- a/drivers/clk/mediatek/clk-mt6589-mfg.c +++ b/drivers/clk/mediatek/clk-mt6589-mfg.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include diff --git a/drivers/clk/mediatek/clk-mt6589-pericfg.c b/drivers/clk/mediatek/clk-mt6589-pericfg.c index 1aaeef1b33c74a..b34aa36b62bf35 100644 --- a/drivers/clk/mediatek/clk-mt6589-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6589-pericfg.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -42,8 +42,8 @@ static const struct mtk_gate peri_clks[] = { GATE_PERI0(CLK_PERI0_PWM2, "peri_pwm2", "axi_sel", 3), /* maybe */ GATE_PERI0(CLK_PERI0_PWM3, "peri_pwm3", "axi_sel", 4), /* maybe */ GATE_PERI0(CLK_PERI0_PWM4, "peri_pwm4", "axi_sel", 5), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM5, "pwri_pwm5", "axi_sel", 6), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM6, "pwri_pwm6", "axi_sel", 7), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM5, "peri_pwm5", "axi_sel", 6), /* maybe */ + GATE_PERI0(CLK_PERI0_PWM6, "peri_pwm6", "axi_sel", 7), /* maybe */ GATE_PERI0(CLK_PERI0_PWM7, "peri_pwm7", "axi_sel", 8), /* maybe */ GATE_PERI0(CLK_PERI0_PWM, "peri_pwm", "axi_sel", 9), /* maybe */ GATE_PERI0(CLK_PERI0_USB0, "peri_usb0", "usb20_sel", 10), diff --git a/drivers/clk/mediatek/clk-mt6589-topckgen.c b/drivers/clk/mediatek/clk-mt6589-topckgen.c index 1e8e5756ae4ccc..34de6e9d2ca266 100644 --- a/drivers/clk/mediatek/clk-mt6589-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6589-topckgen.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -85,7 +85,7 @@ static const struct mtk_fixed_factor top_divs[] = { FACTOR(CLK_TOP_AD_MSDC_H208M_CK, "ad_msdc_h208m_ck", "msdcpll", 1, 8), // ? }; -static const char * axi_parents[] = { +static const char * const axi_parents[] = { "clk26m", "syspll_d3", "syspll_d4", @@ -95,7 +95,7 @@ static const char * axi_parents[] = { "syspll_d3p5", }; -static const char * smi_parents[] = { +static const char * const smi_parents[] = { "clk26m", "syspll_d3", "syspll_d8", @@ -164,7 +164,7 @@ static const char * const msdc1_parents[] = { "syspll_d6", "syspll_d5", "univpll1_d4", - "unicpll2_d4", + "univpll2_d4", "ad_msdc_h208m_ck", }; @@ -173,7 +173,7 @@ static const char * const msdc2_parents[] = { "syspll_d6", "syspll_d5", "univpll1_d4", - "unicpll2_d4", + "univpll2_d4", "ad_msdc_h208m_ck", }; @@ -182,7 +182,7 @@ static const char * const msdc3_parents[] = { "syspll_d6", "syspll_d5", "univpll1_d4", - "unicpll2_d4", + "univpll2_d4", "ad_msdc_h208m_ck", }; @@ -191,7 +191,7 @@ static const char * const msdc4_parents[] = { "syspll_d6", "syspll_d5", "univpll1_d4", - "unicpll2_d4", + "univpll2_d4", "ad_msdc_h208m_ck", }; @@ -314,7 +314,7 @@ static const char * const msdc0_parents[] = { "syspll_d6", "syspll_d5", "univpll1_d4", - "unicpll2_d4", + "univpll2_d4", "ad_msdc_h208m_ck", }; diff --git a/drivers/clk/mediatek/clk-mt6589-vdec.c b/drivers/clk/mediatek/clk-mt6589-vdec.c index 7b7c9c999b0a83..aa0d787e09b930 100644 --- a/drivers/clk/mediatek/clk-mt6589-vdec.c +++ b/drivers/clk/mediatek/clk-mt6589-vdec.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -15,29 +15,10 @@ #define LARB_CKEN_SET 0x0008 #define LARB_CKEN_CLR 0x000c -/* - * downstream - { - .name = __stringify(CG_VDEC0), - .set_addr = VDEC_CKEN_CLR, - .clr_addr = VDEC_CKEN_SET, - .mask = 0x00000001, - .ops = &vdec_cg_grp_ops, - .sys = &syss[SYS_VDE], - }, { - .name = __stringify(CG_VDEC1), - .set_addr = LARB_CKEN_CLR, - .clr_addr = LARB_CKEN_SET, - .mask = 0x00000001, - .ops = &vdec_cg_grp_ops, - .sys = &syss[SYS_VDE], - } - */ - static const struct mtk_gate_regs vdec_cg_regs = { .set_ofs = VDEC_CKEN_SET, .clr_ofs = VDEC_CKEN_CLR, - .sta_ofs = VDEC_CKEN_SET, /* many SoCs use set reg as sta reg */ + .sta_ofs = VDEC_CKEN_SET, }; static const struct mtk_gate_regs larb_cg_regs = { @@ -54,7 +35,7 @@ static const struct mtk_gate_regs larb_cg_regs = { static const struct mtk_gate vdec_clks[] = { GATE_VDEC(CLK_VDEC0_VDE, "vdec0_vde", "vdec_sel", 0), - GATE_LARB(CLK_VDEC1_SMI, "vdec0_smi", "vdec_sel", 0), + GATE_LARB(CLK_VDEC1_SMI, "vdec1_smi", "vdec_sel", 0), }; static const struct mtk_clk_desc vdec_desc = { diff --git a/drivers/clk/mediatek/clk-mt6589-venc.c b/drivers/clk/mediatek/clk-mt6589-venc.c index 57192e593377e8..3da31e91cad6d9 100644 --- a/drivers/clk/mediatek/clk-mt6589-venc.c +++ b/drivers/clk/mediatek/clk-mt6589-venc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Author: akku + * Author: Akari Tsuyukusa */ #include #include @@ -14,12 +14,6 @@ #define VENCSYS_CG_SET 0x0004 #define VENCSYS_CG_CLR 0x0008 -/* - * NOTE: downstream: - * .set_addr = VENCSYS_CG_CLR, - * .clr_addr = VENCSYS_CG_SET, - * .sta_addr = VENCSYS_CG_CON, - */ static const struct mtk_gate_regs venc_cg_regs = { .set_ofs = VENCSYS_CG_SET, .clr_ofs = VENCSYS_CG_CLR, @@ -27,7 +21,7 @@ static const struct mtk_gate_regs venc_cg_regs = { }; #define GATE_VENC(_id, _name, _parent, _shift) \ - GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) static const struct mtk_gate venc_clks[] = { GATE_VENC(CLK_VENC_VEN, "venc_ven", "venc_sel", 0), diff --git a/include/dt-bindings/clock/mt6589-clk.h b/include/dt-bindings/clock/mt6589-clk.h index ed8c44a43d2b2a..00cc66fefd9375 100644 --- a/include/dt-bindings/clock/mt6589-clk.h +++ b/include/dt-bindings/clock/mt6589-clk.h @@ -166,7 +166,7 @@ #define CLK_INFRA_SMI 2 #define CLK_INFRA_SPI0 3 #define CLK_INFRA_AUDIO 4 -#define CLK_INFRA_DEVAPC 5 +#define CLK_INFRA_CEC 5 #define CLK_INFRA_MFGAXI 6 #define CLK_INFRA_M4U 7 #define CLK_INFRA_MD1MCUAXI 8 @@ -271,7 +271,7 @@ /* IMG */ #define CLK_IMAGE_LARB3_SMI 0 #define CLK_IMAGE_LARB4_SMI 1 -#define CLK_IMAGE_COMMN_SMI 2 +#define CLK_IMAGE_COMMON_SMI 2 #define CLK_IMAGE_CAM_SMI 3 #define CLK_IMAGE_CAM_CAM 4 #define CLK_IMAGE_SEN_TG 5 From 9014b571c29a4c390c004b0363409ce31cd5c591 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 23 Jun 2026 15:12:57 +0900 Subject: [PATCH 85/98] arm: dts: mediatek: mt6589: fix interrupt trigger Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 3354e252e0f8ba..62403167e56da6 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -49,10 +49,10 @@ timer { compatible = "arm,armv7-timer"; interrupt-parent = <&gic>; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <13000000>; arm,cpu-registers-not-fw-configured; }; @@ -382,7 +382,7 @@ timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; - interrupts = ; + interrupts = ; clocks = <&system_clk>, <&rtc_clk>; clock-names = "system-clk", "rtc-clk"; }; @@ -430,12 +430,12 @@ <0x11000800 0x54>, <0x11000880 0x54>, <0x11000900 0x54>; - interrupts = , - , - , - , - , - ; + interrupts = , + , + , + , + , + ; dma-requests = <6>; clocks = <&pericfg CLK_PERI0_APDMA>; clock-names = "apdma"; From 20d5e91a0334a9889b0e98b26cf8a1d37a88a153 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Fri, 26 Jun 2026 17:31:40 +0900 Subject: [PATCH 86/98] arm: dts: mt6589: remove mediatek,have-pmic; from non-pmic i2c nodes Assisted-by: DeepSeek:deepseek-v4-pro Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 62403167e56da6..75751e757b19a6 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -213,7 +213,6 @@ <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; clock-div = <16>; - mediatek,have-pmic; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -229,7 +228,6 @@ <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; clock-div = <16>; - mediatek,have-pmic; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -245,7 +243,6 @@ <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; clock-div = <16>; - mediatek,have-pmic; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -261,7 +258,6 @@ <&pericfg CLK_PERI0_APDMA>; clock-names = "main", "pmic", "dma"; clock-div = <16>; - mediatek,have-pmic; status = "disabled"; #address-cells = <1>; #size-cells = <0>; From a07f80c83fe4b6865caf2515f3498106a8836bc2 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:15:31 +0900 Subject: [PATCH 87/98] dt-bindings: reset: mt6589: add MT6589_TOPRGU_RST_NUM Signed-off-by: Akari Tsuyukusa --- include/dt-bindings/reset/mt6589-resets.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/reset/mt6589-resets.h b/include/dt-bindings/reset/mt6589-resets.h index f7960ac04203b5..814afb508d5aa5 100644 --- a/include/dt-bindings/reset/mt6589-resets.h +++ b/include/dt-bindings/reset/mt6589-resets.h @@ -65,6 +65,8 @@ #define MT6589_TOPRGU_APMIXED_RST 10 #define MT6589_TOPRGU_PWRAP_SPICTL_RST 11 +#define MT6589_TOPRGU_RST_NUM 12 + /* MFG */ #define MT6589_MFG_AXI_RESET 0 #define MT6589_MFG_G3D_RESET 1 From f626396d9f52fe6d339d40b3e202d73f36e7b602 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:32:52 +0900 Subject: [PATCH 88/98] watchdog: mtk_wdt: add explicit compatible entries for fallback SoCs Assisted-by: DeepSeek:deepseek-v4-pro Signed-off-by: Akari Tsuyukusa --- drivers/watchdog/mtk_wdt.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 91d110646e16f7..9613566cf00fa1 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -492,17 +492,26 @@ static int mtk_wdt_resume(struct device *dev) } static const struct of_device_id mtk_wdt_dt_ids[] = { + { .compatible = "mediatek,mt2701-wdt" }, { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, + { .compatible = "mediatek,mt6582-wdt" }, { .compatible = "mediatek,mt6589-wdt" }, { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data }, { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, + { .compatible = "mediatek,mt6797-wdt" }, + { .compatible = "mediatek,mt7622-wdt" }, + { .compatible = "mediatek,mt7623-wdt" }, + { .compatible = "mediatek,mt7629-wdt" }, { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data }, { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data }, + { .compatible = "mediatek,mt8173-wdt" }, { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data }, { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data }, { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data }, { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data }, { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data }, + { .compatible = "mediatek,mt8365-wdt" }, + { .compatible = "mediatek,mt8516-wdt" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids); From 149308d39fe7cc6d24913ef16ec7fa644291a7d9 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:46:51 +0900 Subject: [PATCH 89/98] dt-bindings: watchdog: mtk-wdt: add single compatibles Signed-off-by: Akari Tsuyukusa --- .../devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index 8d2520241e37f0..a904778bc2ae9c 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -20,17 +20,26 @@ properties: compatible: oneOf: - enum: + - mediatek,mt2701-wdt - mediatek,mt2712-wdt + - mediatek,mt6582-wdt - mediatek,mt6589-wdt - mediatek,mt6735-wdt - mediatek,mt6795-wdt + - mediatek,mt6797-wdt + - mediatek,mt7622-wdt + - mediatek,mt7623-wdt + - mediatek,mt7629-wdt - mediatek,mt7986-wdt - mediatek,mt7988-wdt + - mediatek,mt8173-wdt - mediatek,mt8183-wdt - mediatek,mt8186-wdt - mediatek,mt8188-wdt - mediatek,mt8192-wdt - mediatek,mt8195-wdt + - mediatek,mt8365-wdt + - mediatek,mt8516-wdt - items: - enum: - mediatek,mt2701-wdt From ad86137c89bee6576a711edad38f3bf2ccfe9ee3 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:47:25 +0900 Subject: [PATCH 90/98] arm: dts: mediatek: remove mt6589 fallback from watchdog nodes Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt2701.dtsi | 3 +-- arch/arm/boot/dts/mediatek/mt6582.dtsi | 3 +-- arch/arm/boot/dts/mediatek/mt6589.dtsi | 1 + arch/arm/boot/dts/mediatek/mt7623.dtsi | 3 +-- arch/arm/boot/dts/mediatek/mt7629.dtsi | 3 +-- 5 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi index ce6a4015fed5ad..6d4a6a27bfaf6b 100644 --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -160,8 +160,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt2701-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt2701-wdt"; reg = <0 0x10007000 0 0x100>; }; diff --git a/arch/arm/boot/dts/mediatek/mt6582.dtsi b/arch/arm/boot/dts/mediatek/mt6582.dtsi index 4263371784cd15..2ef4b43450c9eb 100644 --- a/arch/arm/boot/dts/mediatek/mt6582.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6582.dtsi @@ -121,8 +121,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt6582-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt6582-wdt"; reg = <0x10007000 0x100>; }; }; diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 75751e757b19a6..c147d284cd06ba 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -93,6 +93,7 @@ wdt: watchdog@10000000 { compatible = "mediatek,mt6589-wdt"; reg = <0x10000000 0x44>; + #reset-cells = <1>; }; topckgen: syscon@10000100 { diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index fd7a89cc337d69..eb9e95d53bb6e2 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -281,8 +281,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt7623-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt7623-wdt"; reg = <0 0x10007000 0 0x100>; }; diff --git a/arch/arm/boot/dts/mediatek/mt7629.dtsi b/arch/arm/boot/dts/mediatek/mt7629.dtsi index acab0883a3bbf2..b034e9ab5af1f4 100644 --- a/arch/arm/boot/dts/mediatek/mt7629.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi @@ -141,8 +141,7 @@ }; watchdog: watchdog@10212000 { - compatible = "mediatek,mt7629-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt7629-wdt"; reg = <0x10212000 0x100>; }; From 9236b4528458ba8cc123d6efd0a157b031d59776 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:47:33 +0900 Subject: [PATCH 91/98] arm64: dts: mediatek: remove mt6589 fallback from watchdog nodes Signed-off-by: Akari Tsuyukusa --- arch/arm64/boot/dts/mediatek/mt6797.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 3 +-- arch/arm64/boot/dts/mediatek/mt8516.dtsi | 3 +-- 5 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6797.dtsi b/arch/arm64/boot/dts/mediatek/mt6797.dtsi index 0e9d11b4585be2..bf9a3cfff4ee08 100644 --- a/arch/arm64/boot/dts/mediatek/mt6797.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6797.dtsi @@ -218,7 +218,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; + compatible = "mediatek,mt6797-wdt"; reg = <0 0x10007000 0 0x100>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 917fa39a74f8d7..c195a0d4d5da48 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -318,8 +318,7 @@ }; watchdog: watchdog@10212000 { - compatible = "mediatek,mt7622-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt7622-wdt"; reg = <0 0x10212000 0 0x800>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 6d1d8877b43f24..ae0278ec6ea0ac 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -520,8 +520,7 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8173-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8173-wdt"; reg = <0 0x10007000 0 0x100>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index e6d2b3221a3b7a..b9a2878d9fbfc1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -428,9 +428,8 @@ }; watchdog: watchdog@10007000 { - compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8365-wdt"; reg = <0 0x10007000 0 0x100>; - #reset-cells = <1>; }; pio: pinctrl@1000b000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi index b5e753759465d9..515eed0bee217f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi @@ -203,8 +203,7 @@ }; watchdog@10007000 { - compatible = "mediatek,mt8516-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt8516-wdt"; reg = <0 0x10007000 0 0x1000>; interrupts = ; #reset-cells = <1>; From 1fa411ccc77603f225aadb72a8d1686ce3b5489a Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:47:57 +0900 Subject: [PATCH 92/98] dt-bindings: watchdog: mtk-wdt: remove mt6589 fallback Signed-off-by: Akari Tsuyukusa --- .../bindings/watchdog/mediatek,mtk-wdt.yaml | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml index a904778bc2ae9c..e8152942c0a1d9 100644 --- a/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml @@ -40,18 +40,6 @@ properties: - mediatek,mt8195-wdt - mediatek,mt8365-wdt - mediatek,mt8516-wdt - - items: - - enum: - - mediatek,mt2701-wdt - - mediatek,mt6582-wdt - - mediatek,mt6797-wdt - - mediatek,mt7622-wdt - - mediatek,mt7623-wdt - - mediatek,mt7629-wdt - - mediatek,mt8173-wdt - - mediatek,mt8365-wdt - - mediatek,mt8516-wdt - - const: mediatek,mt6589-wdt reg: maxItems: 1 From 66a1a4b58c9e3ad5d3a997c0fa400cf718eb7ffb Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:51:08 +0900 Subject: [PATCH 93/98] watchdog: mtk_wdt: add mt6589 reset support Signed-off-by: Akari Tsuyukusa --- drivers/watchdog/mtk_wdt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index 9613566cf00fa1..e7d440917ce339 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -88,6 +89,10 @@ static const struct mtk_wdt_data mt2712_data = { .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM, }; +static const struct mtk_wdt_data mt6589_data = { + .toprgu_sw_rst_num = MT6589_TOPRGU_RST_NUM, +}; + static const struct mtk_wdt_data mt6735_data = { .toprgu_sw_rst_num = MT6735_TOPRGU_RST_NUM, }; @@ -495,7 +500,7 @@ static const struct of_device_id mtk_wdt_dt_ids[] = { { .compatible = "mediatek,mt2701-wdt" }, { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data }, { .compatible = "mediatek,mt6582-wdt" }, - { .compatible = "mediatek,mt6589-wdt" }, + { .compatible = "mediatek,mt6589-wdt", .data = &mt6589_data }, { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data }, { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data }, { .compatible = "mediatek,mt6797-wdt" }, From d2df63baf9223782c6cf923a484e637bcc7c5cfb Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 20:52:11 +0900 Subject: [PATCH 94/98] arm: dts: mediatek: mt6589: restore timer's interrupt trigger no one wants it, IRQ_TYPE_LEVEL_HIGH is untested Signed-off-by: Akari Tsuyukusa --- arch/arm/boot/dts/mediatek/mt6589.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index c147d284cd06ba..7efaf786ce1a2a 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -379,7 +379,7 @@ timer: timer@10008000 { compatible = "mediatek,mt6577-timer"; reg = <0x10008000 0x80>; - interrupts = ; + interrupts = ; clocks = <&system_clk>, <&rtc_clk>; clock-names = "system-clk", "rtc-clk"; }; From c18c7d7179b4cf63f4f36bc85e88dd9e6c92bd24 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Tue, 30 Jun 2026 21:06:50 +0900 Subject: [PATCH 95/98] clk: mediatek: mt6589-img: fix typo followup --- drivers/clk/mediatek/clk-mt6589-img.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt6589-img.c b/drivers/clk/mediatek/clk-mt6589-img.c index 444a8f42de5f23..6db48ee142f399 100644 --- a/drivers/clk/mediatek/clk-mt6589-img.c +++ b/drivers/clk/mediatek/clk-mt6589-img.c @@ -26,7 +26,7 @@ static const struct mtk_gate_regs img_cg_regs = { static const struct mtk_gate img_clks[] = { GATE_IMG(CLK_IMAGE_LARB3_SMI, "image_larb3_smi", "smi_sel", 0), /* maybe */ GATE_IMG(CLK_IMAGE_LARB4_SMI, "image_larb4_smi", "smi_sel", 2), /* maybe */ - GATE_IMG(CLK_IMAGE_COMMN_SMI, "image_common_smi", "smi_sel", 4), /* maybe */ + GATE_IMG(CLK_IMAGE_COMMON_SMI, "image_common_smi", "smi_sel", 4), /* maybe */ GATE_IMG(CLK_IMAGE_CAM_SMI, "image_cam_smi", "smi_sel", 5), /* maybe */ GATE_IMG(CLK_IMAGE_CAM_CAM, "image_cam_cam", "cam_sel", 6), GATE_IMG(CLK_IMAGE_SEN_TG, "image_sen_tg", "camtg_sel", 7), From 87c4232fa78d5b7c621dc5f39034fb8787bafa27 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 1 Jul 2026 09:25:44 +0900 Subject: [PATCH 96/98] arm: dts: mediatek: mt6589: use mediatek,mt8135-mmc insted of mediatek,mt2701-mmc --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 5 ++++- arch/arm/boot/dts/mediatek/mt6589.dtsi | 10 +++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 12e32abd21457d..76874d51db12a6 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -29,9 +29,12 @@ properties: - mediatek,mt8516-mmc - items: - enum: - - mediatek,mt6589-mmc - mediatek,mt7623-mmc - const: mediatek,mt2701-mmc + - items: + - enum: + - mediatek,mt6589-mmc + - const: mediatek,mt8135-mmc - items: - enum: - mediatek,mt6893-mmc diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi index 7efaf786ce1a2a..6910146a69eff1 100644 --- a/arch/arm/boot/dts/mediatek/mt6589.dtsi +++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi @@ -484,7 +484,7 @@ mmc0: mmc@11230000 { compatible = "mediatek,mt6589-mmc", - "mediatek,mt2701-mmc"; + "mediatek,mt8135-mmc"; reg = <0x11230000 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI0_MSDC0>, @@ -495,7 +495,7 @@ mmc1: mmc@11240000 { compatible = "mediatek,mt6589-mmc", - "mediatek,mt2701-mmc"; + "mediatek,mt8135-mmc"; reg = <0x11240000 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI0_MSDC1>, @@ -506,7 +506,7 @@ mmc2: mmc@11250000 { compatible = "mediatek,mt6589-mmc", - "mediatek,mt2701-mmc"; + "mediatek,mt8135-mmc"; reg = <0x11250000 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI0_MSDC2>, @@ -517,7 +517,7 @@ mmc3: mmc@11260000 { compatible = "mediatek,mt6589-mmc", - "mediatek,mt2701-mmc"; + "mediatek,mt8135-mmc"; reg = <0x11260000 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI0_MSDC3>, @@ -528,7 +528,7 @@ mmc4: mmc@11270000 { compatible = "mediatek,mt6589-mmc", - "mediatek,mt2701-mmc"; + "mediatek,mt8135-mmc"; reg = <0x11270000 0x1000>; interrupts = ; clocks = <&pericfg CLK_PERI0_MSDC4>, From 165755b544bfa03382e012d78fca7dea457ca9d8 Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 1 Jul 2026 14:34:22 +0900 Subject: [PATCH 97/98] clk: mediatek: mt6589-topckgen: remove BASE_SHIFT --- drivers/clk/mediatek/clk-mt6589-topckgen.c | 27 ++++++++++------------ 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6589-topckgen.c b/drivers/clk/mediatek/clk-mt6589-topckgen.c index 34de6e9d2ca266..a6bbc36f0873db 100644 --- a/drivers/clk/mediatek/clk-mt6589-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6589-topckgen.c @@ -10,9 +10,6 @@ #include -/* HACK: reg starts from 0x10000100 to avoid overlap with the watchdog register area */ -#define BASE_SHIFT 0x0100 - static DEFINE_SPINLOCK(mt6589_clk_lock); static const struct mtk_fixed_clk top_fixed_clks[] = { @@ -325,15 +322,15 @@ static const char * const smi_mfg_as_parents[] = { "hyd_sel", }; -#define CLK_CFG_0 (0x0140 - BASE_SHIFT) -#define CLK_CFG_1 (0x0144 - BASE_SHIFT) -#define CLK_CFG_2 (0x0148 - BASE_SHIFT) -#define CLK_CFG_3 (0x014c - BASE_SHIFT) -#define CLK_CFG_4 (0x0150 - BASE_SHIFT) -#define CLK_CFG_5 (0x0154 - BASE_SHIFT) -#define CLK_CFG_6 (0x0158 - BASE_SHIFT) -#define CLK_CFG_7 (0x015c - BASE_SHIFT) -#define CLK_CFG_8 (0x0164 - BASE_SHIFT) +#define CLK_CFG_0 0x40 +#define CLK_CFG_1 0x44 +#define CLK_CFG_2 0x48 +#define CLK_CFG_3 0x4c +#define CLK_CFG_4 0x50 +#define CLK_CFG_5 0x54 +#define CLK_CFG_6 0x58 +#define CLK_CFG_7 0x5c +#define CLK_CFG_8 0x64 static struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ @@ -407,9 +404,9 @@ static struct mtk_composite top_muxes[] = { CLK_CFG_8, 16, 2, 23), }; -#define TOPCK_PDN_SET (0x0170 - BASE_SHIFT) -#define TOPCK_PDN_CLR (0x0174 - BASE_SHIFT) -#define TOPCK_PDN_STA (0x0178 - BASE_SHIFT) +#define TOPCK_PDN_SET 0x70 +#define TOPCK_PDN_CLR 0x74 +#define TOPCK_PDN_STA 0x78 static const struct mtk_gate_regs topck_cg_regs = { .set_ofs = TOPCK_PDN_SET, From 3d5566f2c7ca447d8784768de5f45390b711b05d Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Wed, 1 Jul 2026 15:56:07 +0900 Subject: [PATCH 98/98] clk: mediatek: mt6589: sync with mt8135 --- drivers/clk/mediatek/clk-mt6589-img.c | 14 +++--- drivers/clk/mediatek/clk-mt6589-infracfg.c | 20 ++++----- drivers/clk/mediatek/clk-mt6589-mfg.c | 2 +- drivers/clk/mediatek/clk-mt6589-pericfg.c | 50 +++++++++++----------- drivers/clk/mediatek/clk-mt6589-vdec.c | 2 +- 5 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6589-img.c b/drivers/clk/mediatek/clk-mt6589-img.c index 6db48ee142f399..4320f07510f258 100644 --- a/drivers/clk/mediatek/clk-mt6589-img.c +++ b/drivers/clk/mediatek/clk-mt6589-img.c @@ -24,18 +24,18 @@ static const struct mtk_gate_regs img_cg_regs = { GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate img_clks[] = { - GATE_IMG(CLK_IMAGE_LARB3_SMI, "image_larb3_smi", "smi_sel", 0), /* maybe */ - GATE_IMG(CLK_IMAGE_LARB4_SMI, "image_larb4_smi", "smi_sel", 2), /* maybe */ - GATE_IMG(CLK_IMAGE_COMMON_SMI, "image_common_smi", "smi_sel", 4), /* maybe */ - GATE_IMG(CLK_IMAGE_CAM_SMI, "image_cam_smi", "smi_sel", 5), /* maybe */ + GATE_IMG(CLK_IMAGE_LARB3_SMI, "image_larb3_smi", "smi_sel", 0), /* mt8135 */ + GATE_IMG(CLK_IMAGE_LARB4_SMI, "image_larb4_smi", "smi_sel", 2), /* mt8135 */ + GATE_IMG(CLK_IMAGE_COMMON_SMI, "image_common_smi", "smi_sel", 4), /* mt8135 */ + GATE_IMG(CLK_IMAGE_CAM_SMI, "image_cam_smi", "smi_sel", 5), /* mt8135 */ GATE_IMG(CLK_IMAGE_CAM_CAM, "image_cam_cam", "cam_sel", 6), GATE_IMG(CLK_IMAGE_SEN_TG, "image_sen_tg", "camtg_sel", 7), GATE_IMG(CLK_IMAGE_SEN_CAM, "image_sen_cam", "cam_sel", 8), - GATE_IMG(CLK_IMAGE_JPGD_SMI, "image_jpgd_smi", "smi_sel", 9), /* maybe, mt8135 */ + GATE_IMG(CLK_IMAGE_JPGD_SMI, "image_jpgd_smi", "smi_sel", 9), /* mt8135 */ GATE_IMG(CLK_IMAGE_JPGD_JPG, "image_jpgd_jpg", "jpg_sel", 10), - GATE_IMG(CLK_IMAGE_JPGE_SMI, "image_jpge_smi", "smi_sel", 11), /* maybe, mt8135 */ + GATE_IMG(CLK_IMAGE_JPGE_SMI, "image_jpge_smi", "smi_sel", 11), /* mt8135 */ GATE_IMG(CLK_IMAGE_JPGE_JPG, "image_jpge_jpg", "jpg_sel", 12), - GATE_IMG(CLK_IMAGE_FPC, "image_fpc", "smi_sel", 13), /* maybe, mt8135 */ + GATE_IMG(CLK_IMAGE_FPC, "image_fpc", "smi_sel", 13), /* mt8135 */ }; static const struct mtk_clk_desc img_desc = { diff --git a/drivers/clk/mediatek/clk-mt6589-infracfg.c b/drivers/clk/mediatek/clk-mt6589-infracfg.c index d292b446536b87..5abaa9732d8171 100644 --- a/drivers/clk/mediatek/clk-mt6589-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6589-infracfg.c @@ -37,25 +37,25 @@ static const struct mtk_gate_regs infra_cg_regs = { GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { - GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), /* maybe */ - GATE_INFRA(CLK_INFRA_SMI, "infra_smi", "smi_sel", 1), /* maybe */ + GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), /* mt8135 */ + GATE_INFRA(CLK_INFRA_SMI, "infra_smi", "smi_sel", 1), /* mt8135 */ GATE_INFRA(CLK_INFRA_SPI0, "infra_spi0", "spi_sel", 2), /* maybe, is it infra_mfg_bus? */ GATE_INFRA(CLK_INFRA_AUDIO, "infra_audio", "audintbus_sel", 5), GATE_MTK(CLK_INFRA_CEC, "infra_cec", "axi_sel", &infra_cg_regs, 6, &mtk_clk_gate_ops_setclr_inv), /* or devapc */ - GATE_INFRA(CLK_INFRA_MFGAXI, "infra_mfgaxi", "axi_sel", 7), /* maybe */ - GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), /* or axi_sel, maybe */ + GATE_INFRA(CLK_INFRA_MFGAXI, "infra_mfgaxi", "axi_sel", 7), /* mt8135 */ + GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), /* mt8135 */ GATE_INFRA(CLK_INFRA_MD1MCUAXI, "infra_md1mcuaxi", "axi_sel", 9), /* maybe */ GATE_INFRA(CLK_INFRA_MD1HWMIXAXI, "infra_md1hwmixaxi", "axi_sel", 10), /* maybe */ GATE_INFRA(CLK_INFRA_MD1AHB, "infra_md1ahb", "axi_sel", 11), /* maybe */ GATE_INFRA(CLK_INFRA_MD2MCUAXI, "infra_md2mcuaxi", "axi_sel", 12), /* maybe */ GATE_INFRA(CLK_INFRA_MD2HWMIXAXI, "infra_md2hwmixaxi", "axi_sel", 13), /* maybe */ GATE_INFRA(CLK_INFRA_MD2AHB, "infra_md2ahb", "axi_sel", 14), /* maybe */ - GATE_INFRA(CLK_INFRA_CPUM, "infra_cpum", "cpum_tck_in", 15), /* from MT8135 */ - GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), /* maybe */ - GATE_INFRA(CLK_INFRA_CCIF0, "infra_ccif0", "axi_sel", 20), /* maybe */ - GATE_INFRA(CLK_INFRA_CCIF1, "infra_ccif1", "axi_sel", 21), /* maybe */ - GATE_INFRA(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), /* maybe */ - GATE_INFRA(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), /* maybe */ + GATE_INFRA(CLK_INFRA_CPUM, "infra_cpum", "cpum_tck_in", 15), /* mt8135 */ + GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), /* mt8135 */ + GATE_INFRA(CLK_INFRA_CCIF0, "infra_ccif0", "axi_sel", 20), /* mt8135 */ + GATE_INFRA(CLK_INFRA_CCIF1, "infra_ccif1", "axi_sel", 21), /* mt8135 */ + GATE_INFRA(CLK_INFRA_PMICSPI, "infra_pmicspi", "pmicspi_sel", 22), /* mt8135 */ + GATE_INFRA(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), /* mt8135 */ }; static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; diff --git a/drivers/clk/mediatek/clk-mt6589-mfg.c b/drivers/clk/mediatek/clk-mt6589-mfg.c index 99ccf09a86829e..855cac4fd27e98 100644 --- a/drivers/clk/mediatek/clk-mt6589-mfg.c +++ b/drivers/clk/mediatek/clk-mt6589-mfg.c @@ -24,7 +24,7 @@ static const struct mtk_gate_regs mfg_cg_regs = { GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate mfg_clks[] = { - GATE_MFG(CLK_MFG_AXI, "mfg_axi", "infra_mfgaxi", 0), /* or axi_sel, maybe */ + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_sel", 0), /* mt8135 (or infra_mfgaxi) */ GATE_MFG(CLK_MFG_MEM, "mfg_mem", "smi_mfg_as_sel", 1), GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2), GATE_MFG(CLK_MFG_HYD, "mfg_hyd", "hyd_sel", 3), diff --git a/drivers/clk/mediatek/clk-mt6589-pericfg.c b/drivers/clk/mediatek/clk-mt6589-pericfg.c index b34aa36b62bf35..343e7daad6568c 100644 --- a/drivers/clk/mediatek/clk-mt6589-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6589-pericfg.c @@ -36,44 +36,44 @@ static const struct mtk_gate_regs peri1_cg_regs = { GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) static const struct mtk_gate peri_clks[] = { - GATE_PERI0(CLK_PERI0_NFI, "peri_nfi", "axi_sel", 0), /* auxadc, maybe */ - GATE_PERI0(CLK_PERI0_THERM, "peri_therm", "axi_sel", 1), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM1, "peri_pwm1", "axi_sel", 2), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM2, "peri_pwm2", "axi_sel", 3), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM3, "peri_pwm3", "axi_sel", 4), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM4, "peri_pwm4", "axi_sel", 5), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM5, "peri_pwm5", "axi_sel", 6), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM6, "peri_pwm6", "axi_sel", 7), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM7, "peri_pwm7", "axi_sel", 8), /* maybe */ - GATE_PERI0(CLK_PERI0_PWM, "peri_pwm", "axi_sel", 9), /* maybe */ + GATE_PERI0(CLK_PERI0_NFI, "peri_nfi", "axi_sel", 0), /* mt8135 */ + GATE_PERI0(CLK_PERI0_THERM, "peri_therm", "axi_sel", 1), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM1, "peri_pwm1", "axi_sel", 2), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM2, "peri_pwm2", "axi_sel", 3), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM3, "peri_pwm3", "axi_sel", 4), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM4, "peri_pwm4", "axi_sel", 5), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM5, "peri_pwm5", "axi_sel", 6), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM6, "peri_pwm6", "axi_sel", 7), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM7, "peri_pwm7", "axi_sel", 8), /* mt8135 */ + GATE_PERI0(CLK_PERI0_PWM, "peri_pwm", "axi_sel", 9), /* mt8135 */ GATE_PERI0(CLK_PERI0_USB0, "peri_usb0", "usb20_sel", 10), GATE_PERI0(CLK_PERI0_USB1, "peri_usb1", "usb20_sel", 11), - GATE_PERI0(CLK_PERI0_APDMA, "peri_apdma", "axi_sel", 12), /* maybe */ + GATE_PERI0(CLK_PERI0_APDMA, "peri_apdma", "axi_sel", 12), /* mt8135 */ GATE_PERI0(CLK_PERI0_MSDC0, "peri_msdc0", "msdc0_sel", 13), GATE_PERI0(CLK_PERI0_MSDC1, "peri_msdc1", "msdc1_sel", 14), GATE_PERI0(CLK_PERI0_MSDC2, "peri_msdc2", "msdc2_sel", 15), GATE_PERI0(CLK_PERI0_MSDC3, "peri_msdc3", "msdc3_sel", 16), GATE_PERI0(CLK_PERI0_MSDC4, "peri_msdc4", "msdc4_sel", 17), - GATE_PERI0(CLK_PERI0_APHIF, "peri_aphif", "axi_sel", 18), /* maybe */ - GATE_PERI0(CLK_PERI0_MDHIF, "peri_mdhif", "axi_sel", 19), /* maybe */ - GATE_PERI0(CLK_PERI0_NLI, "peri_nli", "axi_sel", 20), /* maybe */ + GATE_PERI0(CLK_PERI0_APHIF, "peri_aphif", "axi_sel", 18), /* mt8135 */ + GATE_PERI0(CLK_PERI0_MDHIF, "peri_mdhif", "axi_sel", 19), /* mt8135 */ + GATE_PERI0(CLK_PERI0_NLI, "peri_nli", "axi_sel", 20), /* mt8135 */ GATE_PERI0(CLK_PERI0_IRDA, "peri_irda", "irda_sel", 21), GATE_PERI0(CLK_PERI0_UART0, "peri_uart0", "peri_uart0_sel", 22), GATE_PERI0(CLK_PERI0_UART1, "peri_uart1", "peri_uart1_sel", 23), GATE_PERI0(CLK_PERI0_UART2, "peri_uart2", "peri_uart2_sel", 24), GATE_PERI0(CLK_PERI0_UART3, "peri_uart3", "peri_uart3_sel", 25), - GATE_PERI0(CLK_PERI0_I2C0, "peri_i2c0", "axi_sel", 26), /* maybe */ - GATE_PERI0(CLK_PERI0_I2C1, "peri_i2c1", "axi_sel", 27), /* maybe */ - GATE_PERI0(CLK_PERI0_I2C2, "peri_i2c2", "axi_sel", 28), /* maybe */ - GATE_PERI0(CLK_PERI0_I2C3, "peri_i2c3", "axi_sel", 29), /* maybe */ - GATE_PERI0(CLK_PERI0_I2C4, "peri_i2c4", "axi_sel", 30), /* maybe */ - GATE_PERI0(CLK_PERI0_I2C5, "peri_i2c5", "axi_sel", 31), /* maybe */ - - GATE_PERI1(CLK_PERI1_I2C6, "peri_i2c6", "axi_sel", 0), /* maybe */ - GATE_PERI1(CLK_PERI1_PWRAP, "peri_pwrap", "axi_sel", 1), /* maybe */ - GATE_PERI1(CLK_PERI1_AUXADC, "peri_auxadc", "axi_sel", 2), /* maybe */ + GATE_PERI0(CLK_PERI0_I2C0, "peri_i2c0", "axi_sel", 26), /* mt8135 */ + GATE_PERI0(CLK_PERI0_I2C1, "peri_i2c1", "axi_sel", 27), /* mt8135 */ + GATE_PERI0(CLK_PERI0_I2C2, "peri_i2c2", "axi_sel", 28), /* mt8135 */ + GATE_PERI0(CLK_PERI0_I2C3, "peri_i2c3", "axi_sel", 29), /* mt8135 */ + GATE_PERI0(CLK_PERI0_I2C4, "peri_i2c4", "axi_sel", 30), /* mt8135 */ + GATE_PERI0(CLK_PERI0_I2C5, "peri_i2c5", "axi_sel", 31), /* mt8135 */ + + GATE_PERI1(CLK_PERI1_I2C6, "peri_i2c6", "axi_sel", 0), /* mt8135 */ + GATE_PERI1(CLK_PERI1_PWRAP, "peri_pwrap", "axi_sel", 1), /* mt8135 */ + GATE_PERI1(CLK_PERI1_AUXADC, "peri_auxadc", "axi_sel", 2), /* mt8135 */ GATE_PERI1(CLK_PERI1_SPI1, "peri_spi1", "spi_sel", 3), - GATE_PERI1(CLK_PERI1_FHCTL, "peri_fhctl", "clk26m", 4), /* maybe */ + GATE_PERI1(CLK_PERI1_FHCTL, "peri_fhctl", "clk26m", 4), /* mt8135 */ }; static const char * const uart_mux_parents[] = { diff --git a/drivers/clk/mediatek/clk-mt6589-vdec.c b/drivers/clk/mediatek/clk-mt6589-vdec.c index aa0d787e09b930..9e6b5c8185c537 100644 --- a/drivers/clk/mediatek/clk-mt6589-vdec.c +++ b/drivers/clk/mediatek/clk-mt6589-vdec.c @@ -35,7 +35,7 @@ static const struct mtk_gate_regs larb_cg_regs = { static const struct mtk_gate vdec_clks[] = { GATE_VDEC(CLK_VDEC0_VDE, "vdec0_vde", "vdec_sel", 0), - GATE_LARB(CLK_VDEC1_SMI, "vdec1_smi", "vdec_sel", 0), + GATE_LARB(CLK_VDEC1_SMI, "vdec1_smi", "smi_sel", 0), /* mt8135 */ }; static const struct mtk_clk_desc vdec_desc = {