From f8c9ee1c2abdd4b007abc01f455a653e37e30aaf Mon Sep 17 00:00:00 2001 From: Mikhail Nevskiy Date: Wed, 28 Oct 2026 20:03:37 +0300 Subject: [PATCH 1/2] clk: mediatek: mt6589: msdcpll_208m is msdcpll / 2, not / 8 The MSDC source tap of MSDCPLL is the VCO divided by 8, taken before the /4 post divider. "msdcpll" (390 MHz here) already includes that post divider, so the tap is msdcpll / 2 (195 MHz), not msdcpll / 8 (48.75 MHz). With 1/8 the clock framework believed every MSDC source ran at a quarter of its real rate, so mtk-sd chose dividers that ran each bus about four times faster than requested. The eMMC asked for 24 MHz ran at about 97 MHz. That explains the data CRC errors on the eMMC and on the SDIO bus of the MT6628. Tested on the Lenovo B8000-H (MT8389). The clock summary before the change showed msdcpll at 390000000 and msdcpll_208m at 48750000. Since 27 Sep 2026 our kernels have carried this change, with the eMMC root and the MT6628 Wi-Fi on MSDC3 (SDIO) in daily use. Assisted-by: Claude:claude-opus-5-5 Signed-off-by: Mikhail Nevskiy --- drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c index 2498589c255fca..f0ed2d05bb38a7 100644 --- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -193,7 +193,11 @@ static const struct mtk_fixed_factor pll_divs[] = { FACTOR(CLK_APMIXED_ISPPLL_208M, "isppll_208m", "isppll", 1, 8), - FACTOR(CLK_APMIXED_MSDCPLL_208M, "msdcpll_208m", "msdcpll", 1, 8), + /* + * The MSDC source tap is VCO/8, taken before the /4 post divider + * that "msdcpll" (390 MHz) already includes: msdcpll / 2. + */ + FACTOR(CLK_APMIXED_MSDCPLL_208M, "msdcpll_208m", "msdcpll", 1, 2), FACTOR(CLK_APMIXED_TVDPLL_148P5M, "tvdpll_148p5m", "tvdpll", 1, 16), From 2321368269b42afec52a8e031069048ce3ad4e9d Mon Sep 17 00:00:00 2001 From: Akari Tsuyukusa Date: Sat, 31 Oct 2026 20:38:57 +0900 Subject: [PATCH 2/2] clk: mediatek: mt6589: fix pll div rate based on 85c8f8f882183d3be2008d1b7f9a21673f832428 Signed-off-by: Akari Tsuyukusa --- drivers/clk/mediatek/clk-mt6589-apmixedsys.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c index f0ed2d05bb38a7..ff5c79f533b6b8 100644 --- a/drivers/clk/mediatek/clk-mt6589-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt6589-apmixedsys.c @@ -191,17 +191,13 @@ static const struct mtk_fixed_factor pll_divs[] = { FACTOR(CLK_APMIXED_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5), FACTOR(CLK_APMIXED_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7), - FACTOR(CLK_APMIXED_ISPPLL_208M, "isppll_208m", "isppll", 1, 8), + FACTOR(CLK_APMIXED_ISPPLL_208M, "isppll_208m", "isppll", 1, 2), - /* - * The MSDC source tap is VCO/8, taken before the /4 post divider - * that "msdcpll" (390 MHz) already includes: msdcpll / 2. - */ FACTOR(CLK_APMIXED_MSDCPLL_208M, "msdcpll_208m", "msdcpll", 1, 2), FACTOR(CLK_APMIXED_TVDPLL_148P5M, "tvdpll_148p5m", "tvdpll", 1, 16), - FACTOR(CLK_APMIXED_LVDSPLL_180M, "lvdspll_180m", "lvdspll", 1, 8), + FACTOR(CLK_APMIXED_LVDSPLL_180M, "lvdspll_180m", "lvdspll", 1, 2), }; static const struct mtk_clk_desc apmixed_desc = {