diff --git a/Bender.lock b/Bender.lock index 9684f42..155c610 100644 --- a/Bender.lock +++ b/Bender.lock @@ -71,7 +71,7 @@ packages: - common_verification - register_interface insitu-cache: - revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49 + revision: fbabd6a06fd801c960078517ad47f7994130b944 version: null source: Git: https://github.com/pulp-platform/Insitu-Cache.git diff --git a/Bender.yml b/Bender.yml index 45b01da..2f457d1 100644 --- a/Bender.yml +++ b/Bender.yml @@ -14,7 +14,7 @@ dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8 } riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.7.0 } tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 } - Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/cachepool_dev } + Insitu-Cache: { git: "https://github.com/pulp-platform/Insitu-Cache.git", rev: zexin/sync-flush-fixes } spatz: { git: "https://github.com/pulp-platform/spatz.git", rev: cachepool-32b } dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", rev: cachepool } @@ -49,6 +49,10 @@ sources: - hardware/src/cachepool_cluster.sv # Level 4 - hardware/tb/cachepool_cluster_wrapper.sv + # sim-only verification IP (bind-attached; excluded from synth/lint) + - target: simulation + files: + - hardware/src/verif/cachepool_tile_tcdm_checker.sv # testbench - target: cachepool_test files: diff --git a/Makefile b/Makefile index 588cf0f..c3dc460 100644 --- a/Makefile +++ b/Makefile @@ -251,6 +251,12 @@ VLOG_DEFS += -DL1D_TILE_SIZE=$(l1d_tile_size) VLOG_DEFS += -DL1D_TAG_DATA_WIDTH=$(l1d_tag_data_width) VLOG_DEFS += -DL1D_NUM_BANKS=$(l1d_num_banks) VLOG_DEFS += -DL1D_DEPTH=$(l1d_depth) +# L1 data-bank micro-architecture knobs (1=on/0=off). Production = folded(1) + +# hash-way(1) + fwd-buffer(1). Unfolded conventional = folded(0)+hash(0)+fwd(0). +VLOG_DEFS += -DL1D_USE_FOLDED=$(l1d_use_folded) +VLOG_DEFS += -DL1D_FOLD_WAY_GROUP=$(l1d_fold_way_group) +VLOG_DEFS += -DL1D_USE_HASH_WAY=$(l1d_use_hash_way) +VLOG_DEFS += -DL1D_USE_FWD_BUF=$(l1d_use_fwd_buf) # CachePool CC / core cluster VLOG_DEFS += -DSPATZ_FPU_EN=$(spatz_fpu_en) @@ -277,6 +283,8 @@ VLOG_DEFS += -DPERIPH_START_ADDR=$(periph_start_addr) VLOG_DEFS += -DBOOT_ADDR=$(boot_addr) VLOG_DEFS += -DUART_ADDR=$(uart_addr) +VLOG_DEFS += -DENABLE_SPATZ_REQ_SCOREBOARD + ENABLE_CACHEPOOL_TESTS ?= 1 # Bender targets diff --git a/config/cachepool_2t_fpu_512.mk b/config/cachepool_2t_fpu_512.mk new file mode 100644 index 0000000..4ed66ba --- /dev/null +++ b/config/cachepool_2t_fpu_512.mk @@ -0,0 +1,101 @@ +# Copyright 2026 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# 2-tile / 8-core FPU variant of cachepool_fpu_512. +# Bisect point between 1t/4c (works) and 4t/16c (broken) to isolate +# whether the bug is in the inter-tile (group-level) xbar at all, or +# only at 4t. + +######################### +## CachePool Cluster ## +######################### + +# Number of tiles +num_tiles ?= 2 + +# Number of cores +num_cores ?= 8 + +# Core datawidth +data_width ?= 32 + +# Core addrwidth +addr_width ?= 32 + +num_remote_ports_per_tile ?= 1 + + +###################### +## CachePool Tile ## +###################### + +# Number of cores per CachePool tile +num_cores_per_tile ?= 4 + +# Refill interconnection data width +refill_data_width ?= 128 + +##### L1 Data Cache ##### + +# L1 data cacheline width (in Bit) +l1d_cacheline_width ?= 512 + +# L1 data cache size (in KiB) +l1d_size ?= 256 + +# L1 data cache banking factor (how many banks per core?) +l1d_bank_factor ?= 1 + +# L1 coalecsing window +l1d_coal_window ?= 2 + +# L1 data cache number of ways per +l1d_num_way ?= 4 + +# L1 data cache size per tile (KiB) +l1d_tile_size ?= 256 + +# L1 data cache tag width (TODO: should be calcualted) +l1d_tag_data_width ?= 92 + +#################### +## CachePool CC ## +#################### +# Spatz fpu support? +spatz_fpu_en ?= 1 + +# Spatz number of FPU +spatz_num_fpu ?= 4 + +# Spatz number of IPU +spatz_num_ipu ?= 4 + +# Spatz max outstanding transactions +spatz_max_trans ?= 32 + +# Snitch/FPU max outstanding transactions +snitch_max_trans ?= 16 + + +##################### +## L2 Main Memory ## +##################### +# L2 number of channels +l2_channel ?= 4 + +# L2 bank width (DRAM width, change with care) +l2_bank_width ?= 512 + +# L2 interleaving factor (in order of bank_width) +l2_interleave ?= 16 + + +################## +## Peripherals ## +################## +# Hardware stack size (in Byte) +stack_hw_size ?= 1024 + +# Stack size (total, including share and private, 32'h800) +stack_tot_size ?= 2048 diff --git a/config/cachepool_512.mk b/config/cachepool_512.mk index 6d04a68..4de9b76 100644 --- a/config/cachepool_512.mk +++ b/config/cachepool_512.mk @@ -9,10 +9,10 @@ ######################### # Number of tiles -num_tiles ?= 4 +num_tiles ?= 1 # Number of cores -num_cores ?= 16 +num_cores ?= 4 # Core datawidth data_width ?= 32 @@ -54,6 +54,18 @@ l1d_tile_size ?= 256 # L1 data cache tag width (TODO: should be calcualted) l1d_tag_data_width ?= 92 +# L1 data-bank micro-architecture (1=on, 0=off). +# Production cache = folded(1) + hash-way(1) + fwd-buffer(1). +# Unfolded "conventional" cache = folded(0) + hash-way(0) + fwd-buffer(0). +# Constraints (enforced by RTL elaboration asserts): +# - folded (l1d_use_folded=1) REQUIRES l1d_use_hash_way=1 +# - fwd-buffer (l1d_use_fwd_buf=1) REQUIRES l1d_use_hash_way=1 +# l1d_fold_way_group=0 => auto (min(4, ways)). +l1d_use_folded ?= 1 +l1d_fold_way_group ?= 0 +l1d_use_hash_way ?= 1 +l1d_use_fwd_buf ?= 1 + #################### ## CachePool CC ## #################### diff --git a/config/cachepool_fpu_512.mk b/config/cachepool_fpu_512.mk index 2e4c3ca..93fb2fb 100644 --- a/config/cachepool_fpu_512.mk +++ b/config/cachepool_fpu_512.mk @@ -56,6 +56,18 @@ l1d_tile_size ?= 256 # L1 data cache tag width (TODO: should be calcualted) l1d_tag_data_width ?= 92 +# L1 data-bank micro-architecture (1=on, 0=off). +# Production cache = folded(1) + hash-way(1) + fwd-buffer(1). +# Unfolded "conventional" cache = folded(0) + hash-way(0) + fwd-buffer(0). +# Constraints (enforced by RTL elaboration asserts): +# - folded (l1d_use_folded=1) REQUIRES l1d_use_hash_way=1 +# - fwd-buffer (l1d_use_fwd_buf=1) REQUIRES l1d_use_hash_way=1 +# l1d_fold_way_group=0 => auto (min(4, ways)). +l1d_use_folded ?= 1 +l1d_fold_way_group ?= 0 +l1d_use_hash_way ?= 1 +l1d_use_fwd_buf ?= 1 + #################### ## CachePool CC ## #################### diff --git a/config/config.mk b/config/config.mk index 9eee8cb..99eec8e 100644 --- a/config/config.mk +++ b/config/config.mk @@ -105,14 +105,57 @@ snitch_max_trans ?= 16 ## AXI configuration ## ######################### +# axi_user_width sets the AXI 'user' field that carries refill_user_t over the +# cache->L2 AXI. Hard requirement: axi_user_width >= $bits(refill_user_t). +# This floor is now enforced in RTL by ASSERT_INIT(CheckAxiUserFitsRefillUser) +# in cachepool_cluster.sv, and the cluster zero-extends refill_user_t onto the +# (wider) AXI user port at the reqrsp_to_axi call site. +# +# refill_user_t = bank_id(BankIDWidth) + tile_id(TileIDWidth) +# + cache_info_t + burst_req_t +# cache_info_t = {for_write_pend, depth, way} -- NOTE: NO tile_id inside. +# +# So refill_user_t carries TileIDWidth exactly ONCE. The values below are +# deliberately conservative headroom, not an exact fit: the per-tile adjustment +# adds 2*(idx_width(NumTiles)-1) bits, and cachepool_pkg.sv:163 then adds a +# further clog2(NumTiles) (SpatzAxiUserWidth = AXI_USER_WIDTH + clog2(NumTiles)), +# so the tile term ends up over-provisioned. This is harmless: no RTL reads any +# AXI user bit above $bits(refill_user_t)-1. +# (An earlier version of this comment claimed cache_info_t held a second +# TileIDWidth copy and therefore doubled idx_width(NumTiles) -- it does not; +# the 2x factor is just slack, kept as-is for headroom.) +# +# Do NOT let axi_user_width drop below $bits(refill_user_t): the MSB of bank_id +# (or higher tile_id) would be truncated on the AXI loopback and refill +# responses would route back to the wrong slv port (e.g. bank_id=4 aliases to +# bank_id=0, sending cb=3's refill response to the icache bypass slot, making +# cb=3 hang). The ASSERT_INIT above catches this at elaboration. + +ifeq ($(num_tiles),1) + axi_user_tile_adj := 0 +else ifeq ($(num_tiles),2) + axi_user_tile_adj := 0 +else ifeq ($(num_tiles),4) + axi_user_tile_adj := 2 +else ifeq ($(num_tiles),8) + axi_user_tile_adj := 4 +else ifeq ($(num_tiles),16) + axi_user_tile_adj := 6 +else + $(error num_tiles=$(num_tiles) not handled by axi_user_width formula; add a case in config.mk) +endif + +# Base widths for NumTiles=1 (= reference values, verified working). ifeq ($(l1d_cacheline_width),512) - axi_user_width := 17 + axi_user_base := 18 else ifeq ($(l1d_cacheline_width),256) - axi_user_width := 18 + axi_user_base := 19 else ifeq ($(l1d_cacheline_width),128) - axi_user_width := 21 + axi_user_base := 22 endif +axi_user_width := $(shell echo $$(( $(axi_user_base) + $(axi_user_tile_adj) ))) + ##################### ## L2 Main Memory ## ##################### diff --git a/hardware/src/cachepool_cc.sv b/hardware/src/cachepool_cc.sv index 86c8d7e..64e26d5 100644 --- a/hardware/src/cachepool_cc.sv +++ b/hardware/src/cachepool_cc.sv @@ -95,6 +95,23 @@ module cachepool_cc /// Insert Pipeline registers into data memory path (response) parameter bit RegisterCoreRsp = 0, parameter snitch_pma_pkg::snitch_pma_t SnitchPMACfg = '{default: 0}, + /// DEBUG: enable Spatz<->TCDM request/response scoreboard. + /// When 1, per-port counters and a queue of outstanding (id,addr,write) + /// records are exposed in the waveform under + /// gen_spatz_req_scoreboard.gen_port[P]/{req_id_q,rsp_id_q,outstanding_q,sb_q,...} + /// A watchdog $displays the contents of any port that has been stuck + /// for >5 us (configurable below). Defaults off; pass + /// +define+ENABLE_SPATZ_REQ_SCOREBOARD + /// to vlog to enable globally, or override per instance. +`ifdef ENABLE_SPATZ_REQ_SCOREBOARD + parameter bit EnableSpatzReqScoreboard = 1'b1, +`else + parameter bit EnableSpatzReqScoreboard = 1'b0, +`endif + /// DEBUG: scoreboard depth (entries per port). + parameter int unsigned SpatzReqScoreboardDepth = 64, + /// DEBUG: watchdog timeout in ps. 0 disables the watchdog. + parameter longint unsigned SpatzReqScoreboardWdogPs = 5_000_000, /// Derived parameter *Do not override* parameter int unsigned NumSpatzFUs = (NumSpatzFPUs > NumSpatzIPUs) ? NumSpatzFPUs : NumSpatzIPUs, parameter int unsigned NumMemPortsPerSpatz = NumSpatzFUs, @@ -276,7 +293,10 @@ module cachepool_cc tcdm_rsp_chan_t [NumMemPortsPerSpatz-1:0] spatz_mem_rsp, spatz_mem_fifo; logic [NumMemPortsPerSpatz-1:0] spatz_mem_rsp_valid; logic [NumMemPortsPerSpatz-1:0] spatz_mem_rsp_ready; - logic [NumMemPortsPerSpatz-1:0] spatz_mem_rsp_empty, spatz_mem_rsp_pop, spatz_mem_rsp_push, spatz_mem_fifo_bypass; + logic [NumMemPortsPerSpatz-1:0] spatz_mem_rsp_empty, spatz_mem_rsp_full; + logic [NumMemPortsPerSpatz-1:0] spatz_mem_rsp_pop, spatz_mem_rsp_push; + localparam int unsigned SpatzRspFifoDepth = + (NumSpatzOutstandingLoads > 0) ? NumSpatzOutstandingLoads : 1; spatz #( .NrMemPorts (NumMemPortsPerSpatz ), @@ -326,7 +346,7 @@ module cachepool_cc fifo_v3 #( .dtype (tcdm_rsp_chan_t ), - .DEPTH (4 ), + .DEPTH (SpatzRspFifoDepth ), .FALL_THROUGH (1 ) ) i_spatz_rsp_fifo ( .clk_i (clk_i ), @@ -337,31 +357,250 @@ module cachepool_cc .push_i (spatz_mem_rsp_push[p] ), .data_o (spatz_mem_fifo[p] ), .pop_i (spatz_mem_rsp_pop[p] ), - .full_o ( ), + .full_o (spatz_mem_rsp_full[p] ), .empty_o (spatz_mem_rsp_empty[p]), .usage_o (/* Unused */ ) ); - // bypass fifo if response is valid and write - assign spatz_mem_fifo_bypass[p] = tcdm_rsp_i[p].p_valid & tcdm_rsp_i[p].p.write; - always_comb begin spatz_mem_rsp_valid[p] = !spatz_mem_rsp_empty[p]; spatz_mem_rsp[p] = spatz_mem_fifo[p]; - // if input response is valid, put it into fifo for HS check by default + // Queue every response to avoid lossy bypass under backpressure. spatz_mem_rsp_push[p] = tcdm_rsp_i[p].p_valid; spatz_mem_rsp_pop[p] = spatz_mem_rsp_valid[p] & spatz_mem_rsp_ready[p]; + end - // Bypass FIFO if is a write response - if (spatz_mem_fifo_bypass[p]) begin - // make sure not write this response into fifo - spatz_mem_rsp_push[p] = 1'b0; - spatz_mem_rsp_pop[p] = 1'b0; - spatz_mem_rsp_valid[p] = 1'b1; - spatz_mem_rsp[p] = tcdm_rsp_i[p].p; +`ifndef TARGET_SYNTHESIS + always_ff @(posedge clk_i) begin + if (rst_ni && tcdm_rsp_i[p].p_valid && spatz_mem_rsp_full[p] && !spatz_mem_rsp_pop[p]) begin + $error("[cachepool_cc] Spatz response FIFO overflow on port %0d", p); end end +`endif end + // --------------------------------------------------------------------------- + // Spatz<->TCDM request/response scoreboard (DEBUG ONLY). + // + // Compile-time gated by `EnableSpatzReqScoreboard`. When the parameter is + // 1'b0 the entire `gen_spatz_req_scoreboard` block is elaborated empty and + // synthesizes to nothing. + // + // The scoreboard is a per-port table indexed by `user.req_id` (NOT a + // FIFO). This is critical because: + // + // * The 4 cache banks can return responses in any global order. + // * Each cache bank has MSHRs and supports hit-under-miss / miss-under- + // miss, so even a single bank can return responses out-of-order. + // + // A FIFO scoreboard would mis-attribute out-of-order responses to the + // wrong issued request. Indexing the slot table by `user.req_id` makes + // the match correct regardless of arrival order: when a response arrives + // its `user.req_id` directly identifies which outstanding entry it + // resolves. + // + // Per port: + // sb_q[p][id] -- {valid, write, global_id, addr, issue_time} + // Slot is filled on req_fire (idx = req's user.req_id); + // cleared on rsp_fire (idx = rsp's user.req_id). + // `valid` set means an outstanding request with that + // `user.req_id` is currently in flight. + // req_id_q -- 32-bit cumulative count of issued reqs (sanity) + // rsp_id_q -- 32-bit cumulative count of received rsps (sanity) + // outstanding_q -- req_id_q - rsp_id_q (in-flight count) + // req_fire/rsp_fire -- per-cycle handshake strobes (waveform aid) + // + // The slot table size = `NumSpatzOutstandingLoads`, which is the maximum + // number of unique `user.req_id` values Spatz can issue per port. Spatz + // does not reuse a `user.req_id` while another request with the same id + // is in flight, so each slot can hold at most one entry at any time. + // + // SVA / watchdog: + // * sba_no_dup_push : asserts a slot is not already valid when pushed. + // * sba_pop_was_valid: asserts a slot was valid when popped. + // * watchdog $displays valid entries of stuck ports every WdogPs ps. + // --------------------------------------------------------------------------- + localparam int unsigned SpatzSbPorts = NumMemPortsPerSpatz; + localparam int unsigned SpatzSbReqIdW = (NumSpatzOutstandingLoads <= 1) ? 1 + : $clog2(NumSpatzOutstandingLoads); + localparam int unsigned SpatzSbDepth = (NumSpatzOutstandingLoads <= 1) ? 1 + : NumSpatzOutstandingLoads; + + typedef struct packed { + logic valid; + logic write; + logic [31:0] global_id; // monotonic counter at issue time + logic [31:0] addr; + logic [63:0] issue_time; // $time at issue (sim only) + } spatz_sb_entry_t; + + if (EnableSpatzReqScoreboard) begin : gen_spatz_req_scoreboard + + // Module-scope arrays. Adding the array name once in the wave window + // expands to all ports / all ids. + logic [SpatzSbPorts-1:0][31:0] req_id_q, req_id_d; + logic [SpatzSbPorts-1:0][31:0] rsp_id_q, rsp_id_d; + logic [SpatzSbPorts-1:0][31:0] outstanding_q, outstanding_d; + spatz_sb_entry_t [SpatzSbPorts-1:0][SpatzSbDepth-1:0] sb_q, sb_d; + logic [SpatzSbPorts-1:0] req_fire; + logic [SpatzSbPorts-1:0] rsp_fire; + // Per-cycle indices used (waveform aid) + logic [SpatzSbPorts-1:0][SpatzSbReqIdW-1:0] req_idx; + logic [SpatzSbPorts-1:0][SpatzSbReqIdW-1:0] rsp_idx; +`ifndef TARGET_SYNTHESIS + logic [SpatzSbPorts-1:0][63:0] last_progress_time_q; + logic [SpatzSbPorts-1:0][63:0] last_warn_time_q; + // Loop indices hoisted out of always blocks (debug-only). + int unsigned sb_log_pp; + int unsigned wdog_p; + int unsigned wdog_ii; +`endif + + `FFARN(req_id_q, req_id_d, '0, clk_i, rst_ni) + `FFARN(rsp_id_q, rsp_id_d, '0, clk_i, rst_ni) + `FFARN(outstanding_q, outstanding_d, '0, clk_i, rst_ni) + `FFARN(sb_q, sb_d, '0, clk_i, rst_ni) + + for (genvar p = 0; p < SpatzSbPorts; p++) begin : gen_port + assign req_fire[p] = spatz_mem_req_valid[p] & spatz_mem_req_ready[p]; + assign rsp_fire[p] = spatz_mem_rsp_valid[p] & spatz_mem_rsp_ready[p]; + // Slot index is the lower SpatzSbReqIdW bits of user.req_id. + // (`reqid_t` is exactly that width, so this is a width match.) + assign req_idx[p] = SpatzSbReqIdW'(spatz_mem_req[p].user.req_id); + assign rsp_idx[p] = SpatzSbReqIdW'(spatz_mem_rsp[p].user.req_id); + + always_comb begin + req_id_d[p] = req_id_q[p]; + rsp_id_d[p] = rsp_id_q[p]; + sb_d[p] = sb_q[p]; + + // Push (slot indexed by request's user.req_id). + if (req_fire[p]) begin + req_id_d[p] = req_id_q[p] + 32'd1; + sb_d[p][req_idx[p]].valid = 1'b1; + sb_d[p][req_idx[p]].write = spatz_mem_req[p].write; + sb_d[p][req_idx[p]].global_id = req_id_q[p]; + sb_d[p][req_idx[p]].addr = 32'(spatz_mem_req[p].addr); +`ifndef TARGET_SYNTHESIS + sb_d[p][req_idx[p]].issue_time = 64'($time); +`else + sb_d[p][req_idx[p]].issue_time = '0; +`endif + end + + // Pop (slot indexed by response's user.req_id). + // If both fire same cycle for the SAME id, the pop wins (rare, + // would require Spatz to re-issue the id in the same cycle the + // previous one resolves; semantics match a straight-through hit). + if (rsp_fire[p]) begin + rsp_id_d[p] = rsp_id_q[p] + 32'd1; + sb_d[p][rsp_idx[p]].valid = 1'b0; + end + + outstanding_d[p] = (req_id_d[p] - rsp_id_d[p]); + end + end : gen_port + +`ifndef TARGET_SYNTHESIS + // Verbose push/pop log (gated by +spatz_sb_verbose plusarg). + // Useful for debugging the exact request/response sequence on a port. + // Each event prints time, port, side, req_id, addr (push only). + bit sb_verbose_log = 1'b0; + initial begin + // verilog_lint: waive plusarg-assignment + sb_verbose_log = $test$plusargs("spatz_sb_verbose"); + end + always_ff @(posedge clk_i) begin + if (rst_ni && sb_verbose_log) begin + for (sb_log_pp = 0; sb_log_pp < SpatzSbPorts; sb_log_pp++) begin + if (req_fire[sb_log_pp]) begin + $display({"[SPATZ-SB-LOG %0t %m] port=%0d PUSH req_id=0x%02h ", + "addr=0x%08h global_id=%0d write=%0b"}, + $time, sb_log_pp, req_idx[sb_log_pp], spatz_mem_req[sb_log_pp].addr, + req_id_q[sb_log_pp], spatz_mem_req[sb_log_pp].write); + end + if (rsp_fire[sb_log_pp]) begin + $display({"[SPATZ-SB-LOG %0t %m] port=%0d POP rsp_id=0x%02h ", + "slot_valid_pre=%0b slot_addr_pre=0x%08h slot_gid_pre=%0d ", + "rsp_data=0x%08h rsp_write=%0b"}, + $time, sb_log_pp, rsp_idx[sb_log_pp], + sb_q[sb_log_pp][rsp_idx[sb_log_pp]].valid, + sb_q[sb_log_pp][rsp_idx[sb_log_pp]].addr, + sb_q[sb_log_pp][rsp_idx[sb_log_pp]].global_id, + spatz_mem_rsp[sb_log_pp].data, + spatz_mem_rsp[sb_log_pp].write); + end + end + end + end + + // SVA: a request must not push to a slot that is already valid (would + // mean Spatz reused a user.req_id while a previous one with the same + // id was still in flight -- a protocol violation). + for (genvar p = 0; p < SpatzSbPorts; p++) begin : gen_assert_dup_push + property p_no_dup_push; + @(posedge clk_i) disable iff (!rst_ni) + req_fire[p] |-> !sb_q[p][req_idx[p]].valid; + endproperty + sba_no_dup_push: assert property (p_no_dup_push) + else $error({"[SPATZ-SB %m port %0d] DUP-PUSH: req_id=0x%h slot already ", + "valid (prior global_id=%0d addr=0x%08h)"}, + p, req_idx[p], + sb_q[p][req_idx[p]].global_id, + sb_q[p][req_idx[p]].addr); + + // SVA: a response must not pop a slot that is invalid (would mean + // a response arrived for a request that was never issued or already + // resolved). + property p_pop_was_valid; + @(posedge clk_i) disable iff (!rst_ni) + rsp_fire[p] |-> sb_q[p][rsp_idx[p]].valid; + endproperty + sba_pop_was_valid: assert property (p_pop_was_valid) + else $error({"[SPATZ-SB %m port %0d] STRAY-RSP: rsp_id=0x%h ", + "has no matching outstanding request"}, + p, rsp_idx[p]); + end + + // Watchdog: when a port has not received any rsp for SpatzReqScoreboardWdogPs + // and outstanding > 0, dump the still-valid entries (each is the + // exact `user.req_id` whose response is missing). Re-warns every + // WdogPs while still stuck. + if (SpatzReqScoreboardWdogPs > 0) begin : gen_wdog + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + last_progress_time_q <= '0; + last_warn_time_q <= '0; + end else begin + for (wdog_p = 0; wdog_p < SpatzSbPorts; wdog_p++) begin + if (rsp_fire[wdog_p] || outstanding_q[wdog_p] == 32'd0) begin + last_progress_time_q[wdog_p] <= 64'($time); + last_warn_time_q[wdog_p] <= 64'($time); + end + if (outstanding_q[wdog_p] != 32'd0 && + (64'($time) - last_progress_time_q[wdog_p]) > SpatzReqScoreboardWdogPs && + (64'($time) - last_warn_time_q[wdog_p]) > SpatzReqScoreboardWdogPs) begin + last_warn_time_q[wdog_p] <= 64'($time); + $display({"[%0t] [SPATZ-SB %m port %0d] STUCK: req_cnt=%0d rsp_cnt=%0d ", + "outstanding=%0d (entries below indexed by user.req_id)"}, + $time, wdog_p, req_id_q[wdog_p], rsp_id_q[wdog_p], outstanding_q[wdog_p]); + for (wdog_ii = 0; wdog_ii < SpatzSbDepth; wdog_ii++) begin + if (sb_q[wdog_p][wdog_ii].valid) begin + $display({" user.req_id=0x%02h global_id=%0d addr=0x%08h ", + "write=%0b issued@%0t (age=%0t)"}, + wdog_ii, sb_q[wdog_p][wdog_ii].global_id, + sb_q[wdog_p][wdog_ii].addr, sb_q[wdog_p][wdog_ii].write, + sb_q[wdog_p][wdog_ii].issue_time, + 64'($time) - sb_q[wdog_p][wdog_ii].issue_time); + end + end + end + end + end + end + end +`endif + end : gen_spatz_req_scoreboard + typedef enum integer { SnitchMem = 0, FPUMem = 1 @@ -948,6 +1187,107 @@ module cachepool_cc `ASSERT_INIT(BootAddrAligned, BootAddr[1:0] == 2'b00) +`ifndef TARGET_SYNTHESIS + // --------------------------------------------------------------------- + // Probe D: targeted address watcher at the Spatz boundary. + // Off by default; enable with +spatz_write_watch plusarg. + // --------------------------------------------------------------------- + bit spatz_write_watch_en = 1'b0; + // verilog_lint: waive plusarg-assignment + initial spatz_write_watch_en = $test$plusargs("spatz_write_watch"); + + // Loop indices hoisted out of always/final blocks (debug-only). + int unsigned dbg_swwatch_p; + int unsigned dbg_wabal_p; + int unsigned dbg_wabal_fp; + + always_ff @(posedge clk_i) begin + if (rst_ni && spatz_write_watch_en) begin + for (dbg_swwatch_p = 0; dbg_swwatch_p < TCDMPorts; dbg_swwatch_p++) begin + if (tcdm_req_o[dbg_swwatch_p].q_valid && tcdm_rsp_i[dbg_swwatch_p].q_ready && + tcdm_req_o[dbg_swwatch_p].q.write) begin + if (tcdm_req_o[dbg_swwatch_p].q.addr == 32'ha0001308 || + tcdm_req_o[dbg_swwatch_p].q.addr == 32'ha0001700 || + tcdm_req_o[dbg_swwatch_p].q.addr == 32'ha0001730) begin + $display({"[SPATZ-WRITE-WATCH %0t %m port %0d] addr=0x%08h data=0x%08h ", + "strb=0x%h user_tile=%0d user_core=%0d user_req=0x%h"}, + $time, dbg_swwatch_p, tcdm_req_o[dbg_swwatch_p].q.addr, + tcdm_req_o[dbg_swwatch_p].q.data, + tcdm_req_o[dbg_swwatch_p].q.strb, + tcdm_req_o[dbg_swwatch_p].q.user.tile_id, + tcdm_req_o[dbg_swwatch_p].q.user.core_id, + tcdm_req_o[dbg_swwatch_p].q.user.req_id); + end + end + end + end + end + + // --------------------------------------------------------------------- + // Probe C: per-port write-ack balance at the cachepool_cc <-> tile interface + // (req side) AND at the FIFO push/pop level (downstream of tile interface). + // --------------------------------------------------------------------- + logic [TCDMPorts-1:0][63:0] cc_wreq_n; + logic [TCDMPorts-1:0][63:0] cc_wack_n; + logic [TCDMPorts-1:0][63:0] cc_wfifo_push_n; + logic [TCDMPorts-1:0][63:0] cc_wfifo_pop_n; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + cc_wreq_n <= '0; + cc_wack_n <= '0; + cc_wfifo_push_n <= '0; + cc_wfifo_pop_n <= '0; + end else begin + for (dbg_wabal_p = 0; dbg_wabal_p < TCDMPorts; dbg_wabal_p++) begin + if (tcdm_req_o[dbg_wabal_p].q_valid && tcdm_rsp_i[dbg_wabal_p].q_ready && + tcdm_req_o[dbg_wabal_p].q.write) + cc_wreq_n[dbg_wabal_p] <= cc_wreq_n[dbg_wabal_p] + 64'd1; + if (tcdm_rsp_i[dbg_wabal_p].p_valid && tcdm_rsp_i[dbg_wabal_p].p.write) + cc_wack_n[dbg_wabal_p] <= cc_wack_n[dbg_wabal_p] + 64'd1; + // FIFO push side: any p_valid pushes; count those with write=1 + if (dbg_wabal_p < NumMemPortsPerSpatz) begin // only Spatz ports have FIFO + if (spatz_mem_rsp_push[dbg_wabal_p] && tcdm_rsp_i[dbg_wabal_p].p.write) + cc_wfifo_push_n[dbg_wabal_p] <= cc_wfifo_push_n[dbg_wabal_p] + 64'd1; + if (spatz_mem_rsp_pop[dbg_wabal_p] && spatz_mem_fifo[dbg_wabal_p].write) + cc_wfifo_pop_n[dbg_wabal_p] <= cc_wfifo_pop_n[dbg_wabal_p] + 64'd1; + end + end + end + end + + final begin + for (dbg_wabal_fp = 0; dbg_wabal_fp < TCDMPorts; dbg_wabal_fp++) begin + // Hard error: the cache failed to acknowledge a write that Spatz issued + // (a genuinely lost write-ack). Valid at EOC because the cache drains + // all accepted requests even after Spatz goes idle. + if (cc_wreq_n[dbg_wabal_fp] != cc_wack_n[dbg_wabal_fp]) begin + $error("[CC-WR-BAL %m port %0d] req-rsp IMBALANCE wreq=%0d wack=%0d diff=%0d", + dbg_wabal_fp, cc_wreq_n[dbg_wabal_fp], cc_wack_n[dbg_wabal_fp], + cc_wreq_n[dbg_wabal_fp] - cc_wack_n[dbg_wabal_fp]); + end + // FIFO push-pop residue: a tail is benign. After EOC the hart is idle + // (main returned) so Spatz never pops the last few acks the cache pushed. + // Such a tail cannot exceed the FIFO depth; only escalate to an error if + // it does, which means pushes were lost to overflow (a real fault). + if (dbg_wabal_fp < NumMemPortsPerSpatz && + cc_wfifo_push_n[dbg_wabal_fp] != cc_wfifo_pop_n[dbg_wabal_fp]) begin + if ((cc_wfifo_push_n[dbg_wabal_fp] - cc_wfifo_pop_n[dbg_wabal_fp]) + > 64'(SpatzRspFifoDepth)) begin + $error({"[CC-WR-BAL %m port %0d] FIFO push-pop OVERFLOW-LEVEL ", + "push_w=%0d pop_w=%0d diff=%0d > depth=%0d (pushes lost)"}, + dbg_wabal_fp, cc_wfifo_push_n[dbg_wabal_fp], cc_wfifo_pop_n[dbg_wabal_fp], + cc_wfifo_push_n[dbg_wabal_fp] - cc_wfifo_pop_n[dbg_wabal_fp], SpatzRspFifoDepth); + end else begin + $display({"[CC-WR-BAL %m port %0d] INFO benign EOC tail push_w=%0d ", + "pop_w=%0d diff=%0d (<= depth=%0d, acks abandoned at program end)"}, + dbg_wabal_fp, cc_wfifo_push_n[dbg_wabal_fp], cc_wfifo_pop_n[dbg_wabal_fp], + cc_wfifo_push_n[dbg_wabal_fp] - cc_wfifo_pop_n[dbg_wabal_fp], SpatzRspFifoDepth); + end + end + end + end +`endif // TARGET_SYNTHESIS `endif endmodule diff --git a/hardware/src/cachepool_cluster.sv b/hardware/src/cachepool_cluster.sv index 31988ed..0f4beb8 100644 --- a/hardware/src/cachepool_cluster.sv +++ b/hardware/src/cachepool_cluster.sv @@ -107,7 +107,13 @@ module cachepool_cluster parameter int unsigned MemoryMacroLatency = 1 + RegisterTCDMCuts, /// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ - parameter int unsigned NrSramCfg = 1 + parameter int unsigned NrSramCfg = 1, + /// Folded data bank configuration (0 = auto: min(4, L1AssoPerCtrl)). + parameter bit UseFoldedDataBanks = 1'b1, + parameter int unsigned FoldWayGroup = 0, + parameter bit UseHashWaySelect = 1'b1, + /// Enable the SRAM forwarding buffer (default on; requires UseHashWaySelect). + parameter bit UseForwardingBuffer = 1'b1 ) ( /// System clock. input logic clk_i, @@ -404,7 +410,11 @@ module cachepool_cluster .RegisterExt ( RegisterExt ), .XbarLatency ( XbarLatency ), .MaxMstTrans ( MaxMstTrans ), - .MaxSlvTrans ( MaxSlvTrans ) + .MaxSlvTrans ( MaxSlvTrans ), + .UseFoldedDataBanks ( UseFoldedDataBanks ), + .FoldWayGroup ( FoldWayGroup ), + .UseHashWaySelect ( UseHashWaySelect ), + .UseForwardingBuffer ( UseForwardingBuffer ) ) i_group ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -500,7 +510,11 @@ module cachepool_cluster .RegisterExt ( RegisterExt ), .XbarLatency ( XbarLatency ), .MaxMstTrans ( MaxMstTrans ), - .MaxSlvTrans ( MaxSlvTrans ) + .MaxSlvTrans ( MaxSlvTrans ), + .UseFoldedDataBanks ( UseFoldedDataBanks ), + .FoldWayGroup ( FoldWayGroup ), + .UseHashWaySelect ( UseHashWaySelect ), + .UseForwardingBuffer ( UseForwardingBuffer ) ) i_tile ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), @@ -726,7 +740,9 @@ module cachepool_cluster ) i_reqrsp2axi ( .clk_i (clk_i ), .rst_ni (rst_ni ), - .user_i (l2_req[ch].q.user ), + // refill_user_t (UserWidth) <= AxiUserWidth (asserted below); explicit + // zero-extend to the AxiUserWidth port to keep the widths matched. + .user_i (AxiUserWidth'(l2_req[ch].q.user)), .reqrsp_req_i (l2_req[ch] ), .reqrsp_rsp_o (l2_rsp[ch] ), .axi_req_o (wide_axi_slv_req[ch] ), @@ -734,6 +750,10 @@ module cachepool_cluster ); end + // The refill user struct carried over the cache->L2 AXI must fit in the AXI + // user field; the user_i zero-extend above relies on this never truncating. + `ASSERT_INIT(CheckAxiUserFitsRefillUser, AxiUserWidth >= $bits(refill_user_t)) + // ------------- // To Main Memory diff --git a/hardware/src/cachepool_group.sv b/hardware/src/cachepool_group.sv index b14d1ac..b4d6654 100644 --- a/hardware/src/cachepool_group.sv +++ b/hardware/src/cachepool_group.sv @@ -107,7 +107,14 @@ module cachepool_group parameter int unsigned MemoryMacroLatency = 1 + RegisterTCDMCuts, /// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ - parameter int unsigned NrSramCfg = 1 + parameter int unsigned NrSramCfg = 1, + /// Folded data bank configuration (0 = auto: min(4, L1AssoPerCtrl)). + parameter bit UseFoldedDataBanks = 1'b1, + parameter int unsigned FoldWayGroup = 0, + /// Use hash-based way selection (1 way per lookup, no LRU). + parameter bit UseHashWaySelect = 1'b1, + /// Enable the SRAM forwarding buffer (default on; requires UseHashWaySelect). + parameter bit UseForwardingBuffer = 1'b1 ) ( /// System clock. input logic clk_i, @@ -266,11 +273,18 @@ module cachepool_group assign tile_remote_in_req_ready[j][t*NumRemotePortCore+r] = tile_remote_in_rsp[t][j+r*NrTCDMPortsPerCore].q_ready; // Request selection: route to target tile's remote-in slot based on - // target tile ID, so that all requests to the same destination tile - // travel through one pipeline — preserving write-before-read ordering. + // SOURCE tile ID (mod NumRemotePortCore). This is required for + // response routing to be consistent: tcdm_cache_interco routes + // responses out via (user.tile_id % NumRemotePortCore), so the + // request must land in the destination's slot indexed by the same + // value (the SOURCE tile id mod N). If we used (target % N) here + // instead, the request would arrive on slot (T%N) but the response + // would leave on slot (S%N) — different xbar mst ports — and the + // xbar's request/response pairing would break, dropping responses + // and corrupting cache state at multi-tile configs where S%N != T%N. assign remote_out_sel_xbar[j][t*NumRemotePortCore+r] = remote_xbar_sel_t'( remote_out_sel_tile[t][j+r*NrTCDMPortsPerCore] * NumRemotePortCore - + remote_out_sel_tile[t][j+r*NrTCDMPortsPerCore] % NumRemotePortCore); + + t % NumRemotePortCore); // Response selection: route back to source tile's remote-out slot. // The originator (tile_id in user field) sent on slot @@ -329,7 +343,11 @@ module cachepool_group .RegisterExt ( RegisterExt ), .XbarLatency ( XbarLatency ), .MaxMstTrans ( MaxMstTrans ), - .MaxSlvTrans ( MaxSlvTrans ) + .MaxSlvTrans ( MaxSlvTrans ), + .UseFoldedDataBanks ( UseFoldedDataBanks ), + .FoldWayGroup ( FoldWayGroup ), + .UseHashWaySelect ( UseHashWaySelect ), + .UseForwardingBuffer ( UseForwardingBuffer ) ) i_tile ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/hardware/src/cachepool_tile.sv b/hardware/src/cachepool_tile.sv index 4c7b024..fb1059d 100644 --- a/hardware/src/cachepool_tile.sv +++ b/hardware/src/cachepool_tile.sv @@ -110,7 +110,14 @@ module cachepool_tile parameter int unsigned MemoryMacroLatency = 1 + RegisterTCDMCuts, /// # SRAM Configuration rules needed: L1D Tag + L1D Data + L1D FIFO + L1I Tag + L1I Data /*** ATTENTION: `NrSramCfg` should be changed if `L1NumDataBank` and `L1NumTagBank` is changed ***/ - parameter int unsigned NrSramCfg = 1 + parameter int unsigned NrSramCfg = 1, + /// Folded data bank configuration (0 = auto: min(4, L1AssoPerCtrl)). + parameter bit UseFoldedDataBanks = 1'b1, + parameter int unsigned FoldWayGroup = 0, + /// Use hash-based way selection (1 way per lookup, no LRU). + parameter bit UseHashWaySelect = 1'b0, + /// Enable the SRAM forwarding buffer (default on; requires UseHashWaySelect). + parameter bit UseForwardingBuffer = 1'b1 ) ( /// System clock. input logic clk_i, @@ -782,6 +789,23 @@ module cachepool_tile localparam NumWordPerLine = L1LineWidth / DataWidth; localparam int unsigned WordBytes = DataWidth / 8; + localparam bit UseSkewedFolded = UseFoldedDataBanks && (L1AssoPerCtrl > 1); + localparam int unsigned DefaultFoldWayGroup = (L1AssoPerCtrl >= 4) ? 4 : 2; + localparam int unsigned EffectiveFoldWayGroup = UseSkewedFolded ? + ((FoldWayGroup == 0) ? DefaultFoldWayGroup : FoldWayGroup) : + L1AssoPerCtrl; + localparam int unsigned NumWayGroups = L1AssoPerCtrl / EffectiveFoldWayGroup; + localparam int unsigned PartSplit = UseSkewedFolded ? EffectiveFoldWayGroup : 1; + localparam int unsigned NumDataBankPerWay = NumDataBankPerCtrl / L1AssoPerCtrl; + localparam int unsigned WordsPerPart = NumWordPerLine / PartSplit; + localparam int unsigned NumDataBankPerWayGrouped = NumDataBankPerWay / WordsPerPart; + localparam int unsigned BankDataWidth = DataWidth * WordsPerPart; + localparam int unsigned BankByteCount = BankDataWidth / 8; + localparam int unsigned FoldedDataDepth = (L1CacheWayEntry / L1BankFactor) * PartSplit; + // Folded mode already shrinks request window to part-width; keep coalescer in + // equal-window mode to avoid response lane remap corner cases. + localparam int unsigned EffectiveCoalFactor = UseSkewedFolded ? 1 : L1CoalFactor; +`ifndef TARGET_SYNTHESIS initial begin $display("Cache Configuration:"); $display(" NumCtrl : %0d", NumL1CtrlTile); @@ -790,12 +814,15 @@ module cachepool_tile $display(" NumSet : %0d", L1NumSet); $display(" AssoPerCtrl : %0d", L1AssoPerCtrl); $display(" BankFactor : %0d", L1BankFactor); + $display(" PartSplit : %0d", PartSplit); + $display(" BankDataWidth : %0d", BankDataWidth); $display(" NumTagBankPerCtrl : %0d", NumTagBankPerCtrl); $display(" NumDataBankPerCtrl: %0d", NumDataBankPerCtrl); - $display(" CoalFactor : %0d", L1CoalFactor); + $display(" CoalFactor : %0d", EffectiveCoalFactor); $display(" RefillDataWidth: %0d", RefillDataWidth); $display(" DynamicOffset : %0d", dynamic_offset_q); end +`endif // CL-offset mask: bits below dynamic_offset_q, verbatim in both directions. logic [SpatzAxiAddrWidth-1:0] bitmask_lo; @@ -912,7 +939,7 @@ module cachepool_tile cachepool_cache_ctrl #( // Core .NumPorts (NrTCDMPortsPerCore ), - .CoalExtFactor (L1CoalFactor ), + .CoalExtFactor (EffectiveCoalFactor), .AddrWidth (L1AddrWidth ), .WordWidth (DataWidth ), .ByteWidth (8 ), @@ -921,6 +948,9 @@ module cachepool_tile .NumCacheEntry (L1NumEntryPerCtrl ), .CacheLineWidth (L1LineWidth ), .SetAssociativity (L1AssoPerCtrl ), + .DataPartSplit (PartSplit ), + .UseHashWaySelect (UseHashWaySelect ), + .UseForwardingBuffer (UseForwardingBuffer ), .BankFactor (L1BankFactor ), .RefillDataWidth (RefillDataWidth ), // Type @@ -1103,62 +1133,207 @@ module cachepool_tile ); end - // TODO: Should we use a single large bank or multiple narrow ones? - for (genvar bank = 0; bank < (NumDataBankPerCtrl/NumWordPerLine); - bank++) begin : gen_l1_data_banks - localparam int unsigned BaseIdx = bank * NumWordPerLine; - logic [NumWordPerLine*WordBytes-1:0] bank_be; + if (UseSkewedFolded) begin : gen_folded_data_banks + // Skewed folded banks: keep W*B macros, narrow width, deeper depth, and skew (way, part) -> column. + typedef logic [$clog2(FoldedDataDepth)-1:0] folded_bank_addr_t; + + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_req; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_we; + folded_bank_addr_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0] bank_addr; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankDataWidth-1:0] bank_wdata; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankByteCount-1:0] bank_be; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][BankDataWidth-1:0] bank_rdata; + + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_req; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_we; + folded_bank_addr_t [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0] part_addr; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0][BankDataWidth-1:0] + part_wdata; + logic [L1AssoPerCtrl-1:0][L1BankFactor-1:0][PartSplit-1:0][BankByteCount-1:0] + part_be; + + // -- Per-way, per-column write contention (loop-free) -- + // For way W and column col, "another way writes at col" is true + // iff some part P' has part_we[col][bank_sel][P'] set AND the + // (col, P') mapping belongs to a way != W. Depends ONLY on + // writes (part_we) -- safe to feed into the grant path without + // creating a combinational loop through read-side signals. + logic [L1AssoPerCtrl-1:0][L1AssoPerCtrl-1:0][L1BankFactor-1:0] any_other_write_in_col; + always_comb begin + for (int wW = 0; wW < L1AssoPerCtrl; wW++) begin + for (int col = 0; col < L1AssoPerCtrl; col++) begin + for (int bsel = 0; bsel < L1BankFactor; bsel++) begin + any_other_write_in_col[wW][col][bsel] = 1'b0; + for (int pp = 0; pp < PartSplit; pp++) begin + // Way that maps to (col, part=pp): same group, way = + // ((col - pp) mod EffectiveFoldWayGroup). + int unsigned mapped_way; + mapped_way = + (col / EffectiveFoldWayGroup) * EffectiveFoldWayGroup + + ((col - pp + EffectiveFoldWayGroup) % EffectiveFoldWayGroup); + if (mapped_way != wW) begin + any_other_write_in_col[wW][col][bsel] |= part_we[col][bsel][pp]; + end + end + end + end + end + end - for (genvar w = 0; w < NumWordPerLine; w++) begin : gen_bank_be - assign bank_be[w*WordBytes +: WordBytes] = l1_data_bank_be[cb][BaseIdx + w]; + for (genvar group = 0; group < NumWayGroups; group++) begin : gen_skew_groups + for (genvar way = 0; way < EffectiveFoldWayGroup; way++) begin : gen_skew_ways + localparam int unsigned WayIdx = group * EffectiveFoldWayGroup + way; + for (genvar part = 0; part < PartSplit; part++) begin : gen_skew_parts + localparam int unsigned ColIdx = + group * EffectiveFoldWayGroup + ((way + part) % EffectiveFoldWayGroup); + for (genvar bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin : gen_skew_banks + localparam int unsigned BankBase = bank_sel * NumWordPerLine + part * WordsPerPart; + assign part_req[ColIdx][bank_sel][part] = + |l1_data_bank_req[cb][WayIdx * NumDataBankPerWay + BankBase +: WordsPerPart]; + assign part_we[ColIdx][bank_sel][part] = + |l1_data_bank_we [cb][WayIdx * NumDataBankPerWay + BankBase +: WordsPerPart]; + assign part_addr[ColIdx][bank_sel][part] = + folded_bank_addr_t'((l1_data_bank_addr[cb][WayIdx * NumDataBankPerWay + BankBase] + * PartSplit) + part); + + for (genvar w = 0; w < WordsPerPart; w++) begin : gen_part_words + localparam int unsigned FlatIdx = WayIdx * NumDataBankPerWay + BankBase + w; + assign part_wdata[ColIdx][bank_sel][part][w*DataWidth +: DataWidth] = + l1_data_bank_wdata[cb][FlatIdx]; + assign part_be[ColIdx][bank_sel][part][w*(DataWidth/8) +: (DataWidth/8)] = + l1_data_bank_be[cb][FlatIdx]; + assign l1_data_bank_rdata[cb][FlatIdx] = + bank_rdata[ColIdx][bank_sel][w*DataWidth +: DataWidth]; + // Grant propagation. The skew-bank arbiter at (ColIdx, + // bank_sel) picks writes with write-priority over reads; + // without grant propagation a concurrent read that shares + // a column with another way's write is silently dropped + // and upstream gets stale rdata. + // - Writes always granted (gnt=1) -- writes win arbitration. + // - Reads granted iff no OTHER way writes at the same + // (col, bank_sel). We exclude our own way's writes + // to avoid spuriously blocking our way's idle words + // that happen to sit in our own write's column. + // Loop-free: depends on part_we only, no read feedback. + assign l1_data_bank_gnt[cb][FlatIdx] = + l1_data_bank_we[cb][FlatIdx] + | ~any_other_write_in_col[WayIdx][ColIdx][bank_sel]; + end + end + end + end end - tc_sram_impl #( - .NumWords (L1CacheWayEntry/L1BankFactor), - .DataWidth (L1LineWidth), - .ByteWidth (8 ), - .NumPorts (1 ), - .Latency (1 ), - .SimInit ("zeros" ) - ) i_data_bank ( - .clk_i (clk_i ), - .rst_ni (rst_ni ), - .impl_i ('0 ), - .impl_o (/* unsed */ ), - .req_i ( l1_data_bank_req [cb][BaseIdx] ), - .we_i ( l1_data_bank_we [cb][BaseIdx] ), - .addr_i ( l1_data_bank_addr [cb][BaseIdx] ), - .wdata_i( l1_data_bank_wdata[cb][BaseIdx+:NumWordPerLine]), - .be_i ( bank_be ), - .rdata_o( l1_data_bank_rdata[cb][BaseIdx+:NumWordPerLine]) - ); + always_comb begin : select_skewed_part + for (int col = 0; col < L1AssoPerCtrl; col++) begin + for (int bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin + automatic logic sel_found; + automatic int unsigned sel_part_idx; + + bank_req[col][bank_sel] = 1'b0; + bank_we[col][bank_sel] = 1'b0; + bank_addr[col][bank_sel] = '0; + bank_wdata[col][bank_sel] = '0; + bank_be[col][bank_sel] = '0; + + sel_found = 1'b0; + sel_part_idx = 0; + for (int part = 0; part < PartSplit; part++) begin + if (part_we[col][bank_sel][part] && !sel_found) begin + sel_found = 1'b1; + sel_part_idx = part; + end + end + if (!sel_found) begin + for (int part = 0; part < PartSplit; part++) begin + if (part_req[col][bank_sel][part] && !sel_found) begin + sel_found = 1'b1; + sel_part_idx = part; + end + end + end + + if (sel_found) begin + bank_req[col][bank_sel] = 1'b1; + bank_we[col][bank_sel] = part_we[col][bank_sel][sel_part_idx]; + bank_addr[col][bank_sel] = part_addr[col][bank_sel][sel_part_idx]; + bank_wdata[col][bank_sel] = part_wdata[col][bank_sel][sel_part_idx]; + bank_be[col][bank_sel] = part_be[col][bank_sel][sel_part_idx]; + end + end + end + end - assign l1_data_bank_gnt[cb][BaseIdx+:NumWordPerLine] = {NumWordPerLine{1'b1}}; - end + for (genvar col = 0; col < L1AssoPerCtrl; col++) begin : gen_skew_cols + for (genvar bank_sel = 0; bank_sel < L1BankFactor; bank_sel++) begin : gen_skew_col_banks + tc_sram_impl #( + .NumWords (FoldedDataDepth), + .DataWidth (BankDataWidth), + .ByteWidth (8), + .NumPorts (1), + .Latency (1), + .SimInit ("zeros") + ) i_data_bank ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .impl_i ('0 ), + .impl_o (/* unused */), + .req_i (bank_req[col][bank_sel]), + .we_i (bank_we[col][bank_sel]), + .addr_i (bank_addr[col][bank_sel]), + .wdata_i(bank_wdata[col][bank_sel]), + .be_i (bank_be[col][bank_sel]), + .rdata_o(bank_rdata[col][bank_sel]) + ); + end + end + end else begin : gen_unfolded_data_banks + // Unfolded banks: each SRAM stores a full cacheline per way/bank factor. + for (genvar bank = 0; bank < NumDataBankPerWayGrouped; bank++) begin : gen_l1_data_banks + for (genvar way = 0; way < L1AssoPerCtrl; way++) begin : gen_way_banks + logic bank_req; + logic bank_we; + tcdm_bank_addr_t bank_addr; + logic [BankDataWidth-1:0] bank_wdata; + logic [BankByteCount-1:0] bank_be; + logic [BankDataWidth-1:0] bank_rdata; + + assign bank_req = + |l1_data_bank_req[cb][way*NumDataBankPerWay + bank*WordsPerPart +: WordsPerPart]; + assign bank_we = + |l1_data_bank_we [cb][way*NumDataBankPerWay + bank*WordsPerPart +: WordsPerPart]; + assign bank_addr = l1_data_bank_addr[cb][way*NumDataBankPerWay + bank*WordsPerPart]; + + for (genvar g = 0; g < WordsPerPart; g++) begin : gen_group_words + localparam int unsigned FlatIdx = way * NumDataBankPerWay + bank * WordsPerPart + g; + assign bank_wdata[g*DataWidth +: DataWidth] = l1_data_bank_wdata[cb][FlatIdx]; + assign bank_be[g*(DataWidth/8) +: (DataWidth/8)] = l1_data_bank_be[cb][FlatIdx]; + assign l1_data_bank_rdata[cb][FlatIdx] = bank_rdata[g*DataWidth +: DataWidth]; + assign l1_data_bank_gnt[cb][FlatIdx] = 1'b1; + end - // for (genvar j = 0; j < NumDataBankPerCtrl; j++) begin : gen_l1_data_banks - // tc_sram_impl #( - // .NumWords (L1CacheWayEntry/L1BankFactor), - // .DataWidth (DataWidth), - // .ByteWidth (DataWidth), - // .NumPorts (1), - // .Latency (1), - // .SimInit ("zeros") - // ) i_data_bank ( - // .clk_i (clk_i ), - // .rst_ni (rst_ni ), - // .impl_i ('0 ), - // .impl_o (/* unsed */ ), - // .req_i (l1_data_bank_req [cb][j]), - // .we_i (l1_data_bank_we [cb][j]), - // .addr_i (l1_data_bank_addr [cb][j]), - // .wdata_i(l1_data_bank_wdata[cb][j]), - // .be_i (l1_data_bank_be [cb][j]), - // .rdata_o(l1_data_bank_rdata[cb][j]) - // ); - - // assign l1_data_bank_gnt[cb][j] = 1'b1; - // end + tc_sram_impl #( + .NumWords (L1CacheWayEntry/L1BankFactor), + .DataWidth (BankDataWidth), + .ByteWidth (8), + .NumPorts (1), + .Latency (1), + .SimInit ("zeros") + ) i_data_bank ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .impl_i ('0 ), + .impl_o (/* unused */), + .req_i (bank_req ), + .we_i (bank_we ), + .addr_i (bank_addr ), + .wdata_i(bank_wdata ), + .be_i (bank_be ), + .rdata_o(bank_rdata ) + ); + end + end + end end hive_req_t [NrCores-1:0] hive_req; @@ -1511,9 +1686,13 @@ module cachepool_tile // Sanity check the parameters. Not every configuration makes sense. `ASSERT_INIT(CheckSuperBankSanity, NrBanks >= BanksPerSuperBank); `ASSERT_INIT(CheckSuperBankFactor, (NrBanks % BanksPerSuperBank) == 0); + `ASSERT_INIT(CheckFoldWayGroup, (EffectiveFoldWayGroup > 0) && + ((L1AssoPerCtrl % EffectiveFoldWayGroup) == 0)); + `ASSERT_INIT(CheckLineSplit, (NumWordPerLine % PartSplit) == 0); // Check that the cluster base address aligns to the TCDMSize. `ASSERT(ClusterBaseAddrAlign, ((TCDMSize - 1) & cluster_base_addr_i) == 0) // Make sure we only have one DMA in the system. `ASSERT_INIT(NumberDMA, $onehot0(Xdma)) + endmodule diff --git a/hardware/src/tcdm_cache_interco.sv b/hardware/src/tcdm_cache_interco.sv index ba49e11..2f723ac 100644 --- a/hardware/src/tcdm_cache_interco.sv +++ b/hardware/src/tcdm_cache_interco.sv @@ -433,4 +433,104 @@ module tcdm_cache_interco #( assign mem_rsp_ready_o = mem_rsp_ready; +`ifndef TARGET_SYNTHESIS + // Probe D: targeted addr watcher inside the cluster xbar. + // Off by default; enable with +xbar_write_watch plusarg. + bit xbar_write_watch_en = 1'b0; + // verilog_lint: waive plusarg-assignment + initial xbar_write_watch_en = $test$plusargs("xbar_write_watch"); + + // Loop indices hoisted out of always blocks (debug-only). + int unsigned dbg_xwwatch_p; + int unsigned dbg_sb_o; + int unsigned dbg_sb_c; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (rst_ni && xbar_write_watch_en) begin + for (dbg_xwwatch_p = 0; dbg_xwwatch_p < NumCache + NumRemotePort; dbg_xwwatch_p++) begin + if (mem_req_valid[dbg_xwwatch_p] && mem_req_ready[dbg_xwwatch_p] && + mem_req[dbg_xwwatch_p].write) begin + if (mem_req[dbg_xwwatch_p].addr == 32'ha0001308 || + mem_req[dbg_xwwatch_p].addr == 32'ha0001700 || + mem_req[dbg_xwwatch_p].addr == 32'ha0001730) begin + $display({"[XBAR-WRITE-WATCH %0t %m port %0d] orig_addr=0x%08h ", + "post_rot=0x%08h is_remote=%0b data=0x%08h strb=0x%h ", + "user_tile=%0d user_core=%0d user_req=0x%h"}, + $time, dbg_xwwatch_p, mem_req[dbg_xwwatch_p].addr, + mem_req_o[dbg_xwwatch_p].q.addr, + (dbg_xwwatch_p >= NumCache), + mem_req[dbg_xwwatch_p].data, mem_req[dbg_xwwatch_p].strb, + mem_req[dbg_xwwatch_p].user.tile_id, mem_req[dbg_xwwatch_p].user.core_id, + mem_req[dbg_xwwatch_p].user.req_id); + end + end + end + end + end + + // Debug scoreboard: track outstanding requests per (output-bank, input-core) + // and validate that each response targets a core with outstanding traffic. + logic [NumCache+NumRemotePort-1:0][NumCores+NumRemotePort-1:0][31:0] outstanding_q; + logic signed [NumCache+NumRemotePort-1:0][NumCores+NumRemotePort-1:0][31:0] delta_d; + logic [NumCache+NumRemotePort-1:0][NumCores+NumRemotePort-1:0][31:0] outstanding_n; + // delta_d/outstanding_n are same-cycle combinational scratch in this debug-only + // accumulator; blocking '=' on them is intentional (non-blocking would break the + // read-after-write accumulate). Declared at module scope per house rule, so the + // always-ff-non-blocking rule is waived rather than satisfied via in-block locals. + // verilog_lint: waive-start always-ff-non-blocking + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + outstanding_q <= '0; + end else begin + // Start from previous occupancy. + delta_d = '0; + + // Account accepted requests (+1). + for (dbg_sb_c = 0; dbg_sb_c < NumCores + NumRemotePort; dbg_sb_c++) begin + if (core_req_valid[dbg_sb_c] && core_req_ready[dbg_sb_c]) begin + delta_d[core_req_sel[dbg_sb_c]][dbg_sb_c] = + delta_d[core_req_sel[dbg_sb_c]][dbg_sb_c] + 32'sd1; + end + end + + // Account accepted responses (-1), allowing same-cycle req/rsp for same + // (output, core) pair without false mismatch reports. + for (dbg_sb_o = 0; dbg_sb_o < NumCache + NumRemotePort; dbg_sb_o++) begin + if (mem_rsp_valid[dbg_sb_o] && mem_rsp_ready[dbg_sb_o]) begin + if (mem_rsp_sel[dbg_sb_o] >= (NumCores + NumRemotePort)) begin + $error("[tcdm_cache_interco] Invalid mem_rsp_sel=%0d on output %0d", + mem_rsp_sel[dbg_sb_o], dbg_sb_o); + end else if (($signed(outstanding_q[dbg_sb_o][mem_rsp_sel[dbg_sb_o]]) + + delta_d[dbg_sb_o][mem_rsp_sel[dbg_sb_o]]) == 0) begin + $error({"[tcdm_cache_interco] Response without outstanding req ", + "on output %0d -> core %0d"}, + dbg_sb_o, mem_rsp_sel[dbg_sb_o]); + end else begin + delta_d[dbg_sb_o][mem_rsp_sel[dbg_sb_o]] = + delta_d[dbg_sb_o][mem_rsp_sel[dbg_sb_o]] - 32'sd1; + end + end + end + + // Commit updated outstanding counters. + for (dbg_sb_o = 0; dbg_sb_o < NumCache + NumRemotePort; dbg_sb_o++) begin + for (dbg_sb_c = 0; dbg_sb_c < NumCores + NumRemotePort; dbg_sb_c++) begin + outstanding_n[dbg_sb_o][dbg_sb_c] = + outstanding_q[dbg_sb_o][dbg_sb_c] + delta_d[dbg_sb_o][dbg_sb_c]; + if (outstanding_n[dbg_sb_o][dbg_sb_c][31]) begin + // Should never go negative. + $error("[tcdm_cache_interco] Outstanding underflow on output %0d core %0d", + dbg_sb_o, dbg_sb_c); + outstanding_q[dbg_sb_o][dbg_sb_c] <= '0; + end else begin + outstanding_q[dbg_sb_o][dbg_sb_c] <= outstanding_n[dbg_sb_o][dbg_sb_c]; + end + end + end + end + end + // verilog_lint: waive-stop always-ff-non-blocking +`endif + + endmodule diff --git a/hardware/src/verif/cachepool_tile_tcdm_checker.sv b/hardware/src/verif/cachepool_tile_tcdm_checker.sv new file mode 100644 index 0000000..c69f59c --- /dev/null +++ b/hardware/src/verif/cachepool_tile_tcdm_checker.sv @@ -0,0 +1,276 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Zexin Fu, ETH Zurich +// +// ============================================================================= +// cachepool_tile_tcdm_checker +// ============================================================================= +// Sim-only verification IP for the per-tile core-side TCDM bus, factored out of +// cachepool_tile.sv (PR review: keep verification code in its own file) and +// `bind`-attached to every cachepool_tile instance. Two passive monitors, both +// drive nothing: +// +// 1. Pre-strip request TRACER -- logs every accepted tcdm_req in an address +// window [+sb_pretrace_addr_lo, +sb_pretrace_addr_hi] so the originating +// (core, port) of a request the L1 scoreboard later sees post-strip can be +// identified. +// +// 2. Per-port TCDM Memory-Model VIP -- a byte-granular shadow of TCDM-visible +// memory built from every accepted write, checked against every read +// response. Enabled with +mm_enable=1. +// +// The whole file is guarded by `ifndef TARGET_SYNTHESIS so synthesis/lint never +// see it. The trailing `bind` wires the monitor to the tile's internal +// tcdm_req / tcdm_rsp arrays. +// ============================================================================= + +`ifndef TARGET_SYNTHESIS +module cachepool_tile_tcdm_checker + import cachepool_pkg::*; +#( + parameter int unsigned NrTCDMPortsCores = 0, + parameter int unsigned NrTCDMPortsPerCore = 0 +) ( + input logic clk_i, + input logic rst_ni, + input tcdm_req_t [NrTCDMPortsCores-1:0] tcdm_req, + input tcdm_rsp_t [NrTCDMPortsCores-1:0] tcdm_rsp +); + + // --------------------------------------------------------------------- + // Verification: per-port pre-strip request tracer. + // Logs every accepted tcdm_req[k] whose addr lies in + // [+sb_pretrace_addr_lo, +sb_pretrace_addr_hi] (inclusive). + // Identifies the originating (core, port) for the request that the + // L1 cache scoreboard will later see post-strip. All output is via + // `$display`; no signal is driven. + // --------------------------------------------------------------------- + longint unsigned tracer_addr_lo = '1; + longint unsigned tracer_addr_hi = '0; + initial begin + void'($value$plusargs("sb_pretrace_addr_lo=%h", tracer_addr_lo)); + void'($value$plusargs("sb_pretrace_addr_hi=%h", tracer_addr_hi)); + if (tracer_addr_lo != '1 || tracer_addr_hi != '0) begin + $display("[TRACER %m] tracing pre-strip TCDM reqs in 0x%0h..0x%0h", + tracer_addr_lo, tracer_addr_hi); + end + end + + // Stateless monitor (drives nothing); rst_ni is in the sensitivity list per + // house style, used only to suppress tracing during reset. + always_ff @(posedge clk_i or negedge rst_ni) begin + if (rst_ni && (tracer_addr_lo != '1 || tracer_addr_hi != '0)) begin + for (int k = 0; k < NrTCDMPortsCores; k++) begin + if (tcdm_req[k].q_valid && tcdm_rsp[k].q_ready) begin + automatic logic [31:0] a = tcdm_req[k].q.addr; + if (a >= tracer_addr_lo[31:0] && a <= tracer_addr_hi[31:0]) begin + $display({"[TRACER %m] t=%0t core=%0d port=%0d addr=0x%0h %s ", + "data=0x%0h strb=0x%0h user=0x%0h"}, + $time, k / NrTCDMPortsPerCore, k % NrTCDMPortsPerCore, + a, + tcdm_req[k].q.write ? "WRITE" : "READ ", + tcdm_req[k].q.data, tcdm_req[k].q.strb, tcdm_req[k].q.user); + end + end + end + end + end + + // --------------------------------------------------------------------- + // Verification: per-port TCDM Memory Model (VIP C1). + // + // Maintains a byte-granular shadow of TCDM-visible memory built from + // EVERY accepted write request, then verifies EVERY read response + // matches. Catches any class of bug where: + // - a store doesn't update the cache (data lost), + // - a load returns stale data inconsistent with prior writes, + // - a store update gets clobbered by an unrelated refill / aliasing, + // ... independent of where the cache is internally hit/missing/evicting. + // + // Per-port outstanding-request FIFOs maintain rsp ordering: every + // accepted upstream req pushes an entry; every rsp pops one and + // compares (for reads) or skips (for writes). + // + // LIMITATION: bytes NEVER written via TCDM are skipped (we don't know + // their DRAM-initialised value). Use combined with the wrapper-level + // SB (which checks against cache's stored data) for full coverage. + // --------------------------------------------------------------------- + typedef struct { + logic is_write; + logic [31:0] addr; + logic [31:0] expected_data; + logic [3:0] expected_mask; // 1 = byte was tracked (and must match) + } mm_outstanding_t; + + mm_outstanding_t mm_q [NrTCDMPortsCores][$]; + byte unsigned mm_mem [longint unsigned]; + + longint unsigned mm_writes_seen = 0; + longint unsigned mm_reads_seen = 0; + longint unsigned mm_rsps_seen = 0; + longint unsigned mm_data_mismatch = 0; + longint unsigned mm_orphan_rsp = 0; // rsp w/o matching req + longint unsigned mm_type_mismatch = 0; // rsp.write != req.write + longint unsigned mm_bytes_checked = 0; + longint unsigned mm_bytes_unknown = 0; + + // Enable/disable via plusarg; off by default to keep the rest of the + // checks fast for kernels that haven't been characterised yet. + bit mm_enable = 1'b0; + + initial begin + void'($value$plusargs("mm_enable=%d", mm_enable)); + if (mm_enable) + $display("[MM %m] Memory Model enabled."); + end + + // Shadow-memory checker. + // + // This is a passive verification scoreboard, NOT synthesizable sequential + // logic, so it uses a plain clocked `always` (not `always_ff`) with BLOCKING + // assignments -- the standard idiom for SV scoreboards (cf. UVM). Both are + // required here, not stylistic: + // * No flip-flop is modelled. There is no `q <= d` next-state register; + // every target is either a SystemVerilog queue / associative array or a + // plain counter. `always_ff` advertises "I am a flop" to lint/synthesis, + // which is false for this block -- so `always @(posedge clk_i)` is the + // honest, waiver-free keyword. + // * Queue / assoc-array updates have no non-blocking form: `mm_q[k] + // .push_back()/.pop_front()/.delete()` and `mm_mem[a]=d` are procedural + // method calls / element writes, evaluated in order within the edge. + // * Counters are read-modify-written MULTIPLE times per edge: e.g. the + // byte loop can hit `mm_bytes_checked++`/`mm_data_mismatch++` up to 4x + // per response, across all ports. With non-blocking `<=`, every `++` in + // the same time step reads the SAME pre-edge value and resolves to + // old+1, so all but one increment is lost. Blocking `=` accumulates + // correctly (old -> old+1 -> old+2 ...). + // * The per-iteration scratch `e` is filled and consumed (`push_back(e)`) + // in the same iteration; NBA would queue a stale `e`. + // Reset just clears the shadow state; no registered output is driven. + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + // Clear shadow state on reset (counters re-zero; pending FIFOs flushed). + mm_writes_seen = 0; + mm_reads_seen = 0; + mm_rsps_seen = 0; + mm_data_mismatch = 0; + mm_orphan_rsp = 0; + mm_type_mismatch = 0; + mm_bytes_checked = 0; + mm_bytes_unknown = 0; + for (int k = 0; k < NrTCDMPortsCores; k++) mm_q[k].delete(); + end else if (mm_enable) begin + // -- Req side: update mem_model on writes, snapshot expected on reads -- + // The TCDM bus carries a 32-bit data word; req.addr may be byte- + // unaligned but strb[i] / data[i*8+:8] always refers to byte i of + // the WORD at (addr & ~3). Word-align before indexing. + for (int k = 0; k < NrTCDMPortsCores; k++) begin + if (tcdm_req[k].q_valid && tcdm_rsp[k].q_ready) begin + automatic logic [31:0] a_word = tcdm_req[k].q.addr & 32'hFFFFFFFC; + automatic mm_outstanding_t e; + e.is_write = tcdm_req[k].q.write; + e.addr = a_word; + e.expected_data = '0; + e.expected_mask = '0; + if (tcdm_req[k].q.write) begin + for (int b = 0; b < 4; b++) begin + if (tcdm_req[k].q.strb[b]) begin + mm_mem[a_word + b] = tcdm_req[k].q.data[b*8 +: 8]; + end + end + mm_writes_seen++; + end else begin + // Snapshot bytes the model has tracked. Reads ignore strb on + // most TCDM masters -- the full word is returned and the core + // extracts the requested byte. + for (int b = 0; b < 4; b++) begin + if (mm_mem.exists(a_word + b)) begin + e.expected_data[b*8 +: 8] = mm_mem[a_word + b]; + e.expected_mask[b] = 1'b1; + end + end + mm_reads_seen++; + end + mm_q[k].push_back(e); + end + end + // -- Rsp side: pop & compare -- + for (int k = 0; k < NrTCDMPortsCores; k++) begin + if (tcdm_rsp[k].p_valid) begin + mm_rsps_seen++; + if (mm_q[k].size() == 0) begin + mm_orphan_rsp++; + $error({"[MM %m port=%0d] ORPHAN_RSP t=%0t rsp_data=0x%0h ", + "write=%0b (no outstanding req in FIFO)"}, + k, $time, tcdm_rsp[k].p.data, tcdm_rsp[k].p.write); + end else begin + automatic mm_outstanding_t e = mm_q[k].pop_front(); + if (e.is_write != tcdm_rsp[k].p.write) begin + mm_type_mismatch++; + $error({"[MM %m port=%0d] TYPE_MISMATCH t=%0t addr=0x%0h ", + "req_was_write=%0b rsp.write=%0b"}, + k, $time, e.addr, e.is_write, tcdm_rsp[k].p.write); + end else if (!e.is_write) begin + // Read response: compare per byte + for (int b = 0; b < 4; b++) begin + if (e.expected_mask[b]) begin + mm_bytes_checked++; + if (tcdm_rsp[k].p.data[b*8 +: 8] !== e.expected_data[b*8 +: 8]) begin + mm_data_mismatch++; + $error({"[MM %m port=%0d] DATA_MISMATCH t=%0t addr=0x%0h ", + "byte=%0d expected=0x%02h got=0x%02h"}, + k, $time, e.addr, b, + e.expected_data[b*8 +: 8], + tcdm_rsp[k].p.data[b*8 +: 8]); + end + end else begin + mm_bytes_unknown++; + end + end + end + end + end + end + end + end + + final begin + if (mm_enable) begin + $display({"[MM %m] ============================ Memory-Model Summary ", + "============================"}); + $display("[MM %m] Writes seen : %0d", mm_writes_seen); + $display("[MM %m] Reads seen : %0d", mm_reads_seen); + $display("[MM %m] Rsps seen : %0d", mm_rsps_seen); + $display("[MM %m] Bytes checked : %0d", mm_bytes_checked); + $display({"[MM %m] Bytes unknown : %0d ", + "(read addrs never previously written via TCDM)"}, mm_bytes_unknown); + $display("[MM %m] Data mismatches : %0d", mm_data_mismatch); + $display("[MM %m] Type mismatches : %0d", mm_type_mismatch); + $display("[MM %m] Orphan rsps : %0d", mm_orphan_rsp); + if (mm_data_mismatch == 0 && mm_type_mismatch == 0 && mm_orphan_rsp == 0) + $display("[MM %m] STATUS: PASS"); + else + $display("[MM %m] STATUS: FAIL (%0d violations)", + mm_data_mismatch + mm_type_mismatch + mm_orphan_rsp); + $display({"[MM %m] ========================================", + "======================================="}); + end + end + +endmodule + +// Attach the checker to every cachepool_tile instance. The bound instance +// lives in the tile's scope, so its ports bind directly to the tile's internal +// tcdm_req / tcdm_rsp arrays and the NrTCDMPorts* localparams. +bind cachepool_tile cachepool_tile_tcdm_checker #( + .NrTCDMPortsCores (NrTCDMPortsCores ), + .NrTCDMPortsPerCore(NrTCDMPortsPerCore) +) i_tcdm_checker ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + .tcdm_req(tcdm_req), + .tcdm_rsp(tcdm_rsp) +); +`endif diff --git a/hardware/tb/cachepool_cluster_wrapper.sv b/hardware/tb/cachepool_cluster_wrapper.sv index a9dba20..dbba3d2 100644 --- a/hardware/tb/cachepool_cluster_wrapper.sv +++ b/hardware/tb/cachepool_cluster_wrapper.sv @@ -18,6 +18,13 @@ module cachepool_cluster_wrapper parameter int unsigned AxiUserWidth = SpatzAxiUserWidth, parameter int unsigned AxiInIdWidth = SpatzAxiIdInWidth, parameter int unsigned AxiOutIdWidth = SpatzAxiIdOutWidth, + // L1 data-bank / way-select / forwarding-buffer knobs. Defaulted from the + // config macros (set in config/*.mk -> Makefile VLOG_DEFS); fall back to the + // production combination (folded + hash + fwd-buffer) when a macro is unset. + parameter bit UseFoldedDataBanks = `ifdef L1D_USE_FOLDED `L1D_USE_FOLDED `else 1'b1 `endif, + parameter int unsigned FoldWayGroup = `ifdef L1D_FOLD_WAY_GROUP `L1D_FOLD_WAY_GROUP `else 0 `endif, + parameter bit UseHashWaySelect = `ifdef L1D_USE_HASH_WAY `L1D_USE_HASH_WAY `else 1'b1 `endif, + parameter bit UseForwardingBuffer = `ifdef L1D_USE_FWD_BUF `L1D_USE_FWD_BUF `else 1'b1 `endif, parameter type axi_in_resp_t = spatz_axi_in_resp_t, parameter type axi_in_req_t = spatz_axi_in_req_t, @@ -90,7 +97,11 @@ module cachepool_cluster_wrapper .RegisterExt (1 ), .XbarLatency (axi_pkg::CUT_ALL_PORTS ), .MaxMstTrans (NumAxiMaxTrans ), - .MaxSlvTrans (NumAxiMaxTrans ) + .MaxSlvTrans (NumAxiMaxTrans ), + .UseFoldedDataBanks (UseFoldedDataBanks ), + .FoldWayGroup (FoldWayGroup ), + .UseHashWaySelect (UseHashWaySelect ), + .UseForwardingBuffer (UseForwardingBuffer ) ) i_cluster ( .clk_i , .rst_ni , diff --git a/software/snRuntime/src/l1cache.c b/software/snRuntime/src/l1cache.c index 79700d1..b761d92 100644 --- a/software/snRuntime/src/l1cache.c +++ b/software/snRuntime/src/l1cache.c @@ -20,6 +20,8 @@ void l1d_xbar_config(uint32_t offset) { (uint32_t *)(_snrt_team_current->root->cluster_mem.end + CACHEPOOL_PERIPHERAL_XBAR_OFFSET_REG_OFFSET); *cfg = offset; + l1d_flush(); + l1d_wait(); l1d_xbar_commit(); } diff --git a/software/tests/CMakeLists.txt b/software/tests/CMakeLists.txt index c090359..c8f47d8 100644 --- a/software/tests/CMakeLists.txt +++ b/software/tests/CMakeLists.txt @@ -86,6 +86,16 @@ set(SNITCH_TEST_PREFIX cachepool-) add_spatz_test_zeroParam(spin-lock spin-lock/main.c) add_spatz_test_zeroParam(mcs-lock mcs-lock/main.c) add_spatz_test_zeroParam(byte-enable byte-enable/main.c) +add_spatz_test_zeroParam(cache-line-rw-smoke cache-line-rw-smoke/main.c) +add_spatz_test_zeroParam(minimal-tile0-repro minimal-tile0-repro/main.c) +add_spatz_test_zeroParam(cache-test-scalar cache-test-scalar/main.c) +add_spatz_test_zeroParam(cache-test-vector cache-test-vector/main.c) +add_spatz_test_zeroParam(cache-mix-smoke cache-mix-smoke/main.c) +add_spatz_test_zeroParam(cache-mix-pressure cache-mix-pressure/main.c) +add_spatz_test_zeroParam(cache-rlc-mimic cache-rlc-mimic/main.c) +add_spatz_test_zeroParam(cache-vector-rw cache-vector-rw/main.c) +add_spatz_test_zeroParam(cache-coverage cache-coverage/main.c) +add_spatz_test_zeroParam(cache-coverage-min cache-coverage-min/main.c) # add_snitch_test(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c) # add_spatz_test_threeParam(multi_producer_single_consumer_double_linked_list multi_producer_single_consumer_double_linked_list/main.c 1 1350 1000) @@ -115,6 +125,7 @@ add_spatz_test_threeParam(fmatmul-32b fmatmul-32b/main.c 64 64 64) add_spatz_test_threeParam(fmatmul-32b fmatmul-32b/main.c 128 128 128) add_spatz_test_twoParam(fft-32b fft-32b/main.c 256 4) +add_spatz_test_twoParam(fft-32b fft-32b/main.c 1024 4) add_spatz_test_twoParam(fft-32b fft-32b/main.c 1024 16) ### Integer-Point diff --git a/software/tests/cache-coverage-min/main.c b/software/tests/cache-coverage-min/main.c new file mode 100644 index 0000000..c596a73 --- /dev/null +++ b/software/tests/cache-coverage-min/main.c @@ -0,0 +1,68 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// +// cache-coverage-min: minimal repro for the phase-06 writeback-loss bug. +// Single core, no warm-up. Just hammers the same cache set with 8 +// stride-64KiB addresses (all hashing to depth=0, ctrl=0) so the VIP +// trace can capture the exact COMMIT / UPREQ sequence without burying +// it in 10s of µs of unrelated traffic. + +#include +#include +#include +#include "printf.h" + +#define CONFLICT_STRIDE_LOG2 16U +#define CONFLICT_STRIDE (1U << CONFLICT_STRIDE_LOG2) +#define CONFLICT_LINES 8U +#define CONFLICT_BYTES (CONFLICT_LINES * CONFLICT_STRIDE) + +static uint8_t conflict_buf[CONFLICT_BYTES] + __attribute__((section(".dram"))) __attribute__((aligned(CONFLICT_STRIDE))); + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + if (cid == 0) { + + // Minimal cache setup: line-interleave (offset=6). + l1d_flush(); + l1d_wait(); + l1d_xbar_config(31 - __builtin_clz(64)); // offset = 6 + l1d_init(0); + l1d_wait(); + printf("[cache-coverage-min] setup done. conflict_buf@0x%x\n", + (uint32_t)conflict_buf); + + volatile uint32_t *p[CONFLICT_LINES]; + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) + p[k] = (volatile uint32_t *)(conflict_buf + (k * CONFLICT_STRIDE)); + + // -- Round 1: write k=0..7, then read all back. + printf("[cache-coverage-min] WRITE round 1\n"); + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) { + start_kernel(); + *(p[k]) = 0xC0FFEE00u + k; + stop_kernel(); + } + + printf("[cache-coverage-min] READ round 1\n"); + uint32_t errs = 0; + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) { + start_kernel(); + uint32_t got = *(p[k]); + uint32_t exp = 0xC0FFEE00u + k; + stop_kernel(); + if (got != exp) { + printf(" [ERR] k=%u addr=0x%x exp=0x%x got=0x%x\n", + k, (uint32_t)p[k], exp, got); + ++errs; + } else { + printf(" [OK ] k=%u addr=0x%x got=0x%x\n", k, (uint32_t)p[k], got); + } + } + printf("[cache-coverage-min] round1 errors=%u\n", errs); + printf("[cache-coverage-min] %s\n", errs ? "FAIL" : "PASS"); + } + snrt_cluster_hw_barrier(); + return 0; +} diff --git a/software/tests/cache-coverage/main.c b/software/tests/cache-coverage/main.c new file mode 100644 index 0000000..d639092 --- /dev/null +++ b/software/tests/cache-coverage/main.c @@ -0,0 +1,512 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// +// cache-coverage: multi-core, multi-phase cache verification kernel. +// +// EVERY phase that doesn't intrinsically need a single core runs on +// ALL 4 cores in parallel. Each core works on its own per-core slice +// (no cross-slice corruption is also a property we check), and the +// verification VIP (SB + Memory Model) checks correctness end-to-end. +// +// Phases: +// 00 setup core 0 only (l1d_flush + xbar_config + l1d_init) +// 01 cold+hit all cores (each owns 1/4 of working set) +// 02 partial-bytes all cores (each owns its own 64-byte scratch line) +// 03 eviction all cores (each evicts its slice via reverse-walk) +// 04 multicore RAW all cores (each writes, all cores read) +// 05 vector all cores (each Spatz does vle+vse on its slice) +// 06 set-conflict core 0 (8 same-set tags, 4 ways → forced evict) +// 07 random LFSR all cores (each core has own seed + own slice) +// 08 AMO atomicity all cores (4×AMO_ITER amoadds to shared counter) +// 09 ping-pong all cores (each ping-pongs on its own line) +// 10 cross-core RAW all cores (each writes, neighbor reads + verifies) +// 11 shared-set all cores (4 cores hit same set/depth) +// 12 producer chain all cores (c0 writes → c1 reads+writes → ... → c3 verifies) + +#include +#include +#include +#include "printf.h" + +#define MAX_CORES 4U +#define LINE_BYTES 64U +#define WORD_BYTES 4U +#define WORDS_PER_LINE (LINE_BYTES / WORD_BYTES) + +// 768 cache lines × 64 B = 48 KiB working set (= 3× per-way footprint). +#define NUM_LINES 768U +#define TOTAL_WORDS (NUM_LINES * WORDS_PER_LINE) + +// Phase 06: set-conflict (single core) +#define CONFLICT_STRIDE_LOG2 16U // 64 KiB upstream stride → same set +#define CONFLICT_STRIDE (1U << CONFLICT_STRIDE_LOG2) +#define CONFLICT_LINES 8U +#define CONFLICT_BYTES (CONFLICT_LINES * CONFLICT_STRIDE) + +// Phase 11: shared-set (multi-core). Each core picks 4 stride-64KiB lines +// all hashing to the SAME set; 4 cores × 4 ways = 16 lines on one set, +// forces continuous eviction churn under multi-core contention. +#define SHARED_CONFLICT_LINES_PER_CORE 4U +#define SHARED_CONFLICT_TOTAL_LINES (SHARED_CONFLICT_LINES_PER_CORE * MAX_CORES) +#define SHARED_CONFLICT_BYTES (SHARED_CONFLICT_TOTAL_LINES * CONFLICT_STRIDE) + +// Per-core / per-phase tunables +#define AMO_ITER 512U +#define PINGPONG_ITER 256U +#define LFSR_ITER 512U + +static uint32_t buf [TOTAL_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(LINE_BYTES))); + +static uint32_t core_errors [MAX_CORES] __attribute__((section(".dram"))); + +// One per-core 64-byte scratch line for phase 02. +static uint8_t scratch [MAX_CORES][LINE_BYTES] + __attribute__((section(".dram"))) __attribute__((aligned(LINE_BYTES))); + +// Set-conflict (phase 06, single core). +static uint8_t conflict_buf [CONFLICT_BYTES] + __attribute__((section(".dram"))) __attribute__((aligned(CONFLICT_STRIDE))); + +// Multi-core shared-set contention buffer (phase 11). +static uint8_t shared_conflict_buf [SHARED_CONFLICT_BYTES] + __attribute__((section(".dram"))) __attribute__((aligned(CONFLICT_STRIDE))); + +// Shared counter for phase 08 (AMO multi-core). +static volatile uint32_t amo_counter + __attribute__((section(".dram"))) __attribute__((aligned(LINE_BYTES))) = 0; + +// Per-phase per-core error aggregation. Each core stores its result; +// core 0 prints a summary line after the barrier. +#define N_PHASES 13 +static volatile uint32_t phase_errs [N_PHASES][MAX_CORES] + __attribute__((section(".dram"))) __attribute__((aligned(LINE_BYTES))); + +static inline uint32_t pattern(uint32_t idx) { + return (idx * 0x01010101u) ^ 0xA5A5A5A5u; +} + +static inline uint32_t core_tag(uint32_t cid) { + return cid * 0x11111111u; +} + +// Forward decls. +static uint32_t phase_01_cold_then_hit(volatile uint32_t *p, uint32_t base, uint32_t chunk); +static uint32_t phase_02_partial_bytes(volatile uint8_t *p); +static uint32_t phase_03_eviction (volatile uint32_t *p, uint32_t base, uint32_t chunk); +static uint32_t phase_04_multicore (volatile uint32_t *p, uint32_t n, uint32_t cid); +static uint32_t phase_05_vector_rw (volatile uint32_t *p, uint32_t base, uint32_t chunk); +static uint32_t phase_06_set_conflict (volatile uint8_t *base); +static uint32_t phase_07_random_lfsr (volatile uint32_t *p, uint32_t base, uint32_t chunk, uint32_t cid); +static uint32_t phase_08_amo_multicore(uint32_t cid); +static uint32_t phase_09_pingpong (volatile uint32_t *p, uint32_t addr); +static uint32_t phase_10_cross_core_raw(volatile uint32_t *p, uint32_t n, uint32_t cid); +static uint32_t phase_11_shared_set (volatile uint8_t *base, uint32_t cid); +static uint32_t phase_12_producer_chain(volatile uint32_t *p, uint32_t base, uint32_t chunk, uint32_t cid); + +static inline void summary(uint32_t cid, uint32_t phase, const char *name) { + // Called by core 0 after the barrier to print per-core counts. + if (cid != 0) return; + uint32_t total = 0; + for (uint32_t c = 0; c < MAX_CORES; ++c) total += phase_errs[phase][c]; + printf("[cache-coverage] phase %02u %s: total=%u (c0=%u c1=%u c2=%u c3=%u)\n", + phase, name, total, + phase_errs[phase][0], phase_errs[phase][1], + phase_errs[phase][2], phase_errs[phase][3]); +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t chunk = TOTAL_WORDS / MAX_CORES; + const uint32_t base = chunk * cid; + + // ---------------- Phase 00: setup -------------------------------- + if (cid == 0) { + l1d_flush(); + l1d_wait(); + l1d_xbar_config(31 - __builtin_clz(LINE_BYTES)); // line-interleaved + l1d_init(0); + l1d_wait(); + printf("[cache-coverage] phase 00: setup done\n"); + // zero the phase_errs table + for (uint32_t i = 0; i < N_PHASES; ++i) + for (uint32_t c = 0; c < MAX_CORES; ++c) phase_errs[i][c] = 0; + } + snrt_cluster_hw_barrier(); + + // ---------------- Phase 01: cold + hit (all cores) ---------------- + phase_errs[1][cid] = phase_01_cold_then_hit(buf, base, chunk); + snrt_cluster_hw_barrier(); + summary(cid, 1, "cold+hit"); + + // ---------------- Phase 02: partial-bytes (all cores) ------------- + phase_errs[2][cid] = phase_02_partial_bytes(scratch[cid]); + snrt_cluster_hw_barrier(); + summary(cid, 2, "partial-bytes"); + + // ---------------- Phase 03: eviction (all cores) ------------------ + phase_errs[3][cid] = phase_03_eviction(buf, base, chunk); + snrt_cluster_hw_barrier(); + summary(cid, 3, "eviction"); + + // ---------------- Phase 04: multicore disjoint slices ------------- + phase_errs[4][cid] = phase_04_multicore(buf, TOTAL_WORDS, cid); + snrt_cluster_hw_barrier(); + summary(cid, 4, "multicore-disjoint"); + + // ---------------- Phase 05: vector (all cores) -------------------- + phase_errs[5][cid] = phase_05_vector_rw(buf, base, chunk); + snrt_cluster_hw_barrier(); + summary(cid, 5, "vector"); + + // ---------------- Phase 06: set-conflict (single core) ------------ + if (cid == 0) + phase_errs[6][0] = phase_06_set_conflict(conflict_buf); + snrt_cluster_hw_barrier(); + summary(cid, 6, "set-conflict"); + + // ---------------- Phase 07: random LFSR (all cores) --------------- + phase_errs[7][cid] = phase_07_random_lfsr(buf, base, chunk, cid); + snrt_cluster_hw_barrier(); + summary(cid, 7, "random-lfsr"); + + // ---------------- Phase 08: AMO multi-core ------------------------ + if (cid == 0) amo_counter = 0; + snrt_cluster_hw_barrier(); + phase_errs[8][cid] = phase_08_amo_multicore(cid); + snrt_cluster_hw_barrier(); + if (cid == 0) { + uint32_t expected = MAX_CORES * AMO_ITER; + uint32_t got = amo_counter; + phase_errs[8][0] += (got != expected); + printf("[cache-coverage] phase 08 AMO: expected=%u got=%u %s\n", + expected, got, (got != expected) ? "FAIL" : "OK"); + } + snrt_cluster_hw_barrier(); + + // ---------------- Phase 09: ping-pong (all cores) ----------------- + // Each core ping-pongs on a different line within its own slice. + phase_errs[9][cid] = phase_09_pingpong(buf, base + (WORDS_PER_LINE * cid)); + snrt_cluster_hw_barrier(); + summary(cid, 9, "ping-pong"); + + // ---------------- Phase 10: cross-core RAW (all cores) ------------ + phase_errs[10][cid] = phase_10_cross_core_raw(buf, TOTAL_WORDS, cid); + snrt_cluster_hw_barrier(); + summary(cid, 10, "cross-core RAW"); + + // ---------------- Phase 11: multi-core shared-set ----------------- + phase_errs[11][cid] = phase_11_shared_set(shared_conflict_buf, cid); + snrt_cluster_hw_barrier(); + summary(cid, 11, "shared-set"); + + // ---------------- Phase 12: producer-consumer chain --------------- + phase_errs[12][cid] = phase_12_producer_chain(buf, base, chunk, cid); + snrt_cluster_hw_barrier(); + summary(cid, 12, "producer-chain"); + + // ---------------- Report ------------------------------------------ + if (cid < MAX_CORES) core_errors[cid] = phase_errs[0][cid]; + snrt_cluster_hw_barrier(); + + if (cid == 0) { + uint32_t total = 0; + for (uint32_t p = 0; p < N_PHASES; ++p) + for (uint32_t c = 0; c < MAX_CORES; ++c) + total += phase_errs[p][c]; + if (total == 0) printf("[cache-coverage] ALL PHASES PASS\n"); + else printf("[cache-coverage] FAIL: total errors = %u\n", total); + } + + return 0; +} + +// ===================================================================== +// Phase 01: cold + hit on per-core slice. +// ===================================================================== +static uint32_t phase_01_cold_then_hit(volatile uint32_t *p, + uint32_t base, uint32_t chunk) { + uint32_t errs = 0; + for (uint32_t i = 0; i < chunk; ++i) p[base + i] = pattern(base + i); + for (uint32_t i = 0; i < chunk; ++i) { + uint32_t got = p[base + i]; + uint32_t exp = pattern(base + i); + if (got != exp) ++errs; + } + return errs; +} + +// ===================================================================== +// Phase 02: partial-byte stores on a per-core scratch line. +// ===================================================================== +static uint32_t phase_02_partial_bytes(volatile uint8_t *p) { + uint32_t errs = 0; + volatile uint32_t *w = (volatile uint32_t *)p; + for (uint32_t i = 0; i < LINE_BYTES / 4; ++i) w[i] = 0xDEADBE00u | i; + + p[5] = 0x42; + if (p[5] != 0x42) ++errs; + if (p[4] != (uint8_t)(0xDEADBE01u >> 0)) ++errs; + if (p[6] != (uint8_t)(0xDEADBE01u >> 16)) ++errs; + if (p[7] != (uint8_t)(0xDEADBE01u >> 24)) ++errs; + + *((volatile uint16_t *)(p + 10)) = 0xCAFEu; + if (*((volatile uint16_t *)(p + 10)) != 0xCAFEu) ++errs; + if (p[8] != (uint8_t)(0xDEADBE02u >> 0)) ++errs; + if (p[9] != (uint8_t)(0xDEADBE02u >> 8)) ++errs; + + return errs; +} + +// ===================================================================== +// Phase 03: write forward, reverse-walk read. Per-core slice. +// ===================================================================== +static uint32_t phase_03_eviction(volatile uint32_t *p, + uint32_t base, uint32_t chunk) { + uint32_t errs = 0; + for (uint32_t i = 0; i < chunk; ++i) p[base + i] = pattern(base + i) ^ 0xFF00FF00u; + for (int32_t i = (int32_t)chunk - 1; i >= 0; --i) { + uint32_t got = p[base + (uint32_t)i]; + uint32_t exp = pattern(base + (uint32_t)i) ^ 0xFF00FF00u; + if (got != exp) ++errs; + } + return errs; +} + +// ===================================================================== +// Phase 04: each core writes its slice, all cores read all slices +// (4-way cross-traffic on the cache). +// ===================================================================== +static uint32_t phase_04_multicore(volatile uint32_t *p, uint32_t n, uint32_t cid) { + if (cid >= MAX_CORES) return 0; + uint32_t chunk = n / MAX_CORES; + uint32_t base = chunk * cid; + uint32_t errs = 0; + for (uint32_t i = 0; i < chunk; ++i) + p[base + i] = pattern(base + i) ^ core_tag(cid); + snrt_cluster_hw_barrier(); + // Each core now reads ALL slices, not just its own. + for (uint32_t c = 0; c < MAX_CORES; ++c) { + uint32_t cbase = chunk * c; + for (uint32_t i = 0; i < chunk; ++i) { + uint32_t got = p[cbase + i]; + uint32_t exp = pattern(cbase + i) ^ core_tag(c); + if (got != exp) ++errs; + } + } + return errs; +} + +// ===================================================================== +// Phase 05: vector vle + vse on per-core slice. Each core's Spatz +// pipeline runs independently, all four producing TCDM traffic in +// parallel on disjoint addresses. +// ===================================================================== +static uint32_t phase_05_vector_rw(volatile uint32_t *p, + uint32_t base, uint32_t chunk) { + uint32_t errs = 0; + uint32_t i = 0; + while (i < chunk) { + uint32_t avl = chunk - i; + uint32_t vl; + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + for (uint32_t j = 0; j < vl; ++j) + p[base + i + j] = pattern(base + i + j) ^ 0xCC00CC00u; + asm volatile("vle32.v v0, (%0)" : : "r"(&p[base + i]) : "memory"); + asm volatile("vse32.v v0, (%0)" : : "r"(&p[base + i]) : "memory"); + for (uint32_t j = 0; j < vl; ++j) { + uint32_t got = p[base + i + j]; + uint32_t exp = pattern(base + i + j) ^ 0xCC00CC00u; + if (got != exp) ++errs; + } + i += vl; + } + return errs; +} + +// ===================================================================== +// Phase 06: 8 stride-64KiB addresses → all same cache set → 4 evictions. +// Single core. +// ===================================================================== +static uint32_t phase_06_set_conflict(volatile uint8_t *base) { + uint32_t errs = 0; + volatile uint32_t *p[CONFLICT_LINES]; + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) + p[k] = (volatile uint32_t *)(base + (k * CONFLICT_STRIDE)); + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) + *(p[k]) = 0xC0FFEE00u + k; + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) { + uint32_t got = *(p[k]); + uint32_t exp = 0xC0FFEE00u + k; + if (got != exp) { + if (errs < 8) + printf(" [p06 round1] k=%u addr=0x%x exp=0x%x got=0x%x\n", + k, (uint32_t)p[k], exp, got); + ++errs; + } + } + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) + *(p[k]) = 0xDEADC0DEu - k; + for (uint32_t k = 0; k < CONFLICT_LINES; ++k) { + uint32_t got = *(p[k]); + uint32_t exp = 0xDEADC0DEu - k; + if (got != exp) { + if (errs < 16) + printf(" [p06 round2] k=%u addr=0x%x exp=0x%x got=0x%x\n", + k, (uint32_t)p[k], exp, got); + ++errs; + } + } + return errs; +} + +// ===================================================================== +// Phase 07: pseudo-random access pattern (per-core LFSR). +// ===================================================================== +static uint32_t phase_07_random_lfsr(volatile uint32_t *p, + uint32_t base, uint32_t chunk, + uint32_t cid) { + uint32_t errs = 0; + uint32_t lfsr = 0xACE1u + cid * 0x1357u; // distinct seed per core + for (uint32_t iter = 0; iter < LFSR_ITER; ++iter) { + uint32_t lsb = lfsr & 1u; + lfsr >>= 1; + if (lsb) lfsr ^= 0xB400u; + if (lfsr == 0) lfsr = 0xACE1u; + uint32_t idx = lfsr % chunk; + uint32_t val = (iter << 16) | ((lfsr & 0xFFFu) << 4) | cid; + p[base + idx] = val; + uint32_t got = p[base + idx]; + if (got != val) ++errs; + } + return errs; +} + +// ===================================================================== +// Phase 08: AMO atomicity. Every core does AMO_ITER amoadds. +// ===================================================================== +static uint32_t phase_08_amo_multicore(uint32_t cid) { + if (cid >= MAX_CORES) return 0; + for (uint32_t i = 0; i < AMO_ITER; ++i) { + uint32_t one = 1; + asm volatile("amoadd.w zero, %1, %0" + : "+A"(amo_counter) + : "r"(one)); + } + return 0; +} + +// ===================================================================== +// Phase 09: ping-pong on a per-core line. Catches forwarding-buffer +// state divergence and WRITE_PEND → VALID merge bugs. +// ===================================================================== +static uint32_t phase_09_pingpong(volatile uint32_t *p, uint32_t addr) { + uint32_t errs = 0; + for (uint32_t iter = 0; iter < PINGPONG_ITER; ++iter) { + uint32_t v = (iter * 0xDEADBEEFu) ^ 0x12345678u; + p[addr] = v; + uint32_t got = p[addr]; + if (got != v) ++errs; + } + return errs; +} + +// ===================================================================== +// Phase 10: cross-core read-after-write — each core writes its slice, +// then reads its NEIGHBOUR'S slice and verifies. Catches stale-data- +// from-wrong-core bugs. +// ===================================================================== +static uint32_t phase_10_cross_core_raw(volatile uint32_t *p, uint32_t n, uint32_t cid) { + if (cid >= MAX_CORES) return 0; + uint32_t chunk = n / MAX_CORES; + uint32_t errs = 0; + // Write own slice. + for (uint32_t i = 0; i < chunk; ++i) + p[chunk * cid + i] = pattern(chunk * cid + i) ^ 0xBEEFBEEFu; + snrt_cluster_hw_barrier(); + // Read NEIGHBOUR's slice. cid=0 reads cid=1's, 1 reads 2's, etc. + uint32_t nb = (cid + 1) % MAX_CORES; + uint32_t nbase = chunk * nb; + for (uint32_t i = 0; i < chunk; ++i) { + uint32_t got = p[nbase + i]; + uint32_t exp = pattern(nbase + i) ^ 0xBEEFBEEFu; + if (got != exp) ++errs; + } + return errs; +} + +// ===================================================================== +// Phase 11: SHARED-SET multi-core contention. Every core owns 4 stride- +// 64KiB lines from the SAME big buffer (offsets cid*4..cid*4+3), all of +// which map to the SAME cache set under offset=6. Total of 16 lines hit +// 1 set with 4 ways → 12 forced evictions, on top of the 4-way race for +// the resident slots between the 4 cores. +// ===================================================================== +static uint32_t phase_11_shared_set(volatile uint8_t *base, uint32_t cid) { + if (cid >= MAX_CORES) return 0; + volatile uint32_t *p[SHARED_CONFLICT_LINES_PER_CORE]; + uint32_t core_off = cid * SHARED_CONFLICT_LINES_PER_CORE; + for (uint32_t k = 0; k < SHARED_CONFLICT_LINES_PER_CORE; ++k) + p[k] = (volatile uint32_t *)(base + ((core_off + k) * CONFLICT_STRIDE)); + + // Each core writes a per-core marker on its lines. + uint32_t errs = 0; + for (uint32_t k = 0; k < SHARED_CONFLICT_LINES_PER_CORE; ++k) + *(p[k]) = core_tag(cid) ^ (0xC0DE0000u + k); + + // Barrier ensures all cores have written before any starts reading. + snrt_cluster_hw_barrier(); + + // Each core reads back ITS OWN lines and verifies. Even with massive + // multi-core eviction churn on the SAME set, each core's tag must be + // returned intact. + for (uint32_t k = 0; k < SHARED_CONFLICT_LINES_PER_CORE; ++k) { + uint32_t got = *(p[k]); + uint32_t exp = core_tag(cid) ^ (0xC0DE0000u + k); + if (got != exp) { + if (errs < 4) + printf(" [p11 cid=%u] k=%u addr=0x%x exp=0x%x got=0x%x\n", + cid, k, (uint32_t)p[k], exp, got); + ++errs; + } + } + return errs; +} + +// ===================================================================== +// Phase 12: producer-consumer chain. +// c0 writes its slice with value V. +// c1 reads its slice (the part c0 wrote), verifies, then writes V+1. +// c2 reads c1's output, verifies, writes V+2. +// c3 reads c2's output, verifies, writes V+3. +// Each step uses a barrier — exercises the cross-core handoff +// (each core consumes data that lived in DRAM/cache from another core). +// ===================================================================== +static uint32_t phase_12_producer_chain(volatile uint32_t *p, + uint32_t base, uint32_t chunk, + uint32_t cid) { + if (cid >= MAX_CORES) return 0; + uint32_t errs = 0; + // Stage 0: c0 writes; others wait. + if (cid == 0) + for (uint32_t i = 0; i < chunk; ++i) + p[base + i] = pattern(base + i) ^ 0x10000000u; + snrt_cluster_hw_barrier(); + + // Stages 1..3: cid C reads (C-1)'s slice, verifies, writes its own. + for (uint32_t stage = 1; stage < MAX_CORES; ++stage) { + if (cid == stage) { + uint32_t prev_base = (stage - 1) * chunk; + for (uint32_t i = 0; i < chunk; ++i) { + uint32_t got = p[prev_base + i]; + uint32_t exp = pattern(prev_base + i) ^ ((uint32_t)stage << 28); + if (got != exp) ++errs; + } + // Now write own slice with stage's tag. + for (uint32_t i = 0; i < chunk; ++i) + p[base + i] = pattern(base + i) ^ ((uint32_t)(stage + 1) << 28); + } + snrt_cluster_hw_barrier(); + } + return errs; +} diff --git a/software/tests/cache-line-rw-smoke/main.c b/software/tests/cache-line-rw-smoke/main.c new file mode 100644 index 0000000..7c4b28b --- /dev/null +++ b/software/tests/cache-line-rw-smoke/main.c @@ -0,0 +1,71 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 + +#include +#include +#include +#include "printf.h" + +#define MAX_CORES 8U +#define LINE_BYTES 64U +#define WORD_BYTES 4U +#define WORDS_PER_LINE (LINE_BYTES / WORD_BYTES) +#define NUM_LINES 16U +#define TOTAL_WORDS (NUM_LINES * WORDS_PER_LINE) +#define L1LineWidth (512/8) // 512 bits + +static uint32_t line_buf[TOTAL_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(LINE_BYTES))); +static uint32_t core_errors[MAX_CORES] __attribute__((section(".dram"))) + __attribute__((aligned(64))); + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + volatile uint32_t *buf = line_buf; + uint32_t errs = 0; + + if (cid == 0) { + l1d_flush(); + uint32_t offset = 31 - __builtin_clz(L1LineWidth); + l1d_xbar_config(offset); // cacheline interleaving + } + snrt_cluster_hw_barrier(); + + if (cid == 0) { + for (uint32_t word = 0; word < TOTAL_WORDS; word++) { + buf[word] = word; + } + + for (uint32_t word = 0; word < TOTAL_WORDS; word++) { + const uint32_t got = buf[word]; + const uint32_t exp = word; + if (got != exp) { + errs++; + } + } + } + + if (cid < MAX_CORES) { + core_errors[cid] = errs; + } + snrt_cluster_hw_barrier(); + + if (cid == 0) { + uint32_t total_err = 0; + for (uint32_t i = 0; i < MAX_CORES; i++) { + total_err += core_errors[i]; + } + + if (total_err == 0) { + printf("[PASS] cache-line-rw-smoke: lines=%u words=%u\n", NUM_LINES, TOTAL_WORDS); + } else { + printf("[FAIL] cache-line-rw-smoke: errors=%u lines=%u words=%u\n", + total_err, NUM_LINES, TOTAL_WORDS); + } + + l1d_flush(); + return (int)total_err; + } + + return 0; +} diff --git a/software/tests/cache-mix-pressure/main.c b/software/tests/cache-mix-pressure/main.c new file mode 100644 index 0000000..de6b0be --- /dev/null +++ b/software/tests/cache-mix-pressure/main.c @@ -0,0 +1,113 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 + +#include +#include +#include +#include "printf.h" + +#define MAX_CORES 8U +#define REGION_BYTES 4096U +#define TOTAL_BYTES (MAX_CORES * REGION_BYTES) +#define VEC_LEN 16U +#define ITERS 4000U +#define SCALAR_CORE 0U +#define VECTOR_CORE 1U + +static uint8_t pressure_buf[TOTAL_BYTES] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static uint32_t vec_vals[VEC_LEN] __attribute__((section(".data"))); +static uint32_t core_sig[MAX_CORES] __attribute__((section(".data"))); +static uint32_t core_err[MAX_CORES] __attribute__((section(".data"))); + +static inline void vec_store_u32(uint32_t *base) { + uint32_t vl = 0; + asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(VEC_LEN)); + asm volatile("vle32.v v0, (%0)" : : "r"(vec_vals) : "memory"); + asm volatile("vse32.v v0, (%0)" : : "r"(base) : "memory"); +} + +static inline uint32_t scalar_mix(uint32_t x) { + x ^= x << 13; + x ^= x >> 17; + x ^= x << 5; + return x; +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t cores = snrt_cluster_core_num(); + const uint32_t scalar_active = (cid == SCALAR_CORE); + const uint32_t vector_active = (cid == VECTOR_CORE); + + if (cid == 0) { + l1d_init(0); + for (uint32_t i = 0; i < VEC_LEN; i++) { + vec_vals[i] = 0xABCD0000u + i; + } + for (uint32_t i = 0; i < TOTAL_BYTES; i++) { + pressure_buf[i] = (uint8_t)(i ^ 0x5Au); + } + for (uint32_t i = 0; i < MAX_CORES; i++) { + core_sig[i] = 0; + core_err[i] = 0; + } + } + snrt_cluster_hw_barrier(); + + uint32_t sig = 0x13579BDFu ^ cid; + uint32_t errs = 0; + if (scalar_active) { + uint8_t *base = &pressure_buf[SCALAR_CORE * REGION_BYTES]; + for (uint32_t it = 0; it < ITERS; it++) { + // Keep `win` 4-byte aligned: Snitch raises a misaligned + // load/store exception for unaligned uint32_t accesses and + // there's no exception handler installed in this runtime, so + // an unaligned `win` would put core 1+ in a trap loop. The + // multiplier 28 = 7*4 preserves the original "varied per-core + // offset" intent while staying 4-aligned. + const uint32_t win = (it * 64u + cid * 28u) % (REGION_BYTES - 64u); + volatile uint32_t *sw = (volatile uint32_t *)(base + win + 32u); + const uint32_t w = scalar_mix(sig ^ it); + *sw = w; + sig ^= *sw; + } + core_sig[cid] = sig; + core_err[cid] = errs; + } else if (vector_active) { + uint8_t *base = &pressure_buf[VECTOR_CORE * REGION_BYTES]; + for (uint32_t it = 0; it < ITERS; it++) { + // Same alignment requirement as the scalar branch above. + const uint32_t win = (it * 64u + cid * 28u) % (REGION_BYTES - 64u); + vec_store_u32((uint32_t *)(base + win)); + for (uint32_t j = 0; j < VEC_LEN; j++) { + volatile uint32_t *wp = (volatile uint32_t *)(base + win + j * 4U); + const uint32_t got = *wp; + sig = scalar_mix(sig ^ got ^ (j << 8)); + if (got != vec_vals[j]) errs++; + } + } + core_sig[cid] = sig; + core_err[cid] = errs; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + uint32_t total_err = 0; + uint32_t fold_sig = 0; + const uint32_t used = (cores > MAX_CORES) ? MAX_CORES : cores; + for (uint32_t i = 0; i < used; i++) { + total_err += core_err[i]; + fold_sig ^= core_sig[i]; + } + if (total_err == 0) { + printf("[PASS] cache-mix-pressure: done, signature=0x%08x\n", fold_sig); + } else { + printf("[FAIL] cache-mix-pressure: errors=%u signature=0x%08x\n", total_err, fold_sig); + } + l1d_flush(); + return (int)total_err; + } + + return 0; +} diff --git a/software/tests/cache-mix-smoke/main.c b/software/tests/cache-mix-smoke/main.c new file mode 100644 index 0000000..c275c60 --- /dev/null +++ b/software/tests/cache-mix-smoke/main.c @@ -0,0 +1,86 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 + +#include +#include +#include +#include "printf.h" + +#define MAX_CORES 8U +#define REGION_BYTES 1024U +#define TOTAL_BYTES (MAX_CORES * REGION_BYTES) +#define PART_BYTES 16U +#define VEC_LEN 4U +#define ITERS 256U +#define SCALAR_CORE 1U +#define VECTOR_CORE 0U + +static uint8_t mix_buf[TOTAL_BYTES] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static uint32_t vec_vals[VEC_LEN] __attribute__((section(".data"))) = { + 0x11111131u, 0x22222242u, 0x33333353u, 0x44444464u}; +static uint32_t core_errors[MAX_CORES] __attribute__((section(".data"))); + +static inline void vec_store_u32(uint32_t *base) { + uint32_t vl = 0; + asm volatile("vsetvli %0, %1, e32, m1, ta, ma" : "=r"(vl) : "r"(VEC_LEN)); + asm volatile("vle32.v v0, (%0)" : : "r"(vec_vals) : "memory"); + asm volatile("vse32.v v0, (%0)" : : "r"(base) : "memory"); +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t cores = snrt_cluster_core_num(); + const uint32_t scalar_active = (cid == SCALAR_CORE); + const uint32_t vector_active = (cid == VECTOR_CORE); + + if (cid == 0) { + l1d_init(0); + for (uint32_t i = 0; i < TOTAL_BYTES; i++) { + mix_buf[i] = (uint8_t)(0xA0u ^ (uint8_t)i); + } + for (uint32_t i = 0; i < MAX_CORES; i++) { + core_errors[i] = 0; + } + } + snrt_cluster_hw_barrier(); + + uint32_t errs = 0; + if (scalar_active) { + uint8_t *base = &mix_buf[SCALAR_CORE * REGION_BYTES]; + for (uint32_t it = 0; it < ITERS; it++) { + const uint32_t part_ofst = (it * PART_BYTES) % (REGION_BYTES - PART_BYTES); + volatile uint32_t *word_p = (volatile uint32_t *)(base + part_ofst + 12); + const uint32_t scalar_exp = (cid << 24) ^ (it * 0x10201u); + *word_p = scalar_exp; + if (*word_p != scalar_exp) errs++; + } + core_errors[cid] = errs; + } else if (vector_active) { + uint8_t *base = &mix_buf[VECTOR_CORE * REGION_BYTES]; + for (uint32_t it = 0; it < ITERS; it++) { + const uint32_t part_ofst = (it * PART_BYTES) % (REGION_BYTES - PART_BYTES); + vec_store_u32((uint32_t *)(base + part_ofst)); + for (uint32_t j = 0; j < VEC_LEN; j++) { + volatile uint32_t *wp = (volatile uint32_t *)(base + part_ofst + j * 4U); + if (*wp != vec_vals[j]) errs++; + } + } + core_errors[cid] = errs; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + uint32_t total = 0; + const uint32_t used = (cores > MAX_CORES) ? MAX_CORES : cores; + for (uint32_t i = 0; i < used; i++) total += core_errors[i]; + if (total == 0) { + printf("[PASS] cache-mix-smoke: mixed scalar/vector access OK\n"); + } else { + printf("[FAIL] cache-mix-smoke: %u mismatches\n", total); + } + l1d_flush(); + return (int)total; + } + return 0; +} diff --git a/software/tests/cache-rlc-mimic/main.c b/software/tests/cache-rlc-mimic/main.c new file mode 100644 index 0000000..0246b2a --- /dev/null +++ b/software/tests/cache-rlc-mimic/main.c @@ -0,0 +1,191 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 + +#include +#include +#include +#include "printf.h" + +#define MAX_CORES 8U +#define CONSUMER_CORE 0U +#define PRODUCER_CORE 1U +#ifndef RLCM_PKT_BYTES +#define RLCM_PKT_BYTES 1360U +#endif +#define WORD_BYTES 4U +#define PKT_BYTES RLCM_PKT_BYTES +#define PKT_WORDS (PKT_BYTES / WORD_BYTES) +#ifndef RLCM_JOBS_PER_PRODUCER +#define RLCM_JOBS_PER_PRODUCER 24U +#endif +#define JOBS_PER_PRODUCER RLCM_JOBS_PER_PRODUCER +#define ACTIVE_PRODUCERS 1U +#define MAX_JOBS (ACTIVE_PRODUCERS * JOBS_PER_PRODUCER) + +typedef struct { + uint32_t src_word_ofst; + uint32_t dst_word_ofst; + uint32_t words; + uint32_t valid; +} job_t; + +static uint32_t src_buf[MAX_JOBS * PKT_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static uint32_t dst_buf[MAX_JOBS * PKT_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static job_t job_table[MAX_JOBS] __attribute__((section(".dram"))) + __attribute__((aligned(64))); + +static uint32_t prod_done[MAX_CORES] __attribute__((section(".data"))); +static uint32_t core_err[MAX_CORES] __attribute__((section(".data"))); +static uint32_t core_sig[MAX_CORES] __attribute__((section(".data"))); + +static inline uint32_t mix32(uint32_t x) { + x ^= x << 13; + x ^= x >> 17; + x ^= x << 5; + return x; +} + +static inline void vec_copy_u32(uint32_t *dst, const uint32_t *src, uint32_t words) { + uint32_t copied = 0; + while (copied < words) { + uint32_t avl = words - copied; + uint32_t vl = 0; + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + asm volatile("vle32.v v0, (%0)" : : "r"(src + copied) : "memory"); + asm volatile("vse32.v v0, (%0)" : : "r"(dst + copied) : "memory"); + copied += vl; + } +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t producers = ACTIVE_PRODUCERS; + const uint32_t total_jobs = producers * JOBS_PER_PRODUCER; + + if (cid == 0) { + l1d_init(0); + for (uint32_t i = 0; i < MAX_JOBS * PKT_WORDS; i++) { + src_buf[i] = 0; + dst_buf[i] = 0; + } + for (uint32_t i = 0; i < MAX_JOBS; i++) { + job_table[i].src_word_ofst = 0; + job_table[i].dst_word_ofst = 0; + job_table[i].words = 0; + job_table[i].valid = 0; + } + for (uint32_t i = 0; i < MAX_CORES; i++) { + prod_done[i] = 0; + core_err[i] = 0; + core_sig[i] = 0; + } + } + snrt_cluster_hw_barrier(); + + uint32_t errs = 0; + uint32_t sig = 0x12345678u ^ (cid * 0x1020304u); + + if (cid == PRODUCER_CORE) { + const uint32_t pidx = 0; + for (uint32_t j = 0; j < JOBS_PER_PRODUCER; j++) { + const uint32_t job_id = pidx * JOBS_PER_PRODUCER + j; + const uint32_t src_base = (((j * producers) + pidx) * PKT_WORDS) % + (MAX_JOBS * PKT_WORDS - PKT_WORDS); + const uint32_t dst_base = (((j * producers) + ((pidx + 3U) % + (producers ? producers : 1U))) * PKT_WORDS) % + (MAX_JOBS * PKT_WORDS - PKT_WORDS); + + for (uint32_t w = 0; w < PKT_WORDS; w++) { + uint32_t v = mix32(((pidx + 1U) << 24) ^ (job_id << 12) ^ w); + src_buf[src_base + w] = v; + dst_buf[dst_base + w] = v ^ 0x5a5a5a5au; + } + + job_table[job_id].src_word_ofst = src_base; + job_table[job_id].dst_word_ofst = dst_base; + job_table[job_id].words = PKT_WORDS; + __atomic_store_n(&job_table[job_id].valid, 1U, __ATOMIC_RELEASE); + sig ^= mix32(src_base ^ (dst_base << 1) ^ job_id); + } + __atomic_store_n(&prod_done[PRODUCER_CORE], 1U, __ATOMIC_RELEASE); + } + + if (cid == CONSUMER_CORE) { + uint32_t consumed = 0; + uint32_t scan = 0; + uint32_t progress_epoch = 0; + + while (consumed < total_jobs) { + uint32_t job_id = scan % (total_jobs ? total_jobs : 1U); + if (__atomic_load_n(&job_table[job_id].valid, __ATOMIC_ACQUIRE) == 1U) { + uint32_t src_base = job_table[job_id].src_word_ofst; + uint32_t dst_base = job_table[job_id].dst_word_ofst; + uint32_t words = job_table[job_id].words; + + vec_copy_u32(&dst_buf[dst_base], &src_buf[src_base], words); + + // Spot-check a few words, then full checksum accumulate to catch corruption. + for (uint32_t k = 0; k < words; k += 17U) { + uint32_t got = dst_buf[dst_base + k]; + uint32_t exp = src_buf[src_base + k]; + if (got != exp) errs++; + sig ^= mix32(got ^ (k << 8) ^ job_id); + } + + __atomic_store_n(&job_table[job_id].valid, 0U, __ATOMIC_RELEASE); + consumed++; + } + scan++; + + if ((scan & 0x7ffffU) == 0U) { + uint32_t done_mask = 0; + if (__atomic_load_n(&prod_done[PRODUCER_CORE], __ATOMIC_ACQUIRE) != 0U) + done_mask |= (1U << PRODUCER_CORE); + printf("[PROGRESS] cache-rlc-mimic: epoch=%u consumed=%u/%u scan=%u done_mask=0x%08x\n", + progress_epoch, consumed, total_jobs, scan, done_mask); + progress_epoch++; + } + } + + // End-to-end verify full destination buffers for all jobs. + for (uint32_t job_id = 0; job_id < total_jobs; job_id++) { + uint32_t src_base = job_table[job_id].src_word_ofst; + uint32_t dst_base = job_table[job_id].dst_word_ofst; + for (uint32_t w = 0; w < PKT_WORDS; w++) { + uint32_t got = dst_buf[dst_base + w]; + uint32_t exp = src_buf[src_base + w]; + if (got != exp) errs++; + } + } + } + + if (cid < MAX_CORES) { + core_err[cid] = errs; + core_sig[cid] = sig; + } + snrt_cluster_hw_barrier(); + + if (cid == 0) { + uint32_t total_err = 0; + uint32_t fold_sig = 0; + for (uint32_t i = 0; i <= PRODUCER_CORE; i++) { + total_err += core_err[i]; + fold_sig ^= core_sig[i]; + } + + if (total_err == 0) { + printf("[PASS] cache-rlc-mimic: jobs=%u pkt=%uB signature=0x%08x\n", + total_jobs, PKT_BYTES, fold_sig); + } else { + printf("[FAIL] cache-rlc-mimic: errors=%u jobs=%u pkt=%uB signature=0x%08x\n", + total_err, total_jobs, PKT_BYTES, fold_sig); + } + + l1d_flush(); + return (int)total_err; + } + + return 0; +} diff --git a/software/tests/cache-test-scalar/main.c b/software/tests/cache-test-scalar/main.c new file mode 100644 index 0000000..159e7dd --- /dev/null +++ b/software/tests/cache-test-scalar/main.c @@ -0,0 +1,298 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#include +#include +#include +#include "printf.h" + +#ifndef CACHE_TEST_ENABLE_BASIC +#define CACHE_TEST_ENABLE_BASIC 1 +#endif + +#ifndef CACHE_TEST_ENABLE_STRESS +#define CACHE_TEST_ENABLE_STRESS 1 +#endif + +#define CACHE_LINE_BYTES (512 / 8) +#define PART_BYTES 16U +#define WORDS_PER_LINE (CACHE_LINE_BYTES / sizeof(uint32_t)) +#define PART_WORDS (PART_BYTES / sizeof(uint32_t)) +#define MAX_CORES 32U + +#define BASIC_LINES 256U +#define BASIC_WORDS (BASIC_LINES * WORDS_PER_LINE) +#define BASIC_PARTS_PER_LINE (WORDS_PER_LINE / PART_WORDS) +#define BASIC_SEED 0x13579BDu + +#define STRESS_WORDS_PER_CORE 8192U +#define STRESS_BLOCKS_PER_CORE (STRESS_WORDS_PER_CORE / PART_WORDS) +#define STRESS_PASSES 4U + +static uint32_t basic_buf[BASIC_WORDS] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); + +static uint32_t stress_buf[MAX_CORES * STRESS_WORDS_PER_CORE] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); + +static uint32_t basic_errors[MAX_CORES] __attribute__((section(".data"))); +static uint32_t stress_errors[MAX_CORES] __attribute__((section(".data"))); + +static inline uint32_t basic_base_pattern(uint32_t line, uint32_t word) { + return BASIC_SEED ^ (line * 0x9E3779B1u) ^ (word * 0x85EBCA6Bu); +} + +static inline uint32_t basic_offset_pattern(uint32_t line, uint32_t word) { + return 0xA5A50000u ^ (line * 0x27D4EB2Du) ^ word; +} + +static inline uint32_t stress_pattern(uint32_t pass, uint32_t idx, + uint32_t cid) { + return 0xA5000000u ^ (cid << 16) ^ (pass << 8) ^ idx; +} + +static uint32_t run_basic_test(void) { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t num_cores = snrt_cluster_core_num(); + + snrt_cluster_hw_barrier(); + + if (cid == 0) { + for (uint32_t line = 0; line < BASIC_LINES; line++) { + const uint32_t base = line * WORDS_PER_LINE; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + basic_buf[base + part + w] = + basic_base_pattern(line, part + w); + } + } + } + } + snrt_cluster_hw_barrier(); + + const uint32_t lines_per_core = (BASIC_LINES + num_cores - 1U) / num_cores; + const uint32_t start_line = cid * lines_per_core; + const uint32_t end_line = + (start_line + lines_per_core > BASIC_LINES) + ? BASIC_LINES + : (start_line + lines_per_core); + + uint32_t errors = 0; + for (uint32_t line = start_line; line < end_line; line++) { + const uint32_t base = line * WORDS_PER_LINE; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = part + w; + const uint32_t got = basic_buf[base + idx]; + const uint32_t exp = basic_base_pattern(line, idx); + if (got != exp) { + errors++; + } + } + } + } + if (cid < MAX_CORES) { + basic_errors[cid] = errors; + } + + snrt_cluster_hw_barrier(); + + if (cid == 0) { + for (uint32_t line = 0; line < BASIC_LINES; line++) { + const uint32_t base = line * WORDS_PER_LINE; + const uint32_t part_idx = (line * 5u + 1u) % BASIC_PARTS_PER_LINE; + const uint32_t offset = part_idx * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + basic_buf[base + offset + w] = + basic_offset_pattern(line, offset + w); + } + } + } + snrt_cluster_hw_barrier(); + + errors = 0; + for (uint32_t line = start_line; line < end_line; line++) { + const uint32_t base = line * WORDS_PER_LINE; + const uint32_t part_idx = (line * 5u + 1u) % BASIC_PARTS_PER_LINE; + const uint32_t offset = part_idx * PART_WORDS; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = part + w; + const uint32_t exp = + (idx >= offset && idx < offset + PART_WORDS) + ? basic_offset_pattern(line, idx) + : basic_base_pattern(line, idx); + const uint32_t got = basic_buf[base + idx]; + if (got != exp) { + errors++; + } + } + } + } + if (cid < MAX_CORES) { + basic_errors[cid] += errors; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + l1d_flush(); + } + snrt_cluster_hw_barrier(); + + uint32_t result = 0; + if (cid == 0) { + uint32_t total_errors = 0; + uint32_t used_cores = (num_cores > MAX_CORES) ? MAX_CORES : num_cores; + for (uint32_t i = 0; i < used_cores; i++) { + total_errors += basic_errors[i]; + } + if (num_cores > MAX_CORES) { + printf("[WARN] cache-basic: only first %u cores checked.\n", used_cores); + } + if (total_errors == 0) { + printf("[PASS] cache-basic: data integrity OK.\n"); + } else { + printf("[FAIL] cache-basic: %u mismatches.\n", total_errors); + } + result = total_errors; + } + + snrt_cluster_hw_barrier(); + return (cid == 0) ? result : 0; +} + +static uint32_t run_stress_test(void) { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t num_cores = snrt_cluster_core_num(); + + snrt_cluster_hw_barrier(); + + const uint32_t active = (cid < MAX_CORES); + + uint32_t *base = NULL; + if (active) { + base = &stress_buf[cid * STRESS_WORDS_PER_CORE]; + for (uint32_t block = 0; block < STRESS_BLOCKS_PER_CORE; block++) { + const uint32_t base_idx = block * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + base[base_idx + w] = + stress_pattern(0, base_idx + w, cid); + } + } + + for (uint32_t pass = 1; pass < STRESS_PASSES; pass++) { + const uint32_t stride = (cid * 2U + 1U) + (pass * 4U); + for (uint32_t iter = 0; iter < STRESS_BLOCKS_PER_CORE; iter++) { + const uint32_t block = (iter * stride) % STRESS_BLOCKS_PER_CORE; + const uint32_t base_idx = block * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + base[base_idx + w] = + stress_pattern(pass, base_idx + w, cid); + } + } + } + } + + snrt_cluster_hw_barrier(); + + uint32_t errors = 0; + if (active) { + for (uint32_t block = 0; block < STRESS_BLOCKS_PER_CORE; block++) { + const uint32_t base_idx = block * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = base_idx + w; + const uint32_t got = base[idx]; + const uint32_t exp = stress_pattern(STRESS_PASSES - 1U, idx, cid); + if (got != exp) { + errors++; + } + } + } + stress_errors[cid] = errors; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + l1d_flush(); + } + snrt_cluster_hw_barrier(); + + uint32_t result = 0; + if (cid == 0) { + uint32_t total_errors = 0; + uint32_t used_cores = (num_cores > MAX_CORES) ? MAX_CORES : num_cores; + for (uint32_t i = 0; i < used_cores; i++) { + total_errors += stress_errors[i]; + } + if (num_cores > MAX_CORES) { + printf("[WARN] cache-stress: only first %u cores checked.\n", used_cores); + } + if (total_errors == 0) { + printf("[PASS] cache-stress: data integrity OK.\n"); + } else { + printf("[FAIL] cache-stress: %u mismatches.\n", total_errors); + } + result = total_errors; + } + + snrt_cluster_hw_barrier(); + return (cid == 0) ? result : 0; +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + uint32_t failures = 0; + + if (cid == 0) { + l1d_init(0); + } + snrt_cluster_hw_barrier(); + +#if CACHE_TEST_ENABLE_BASIC + if (cid == 0) { + printf("[RUN ] cache-basic\n"); + } + uint32_t basic_errors = run_basic_test(); + if (cid == 0 && basic_errors != 0) { + failures++; + } +#endif + +#if CACHE_TEST_ENABLE_STRESS + if (cid == 0) { + printf("[RUN ] cache-stress\n"); + } + uint32_t stress_errors = run_stress_test(); + if (cid == 0 && stress_errors != 0) { + failures++; + } +#endif + + if (cid == 0) { + if (failures == 0) { + printf("[PASS] cache-tests: all enabled tests passed.\n"); + } else { + printf("[FAIL] cache-tests: %u test group(s) failed.\n", failures); + } + } + + snrt_cluster_hw_barrier(); + return (cid == 0 && failures) ? 1 : 0; +} diff --git a/software/tests/cache-test-vector/main.c b/software/tests/cache-test-vector/main.c new file mode 100644 index 0000000..03c5fb7 --- /dev/null +++ b/software/tests/cache-test-vector/main.c @@ -0,0 +1,334 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// Author: Zexin Fu + +#include +#include +#include +#include "printf.h" + +#ifndef CACHE_TEST_ENABLE_BASIC +#define CACHE_TEST_ENABLE_BASIC 1 +#endif + +#ifndef CACHE_TEST_ENABLE_STRESS +#define CACHE_TEST_ENABLE_STRESS 1 +#endif + +#define CACHE_LINE_BYTES (512 / 8) +#define PART_BYTES 16U +#define WORDS_PER_LINE (CACHE_LINE_BYTES / sizeof(uint32_t)) +#define PART_WORDS (PART_BYTES / sizeof(uint32_t)) +#define MAX_CORES 32U + +#define BASIC_LINES 256U +#define BASIC_WORDS (BASIC_LINES * WORDS_PER_LINE) +#define BASIC_PARTS_PER_LINE (WORDS_PER_LINE / PART_WORDS) +#define BASIC_SEED 0x13579BDu + +#define STRESS_WORDS_PER_CORE 8192U +#define STRESS_BLOCKS_PER_CORE (STRESS_WORDS_PER_CORE / PART_WORDS) +#define STRESS_PASSES 4U + +static uint32_t vec_basic_src[BASIC_WORDS] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); +static uint32_t vec_basic_dst[BASIC_WORDS] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); + +static uint32_t vec_stress_src[MAX_CORES * STRESS_WORDS_PER_CORE] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); +static uint32_t vec_stress_dst[MAX_CORES * STRESS_WORDS_PER_CORE] + __attribute__((section(".dram"))) + __attribute__((aligned(CACHE_LINE_BYTES))); + +static uint32_t basic_errors[MAX_CORES] __attribute__((section(".data"))); +static uint32_t stress_errors[MAX_CORES] __attribute__((section(".data"))); + +static inline uint32_t basic_base_pattern(uint32_t line, uint32_t word) { + return BASIC_SEED ^ (line * 0x9E3779B1u) ^ (word * 0x85EBCA6Bu); +} + +static inline uint32_t basic_offset_pattern(uint32_t line, uint32_t word) { + return 0xA5A50000u ^ (line * 0x27D4EB2Du) ^ word; +} + +static inline uint32_t stress_pattern(uint32_t pass, uint32_t idx, + uint32_t cid) { + return 0xA5000000u ^ (cid << 16) ^ (pass << 8) ^ idx; +} + +static inline void vec_copy_parts_u32(uint32_t *dst, const uint32_t *src, + uint32_t parts) { + for (uint32_t part = 0; part < parts; part++) { + asm volatile("vsetvli zero, %0, e32, m1, ta, ma" :: "r"(PART_WORDS)); + asm volatile("vle32.v v0, (%0)" :: "r"(src) : "memory"); + asm volatile("vse32.v v0, (%0)" :: "r"(dst) : "memory"); + src += PART_WORDS; + dst += PART_WORDS; + } +} + +static uint32_t run_basic_test(void) { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t num_cores = snrt_cluster_core_num(); + + snrt_cluster_hw_barrier(); + + if (cid == 0) { + for (uint32_t line = 0; line < BASIC_LINES; line++) { + const uint32_t base = line * WORDS_PER_LINE; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + vec_basic_src[base + part + w] = + basic_base_pattern(line, part + w); + } + } + } + } + snrt_cluster_hw_barrier(); + + const uint32_t lines_per_core = (BASIC_LINES + num_cores - 1U) / num_cores; + const uint32_t start_line = cid * lines_per_core; + const uint32_t end_line = + (start_line + lines_per_core > BASIC_LINES) + ? BASIC_LINES + : (start_line + lines_per_core); + const uint32_t start_part = start_line * BASIC_PARTS_PER_LINE; + const uint32_t part_count = (end_line - start_line) * BASIC_PARTS_PER_LINE; + const uint32_t start_word = start_part * PART_WORDS; + + if (part_count > 0) { + vec_copy_parts_u32(&vec_basic_dst[start_word], + &vec_basic_src[start_word], part_count); + } + + uint32_t errors = 0; + for (uint32_t line = start_line; line < end_line; line++) { + const uint32_t base = line * WORDS_PER_LINE; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = part + w; + const uint32_t got = vec_basic_dst[base + idx]; + const uint32_t exp = basic_base_pattern(line, idx); + if (got != exp) { + errors++; + } + } + } + } + if (cid < MAX_CORES) { + basic_errors[cid] = errors; + } + + snrt_cluster_hw_barrier(); + + if (cid == 0) { + for (uint32_t line = 0; line < BASIC_LINES; line++) { + const uint32_t base = line * WORDS_PER_LINE; + const uint32_t part_idx = (line * 5u + 1u) % BASIC_PARTS_PER_LINE; + const uint32_t offset = part_idx * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + vec_basic_src[base + offset + w] = + basic_offset_pattern(line, offset + w); + } + } + } + snrt_cluster_hw_barrier(); + + if (part_count > 0) { + vec_copy_parts_u32(&vec_basic_dst[start_word], + &vec_basic_src[start_word], part_count); + } + + errors = 0; + for (uint32_t line = start_line; line < end_line; line++) { + const uint32_t base = line * WORDS_PER_LINE; + const uint32_t part_idx = (line * 5u + 1u) % BASIC_PARTS_PER_LINE; + const uint32_t offset = part_idx * PART_WORDS; + for (uint32_t part = 0; part < WORDS_PER_LINE; part += PART_WORDS) { + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = part + w; + const uint32_t exp = + (idx >= offset && idx < offset + PART_WORDS) + ? basic_offset_pattern(line, idx) + : basic_base_pattern(line, idx); + const uint32_t got = vec_basic_dst[base + idx]; + if (got != exp) { + errors++; + } + } + } + } + if (cid < MAX_CORES) { + basic_errors[cid] += errors; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + l1d_flush(); + } + snrt_cluster_hw_barrier(); + + uint32_t result = 0; + if (cid == 0) { + uint32_t total_errors = 0; + uint32_t used_cores = (num_cores > MAX_CORES) ? MAX_CORES : num_cores; + for (uint32_t i = 0; i < used_cores; i++) { + total_errors += basic_errors[i]; + } + if (num_cores > MAX_CORES) { + printf("[WARN] vcache-basic: only first %u cores checked.\n", used_cores); + } + if (total_errors == 0) { + printf("[PASS] vcache-basic: data integrity OK.\n"); + } else { + printf("[FAIL] vcache-basic: %u mismatches.\n", total_errors); + } + result = total_errors; + } + + snrt_cluster_hw_barrier(); + return (cid == 0) ? result : 0; +} + +static uint32_t run_stress_test(void) { + const uint32_t cid = snrt_cluster_core_idx(); + const uint32_t num_cores = snrt_cluster_core_num(); + + snrt_cluster_hw_barrier(); + + const uint32_t active = (cid < MAX_CORES); + uint32_t *src = NULL; + uint32_t *dst = NULL; + if (active) { + src = &vec_stress_src[cid * STRESS_WORDS_PER_CORE]; + dst = &vec_stress_dst[cid * STRESS_WORDS_PER_CORE]; + for (uint32_t block = 0; block < STRESS_BLOCKS_PER_CORE; block++) { + const uint32_t base_idx = block * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + src[base_idx + w] = stress_pattern(0, base_idx + w, cid); + } + } + } + snrt_cluster_hw_barrier(); + + if (active) { + for (uint32_t pass = 0; pass < STRESS_PASSES; pass++) { + const uint32_t offset_parts = + (cid * 7u + pass * 13u) % STRESS_BLOCKS_PER_CORE; + const uint32_t head_parts = STRESS_BLOCKS_PER_CORE - offset_parts; + const uint32_t offset_words = offset_parts * PART_WORDS; + if (head_parts > 0) { + vec_copy_parts_u32(dst + offset_words, src + offset_words, head_parts); + } + if (offset_parts > 0) { + vec_copy_parts_u32(dst, src, offset_parts); + } + } + } + + snrt_cluster_hw_barrier(); + + uint32_t errors = 0; + if (active) { + for (uint32_t block = 0; block < STRESS_BLOCKS_PER_CORE; block++) { + const uint32_t base_idx = block * PART_WORDS; + for (uint32_t w = 0; w < PART_WORDS; w++) { + const uint32_t idx = base_idx + w; + const uint32_t got = dst[idx]; + const uint32_t exp = stress_pattern(0, idx, cid); + if (got != exp) { + errors++; + } + } + } + stress_errors[cid] = errors; + } + + snrt_cluster_hw_barrier(); + if (cid == 0) { + l1d_flush(); + } + snrt_cluster_hw_barrier(); + + uint32_t result = 0; + if (cid == 0) { + uint32_t total_errors = 0; + uint32_t used_cores = (num_cores > MAX_CORES) ? MAX_CORES : num_cores; + for (uint32_t i = 0; i < used_cores; i++) { + total_errors += stress_errors[i]; + } + if (num_cores > MAX_CORES) { + printf("[WARN] vcache-stress: only first %u cores checked.\n", used_cores); + } + if (total_errors == 0) { + printf("[PASS] vcache-stress: data integrity OK.\n"); + } else { + printf("[FAIL] vcache-stress: %u mismatches.\n", total_errors); + } + result = total_errors; + } + + snrt_cluster_hw_barrier(); + return (cid == 0) ? result : 0; +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + uint32_t failures = 0; + + if (cid == 0) { + l1d_init(0); + } + snrt_cluster_hw_barrier(); + +#if CACHE_TEST_ENABLE_BASIC + if (cid == 0) { + printf("[RUN ] vcache-basic\n"); + } + if (run_basic_test() != 0) { + if (cid == 0) { + failures++; + } + } +#endif + +#if CACHE_TEST_ENABLE_STRESS + if (cid == 0) { + printf("[RUN ] vcache-stress\n"); + } + if (run_stress_test() != 0) { + if (cid == 0) { + failures++; + } + } +#endif + + if (cid == 0) { + if (failures == 0) { + printf("[PASS] vcache-tests: all enabled tests passed.\n"); + } else { + printf("[FAIL] vcache-tests: %u test group(s) failed.\n", failures); + } + } + + snrt_cluster_hw_barrier(); + return (cid == 0 && failures) ? 1 : 0; +} diff --git a/software/tests/cache-vector-rw/main.c b/software/tests/cache-vector-rw/main.c new file mode 100644 index 0000000..cc20438 --- /dev/null +++ b/software/tests/cache-vector-rw/main.c @@ -0,0 +1,295 @@ +// Copyright 2026 ETH Zurich and University of Bologna. +// SPDX-License-Identifier: Apache-2.0 +// +// Mimics the RLC consumer data-movement pattern: vector load from a source +// buffer and vector store to a destination buffer, packet by packet. +// By default only core 0 is active. Set NUM_ACTIVE_CORES to use more cores. + +#include +#include +#include +#include "printf.h" +#include + +#define MAX_CORES 4U + +// Number of cores that participate in the data movement (default: 1 = core 0 only) +#ifndef NUM_ACTIVE_CORES +#define NUM_ACTIVE_CORES 1U +#endif + +// Packet size matching the RLC consumer payload (1360 bytes = 340 words) +#define PKT_BYTES 1360U +#define WORD_BYTES 4U +#define PKT_WORDS (PKT_BYTES / WORD_BYTES) + +// Number of packets to move per core +#ifndef NUM_PKTS +#define NUM_PKTS 16U +#endif + +// Optional: flush the L1D before the vector kernel so cold-cache (miss-path) +// behavior is exercised instead of measuring buffer hits left over from the +// scalar buffer-fill warm-up. Set to 1 to enable. Default 0 preserves the +// historical measurement. +#ifndef FLUSH_BEFORE_KERNEL +#define FLUSH_BEFORE_KERNEL 0 +#endif + +// Each active core gets its own src/dst region +#define TOTAL_WORDS_PER_CORE (NUM_PKTS * PKT_WORDS) +#define TOTAL_WORDS (NUM_ACTIVE_CORES * TOTAL_WORDS_PER_CORE) +#define L1LineWidth (512 / 8) + +static uint32_t src_buf[TOTAL_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static uint32_t dst_buf[TOTAL_WORDS] __attribute__((section(".dram"))) + __attribute__((aligned(64))); +static uint32_t core_errors[MAX_CORES] __attribute__((section(".data"))); +static uint32_t core_cycles[MAX_CORES] __attribute__((section(".data"))); + +// Vector memcpy using e32/m8: mimics vec_copy_u32 from cache-rlc-mimic +void vec_copy_u32(uint32_t *dst, const uint32_t *src, + uint32_t words) { + uint32_t copied = 0; + while (copied < words) { + uint32_t avl = words - copied; + uint32_t vl = 0; + asm volatile("vsetvli %0, %1, e32, m8, ta, ma" : "=r"(vl) : "r"(avl)); + asm volatile("vle32.v v0, (%0)" : : "r"(src + copied) : "memory"); + asm volatile("vse32.v v0, (%0)" : : "r"(dst + copied) : "memory"); + copied += vl; + } +} + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + + if (cid == 0) { + l1d_init(0); + // Fill source with known pattern, clear destination + for (uint32_t i = 0; i < TOTAL_WORDS; i++) { + src_buf[i] = 0xCAFE0000u ^ i; + dst_buf[i] = 0; + } + for (uint32_t i = 0; i < MAX_CORES; i++) { + core_errors[i] = 0; + core_cycles[i] = 0; + } + } + snrt_cluster_hw_barrier(); + +#if FLUSH_BEFORE_KERNEL + // Drop the lines warmed by the scalar buffer-init loop so the vector + // kernel below starts with a cold L1D and actually runs the miss path. + // NOTE: with the flush enabled, the verify currently reports mismatches + // (cold-cache vector-store + scalar-verify path appears to have a + // pre-existing bug, unrelated to the FLUSH macro itself). Useful for + // measuring miss-path cycles, not for data-integrity checks until that + // bug is fixed. + if (cid == 0) { + l1d_flush(); + l1d_wait(); + } + snrt_cluster_hw_barrier(); +#endif + + uint32_t errs = 0; + + if (cid < NUM_ACTIVE_CORES) { + // Each core works on its own region + uint32_t *my_src = &src_buf[cid * TOTAL_WORDS_PER_CORE]; + uint32_t *my_dst = &dst_buf[cid * TOTAL_WORDS_PER_CORE]; + + // Move packets one by one: vector load src -> vector store dst + if (cid == 0) start_kernel(); + uint32_t cyc_start = benchmark_get_cycle(); + + for (uint32_t pkt = 0; pkt < NUM_PKTS; pkt++) { + uint32_t *s = &my_src[pkt * PKT_WORDS]; + uint32_t *d = &my_dst[pkt * PKT_WORDS]; + vec_copy_u32(d, s, PKT_WORDS); + } + + uint32_t cyc_end = benchmark_get_cycle(); + if (cid == 0) stop_kernel(); + + core_cycles[cid] = cyc_end - cyc_start; + + // Verify + for (uint32_t i = 0; i < TOTAL_WORDS_PER_CORE; i++) { + uint32_t got = my_dst[i]; + uint32_t exp = 0xCAFE0000u ^ (cid * TOTAL_WORDS_PER_CORE + i); + if (got != exp) { + errs++; + } + } + } + + if (cid < MAX_CORES) { + core_errors[cid] = errs; + } + snrt_cluster_hw_barrier(); + + if (cid == 0) { + uint32_t total_err = 0; + uint32_t max_cyc = 0; + for (uint32_t i = 0; i < NUM_ACTIVE_CORES; i++) { + total_err += core_errors[i]; + if (core_cycles[i] > max_cyc) max_cyc = core_cycles[i]; + } + + const uint32_t total_words = NUM_ACTIVE_CORES * TOTAL_WORDS_PER_CORE; + const uint32_t pass_words = total_words - total_err; + if (total_err == 0) { + printf("[PASS] cache-vector-rw: cores=%u pkts=%u pkt_bytes=%u total_bytes=%u " + "words_tested=%u pass=%u fail=0 cycles=%u\n", + NUM_ACTIVE_CORES, NUM_PKTS, PKT_BYTES, + NUM_ACTIVE_CORES * NUM_PKTS * PKT_BYTES, + total_words, pass_words, max_cyc); + } else { + printf("[FAIL] cache-vector-rw: errors=%u cores=%u pkts=%u pkt_bytes=%u " + "words_tested=%u pass=%u fail=%u cycles=%u\n", + total_err, NUM_ACTIVE_CORES, NUM_PKTS, PKT_BYTES, + total_words, pass_words, total_err, max_cyc); + // -- Diagnostic dump -- + // Goal: distinguish (a) load-side bugs (vle returns wrong data) from + // (b) store-side bugs (vse drops writes), and surface enough pattern + // info to grep waveforms/RTL traces for the failing addresses. + // + // Classifies errors: + // got == 0 : likely "never written" (init value). + // got == exp ^ 0x... : corrupted but probably store-derived. + // got == something_unrelated : foreign data, possibly aliasing. + // + // Cross-checks src_buf (the LOAD source) to see whether the LOAD + // path itself is returning wrong data -- if src_errs > 0, the bug + // is upstream of vec_copy's store path (probably cache refill / + // flush writeback losing init data). + const uint32_t MAX_LINES_REPORT = 32; + for (uint32_t c = 0; c < NUM_ACTIVE_CORES; c++) { + if (core_errors[c] == 0) continue; + uint32_t *c_src = &src_buf[c * TOTAL_WORDS_PER_CORE]; + uint32_t *c_dst = &dst_buf[c * TOTAL_WORDS_PER_CORE]; + + uint32_t first_err_idx = 0xFFFFFFFFu; + uint32_t first_err_got = 0, first_err_exp = 0; + uint32_t got_zero = 0, got_other = 0; + uint32_t src_errs = 0, src_zero = 0; + uint32_t first_src_err_idx = 0xFFFFFFFFu; + uint32_t first_src_err_got = 0, first_src_err_exp = 0; + for (uint32_t i = 0; i < TOTAL_WORDS_PER_CORE; i++) { + uint32_t exp = 0xCAFE0000u ^ (c * TOTAL_WORDS_PER_CORE + i); + uint32_t got_d = c_dst[i]; + if (got_d != exp) { + if (first_err_idx == 0xFFFFFFFFu) { + first_err_idx = i; first_err_got = got_d; first_err_exp = exp; + } + if (got_d == 0) got_zero++; else got_other++; + } + uint32_t got_s = c_src[i]; + if (got_s != exp) { + if (first_src_err_idx == 0xFFFFFFFFu) { + first_src_err_idx = i; first_src_err_got = got_s; first_src_err_exp = exp; + } + src_errs++; + if (got_s == 0) src_zero++; + } + } + uint32_t words_in_core = TOTAL_WORDS_PER_CORE; + printf(" [CORE %u] words=%u pass=%u fail=%u (rate=%u%%)\n", + c, words_in_core, words_in_core - core_errors[c], core_errors[c], + (words_in_core - core_errors[c]) * 100U / words_in_core); + printf(" [CORE %u] dst_errs=%u (got_zero=%u got_other=%u) src_errs=%u (got_zero=%u)\n", + c, core_errors[c], got_zero, got_other, src_errs, src_zero); + if (first_err_idx != 0xFFFFFFFFu) { + printf(" [CORE %u] first_dst_mismatch: idx=%u addr=0x%08x got=0x%08x exp=0x%08x\n", + c, first_err_idx, + (uint32_t)(uintptr_t)&c_dst[first_err_idx], + first_err_got, first_err_exp); + } + if (first_src_err_idx != 0xFFFFFFFFu) { + printf(" [CORE %u] first_src_mismatch: idx=%u addr=0x%08x got=0x%08x exp=0x%08x\n", + c, first_src_err_idx, + (uint32_t)(uintptr_t)&c_src[first_src_err_idx], + first_src_err_got, first_src_err_exp); + } + // Interpretation hints + if (src_errs == core_errors[c] && src_zero == src_errs && got_zero == core_errors[c]) { + printf(" [CORE %u] PATTERN: src and dst both read all-zero for the same indices --\n", c); + printf(" suggests dirty src_buf lines were NEVER written back to DRAM\n"); + printf(" (cache-flush writeback bug, not the vector store).\n"); + } else if (got_zero == core_errors[c] && src_errs == 0) { + printf(" [CORE %u] PATTERN: dst is all-zero on mismatches, src reads correctly --\n", c); + printf(" suggests vector store path dropped writes (store-side bug).\n"); + } else if (got_other > 0) { + printf(" [CORE %u] PATTERN: %u mismatches have non-zero, non-expected got --\n", + c, got_other); + printf(" possible data-corruption / aliasing / forwarding bug.\n"); + } + // Per-cache-line totals: how many lines passed fully vs. partially + // failed vs. failed completely. Separate counts for src and dst. + uint32_t lines_total = (TOTAL_WORDS_PER_CORE + 15) / 16; + uint32_t s_full_ok = 0, s_partial = 0, s_all_wrong = 0; + uint32_t d_full_ok = 0, d_partial = 0, d_all_wrong = 0; + for (uint32_t line = 0; line < lines_total; line++) { + uint32_t s_mask = 0, d_mask = 0; + uint32_t in_line = 16; + if (line * 16 + in_line > TOTAL_WORDS_PER_CORE) + in_line = TOTAL_WORDS_PER_CORE - line * 16; + uint32_t full = (in_line == 16) ? 0xFFFFu : ((1u << in_line) - 1); + for (uint32_t w = 0; w < in_line; w++) { + uint32_t i = line * 16 + w; + uint32_t exp = 0xCAFE0000u ^ (c * TOTAL_WORDS_PER_CORE + i); + if (c_src[i] == exp) s_mask |= (1u << w); + if (c_dst[i] == exp) d_mask |= (1u << w); + } + if (s_mask == full) s_full_ok++; + else if (s_mask == 0) s_all_wrong++; + else s_partial++; + if (d_mask == full) d_full_ok++; + else if (d_mask == 0) d_all_wrong++; + else d_partial++; + } + printf(" [CORE %u] lines_total=%u src_lines: full_ok=%u partial=%u all_wrong=%u " + "dst_lines: full_ok=%u partial=%u all_wrong=%u\n", + c, lines_total, + s_full_ok, s_partial, s_all_wrong, + d_full_ok, d_partial, d_all_wrong); + + // Per-cache-line summary: src_ok_mask + dst_ok_mask per 16-word line. + // Lets the reviewer spot stride / periodic patterns at a glance. + printf(" [CORE %u] per-line {src_ok_mask, dst_ok_mask} (first %u failing lines):\n", + c, MAX_LINES_REPORT); + uint32_t reported = 0; + for (uint32_t line = 0; line < lines_total && reported < MAX_LINES_REPORT; line++) { + uint32_t s_mask = 0, d_mask = 0; + uint32_t in_line = 16; + if (line * 16 + in_line > TOTAL_WORDS_PER_CORE) + in_line = TOTAL_WORDS_PER_CORE - line * 16; + for (uint32_t w = 0; w < in_line; w++) { + uint32_t i = line * 16 + w; + uint32_t exp = 0xCAFE0000u ^ (c * TOTAL_WORDS_PER_CORE + i); + if (c_src[i] == exp) s_mask |= (1u << w); + if (c_dst[i] == exp) d_mask |= (1u << w); + } + uint32_t full = (in_line == 16) ? 0xFFFFu : ((1u << in_line) - 1); + if (s_mask != full || d_mask != full) { + printf(" line %3u (base_idx=%u, dst_addr=0x%08x): src_ok=0x%04x dst_ok=0x%04x\n", + line, line * 16, + (uint32_t)(uintptr_t)&c_dst[line * 16], + s_mask, d_mask); + reported++; + } + } + if (reported == MAX_LINES_REPORT) + printf(" [CORE %u] ... (more failing lines truncated)\n", c); + } + } + + l1d_flush(); + return (int)total_err; + } + + return 0; +} diff --git a/software/tests/fft-32b/data/data_1024_4.h b/software/tests/fft-32b/data/data_1024_4.h new file mode 100644 index 0000000..9a7d305 --- /dev/null +++ b/software/tests/fft-32b/data/data_1024_4.h @@ -0,0 +1,22 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// This file was generated automatically. + +static uint32_t NFFT = 1024; +static uint32_t NTWI_P1 = 768; +static uint32_t NTWI_P2 = 1024; +static uint32_t NTWI_TOT = 1792; +static uint32_t log2_nfft = 10; +static uint32_t log2_nfft1 = 2; +static uint32_t log2_nfft2 = 8; +static uint32_t active_cores = 4; + +float out[2048] __attribute__((section(".pdcp_src"))) = { [0 ... 2047] = 0 }; +static float samples_dram[2048] __attribute__((section(".pdcp_src"))) = {0.49671414494514465, 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-2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16, -2.4492937051703357e-16}; +static uint16_t store_idx_dram[896] __attribute__((section(".pdcp_src"))) = {0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188, 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700, 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252, 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764, 0, 4, 8, 12, 16, 20, 24, 28, 512, 516, 520, 524, 528, 532, 536, 540, 32, 36, 40, 44, 48, 52, 56, 60, 544, 548, 552, 556, 560, 564, 568, 572, 64, 68, 72, 76, 80, 84, 88, 92, 576, 580, 584, 588, 592, 596, 600, 604, 96, 100, 104, 108, 112, 116, 120, 124, 608, 612, 616, 620, 624, 628, 632, 636, 128, 132, 136, 140, 144, 148, 152, 156, 640, 644, 648, 652, 656, 660, 664, 668, 160, 164, 168, 172, 176, 180, 184, 188, 672, 676, 680, 684, 688, 692, 696, 700, 192, 196, 200, 204, 208, 212, 216, 220, 704, 708, 712, 716, 720, 724, 728, 732, 224, 228, 232, 236, 240, 244, 248, 252, 736, 740, 744, 748, 752, 756, 760, 764, 0, 4, 8, 12, 512, 516, 520, 524, 16, 20, 24, 28, 528, 532, 536, 540, 32, 36, 40, 44, 544, 548, 552, 556, 48, 52, 56, 60, 560, 564, 568, 572, 64, 68, 72, 76, 576, 580, 584, 588, 80, 84, 88, 92, 592, 596, 600, 604, 96, 100, 104, 108, 608, 612, 616, 620, 112, 116, 120, 124, 624, 628, 632, 636, 128, 132, 136, 140, 640, 644, 648, 652, 144, 148, 152, 156, 656, 660, 664, 668, 160, 164, 168, 172, 672, 676, 680, 684, 176, 180, 184, 188, 688, 692, 696, 700, 192, 196, 200, 204, 704, 708, 712, 716, 208, 212, 216, 220, 720, 724, 728, 732, 224, 228, 232, 236, 736, 740, 744, 748, 240, 244, 248, 252, 752, 756, 760, 764, 0, 4, 512, 516, 8, 12, 520, 524, 16, 20, 528, 532, 24, 28, 536, 540, 32, 36, 544, 548, 40, 44, 552, 556, 48, 52, 560, 564, 56, 60, 568, 572, 64, 68, 576, 580, 72, 76, 584, 588, 80, 84, 592, 596, 88, 92, 600, 604, 96, 100, 608, 612, 104, 108, 616, 620, 112, 116, 624, 628, 120, 124, 632, 636, 128, 132, 640, 644, 136, 140, 648, 652, 144, 148, 656, 660, 152, 156, 664, 668, 160, 164, 672, 676, 168, 172, 680, 684, 176, 180, 688, 692, 184, 188, 696, 700, 192, 196, 704, 708, 200, 204, 712, 716, 208, 212, 720, 724, 216, 220, 728, 732, 224, 228, 736, 740, 232, 236, 744, 748, 240, 244, 752, 756, 248, 252, 760, 764, 0, 512, 4, 516, 8, 520, 12, 524, 16, 528, 20, 532, 24, 536, 28, 540, 32, 544, 36, 548, 40, 552, 44, 556, 48, 560, 52, 564, 56, 568, 60, 572, 64, 576, 68, 580, 72, 584, 76, 588, 80, 592, 84, 596, 88, 600, 92, 604, 96, 608, 100, 612, 104, 616, 108, 620, 112, 624, 116, 628, 120, 632, 124, 636, 128, 640, 132, 644, 136, 648, 140, 652, 144, 656, 148, 660, 152, 664, 156, 668, 160, 672, 164, 676, 168, 680, 172, 684, 176, 688, 180, 692, 184, 696, 188, 700, 192, 704, 196, 708, 200, 712, 204, 716, 208, 720, 212, 724, 216, 728, 220, 732, 224, 736, 228, 740, 232, 744, 236, 748, 240, 752, 244, 756, 248, 760, 252, 764}; +static uint32_t coffset_dram[4] __attribute__((section(".pdcp_src"))) = {0, 2, 1, 3}; +static float gold_out_dram[2048] __attribute__((section(".pdcp_src"))) = {30.38982582092285, 52.4919319152832, -64.93447875976562, -1.7994935512542725, 0.5312617421150208, -11.845783233642578, -11.25826358795166, -26.447200775146484, 18.520246505737305, 0.6710554957389832, -16.224323272705078, 24.73272132873535, 10.500828742980957, -25.005104064941406, 26.375139236450195, 55.130855560302734, -52.98527145385742, -99.55455017089844, -47.792816162109375, -6.361907482147217, 30.096248626708984, -2.7359507083892822, 14.0851469039917, 19.43863868713379, -10.215001106262207, 19.262540817260742, 36.93578338623047, -10.241194725036621, 16.08917808532715, 35.28187942504883, -34.48371124267578, -44.1446533203125, 7.031262397766113, 15.094441413879395, -37.46671676635742, -25.160749435424805, 19.66892433166504, -15.162410736083984, 1.7627214193344116, -13.169831275939941, 2.640871286392212, 56.30009841918945, 29.235185623168945, -0.20921719074249268, 59.452980041503906, 14.55429744720459, -42.06559753417969, -34.07062911987305, 5.642068862915039, 10.124176979064941, -21.290016174316406, 48.547088623046875, -17.803701400756836, 47.41735076904297, -1.9549849033355713, 20.87868881225586, 24.24578857421875, -10.6095609664917, -7.647822380065918, 23.013660430908203, 10.564753532409668, 24.62432289123535, -32.91133117675781, -37.923274993896484, -63.3153076171875, 59.79908752441406, 32.5206413269043, 6.885171413421631, 47.8851203918457, 46.53282928466797, 8.29708480834961, 10.517952919006348, -35.673336029052734, 12.65208625793457, 44.865882873535156, 50.411102294921875, -15.788732528686523, 28.244199752807617, 37.3781623840332, -24.202985763549805, -0.9476199746131897, 10.923133850097656, 14.70875072479248, -7.117061138153076, -19.048194885253906, 10.194897651672363, -0.5000114440917969, 26.742921829223633, 16.668960571289062, 16.601890563964844, -28.44013023376465, 9.216577529907227, -61.959022521972656, 8.689881324768066, -59.160404205322266, 22.489295959472656, -13.145289421081543, 2.0621449947357178, -41.792293548583984, 13.847508430480957, 18.123571395874023, -25.779977798461914, -8.8235445022583, -19.640066146850586, -15.772799491882324, -16.128557205200195, 32.49431228637695, -14.874480247497559, -13.077047348022461, -76.86676025390625, -7.0281453132629395, -18.541208267211914, -7.931278228759766, -18.801408767700195, 2.3116352558135986, -12.461540222167969, -9.771621704101562, 48.87181091308594, 2.9966838359832764, 11.987529754638672, 41.06984329223633, -0.656406581401825, -15.131464004516602, 15.745871543884277, -24.96202278137207, 5.901882171630859, 7.707090377807617, -0.39422470331192017, -13.195484161376953, -13.689674377441406, 34.5557975769043, -14.024221420288086, 1.75620436668396, 11.214133262634277, 5.420673370361328, 7.923540115356445, -42.82963943481445, 31.217769622802734, 26.464149475097656, -37.962799072265625, 1.0532405376434326, 23.370512008666992, 27.696449279785156, -42.4349365234375, 14.32654094696045, 37.48066329956055, 60.23787307739258, -15.290885925292969, -13.5526704788208, -5.286037445068359, -1.9566154479980469, 9.97933578491211, 11.69211196899414, -59.29701614379883, -31.946958541870117, -7.0449113845825195, 0.10742989182472229, 53.75153732299805, -11.005261421203613, -12.975703239440918, 55.6136360168457, -16.436023712158203, 27.2010498046875, 11.47144603729248, 21.080028533935547, -4.693336486816406, 29.30329704284668, 54.52040100097656, -8.780407905578613, -19.507801055908203, -0.46806415915489197, -12.679871559143066, -15.400189399719238, -29.88102149963379, -29.991455078125, 21.243152618408203, 4.321026802062988, 49.437225341796875, 4.519831657409668, -12.947175025939941, -17.565690994262695, 42.90678024291992, -8.986313819885254, -32.34327697753906, 37.24126052856445, 6.002228260040283, 76.4384765625, -10.62026596069336, -31.652902603149414, 15.59207534790039, -9.385394096374512, 20.425416946411133, -1.0460917949676514, 23.328327178955078, -29.29788589477539, -1.8601490259170532, 20.78265953063965, -6.868046283721924, 57.955963134765625, -20.11995506286621, 113.62064361572266, -62.55335998535156, -29.784683227539062, -30.134836196899414, -8.201340675354004, 45.741783142089844, 35.43132400512695, 3.5757229328155518, -2.478344678878784, -35.13006591796875, -0.09553336352109909, -32.14924240112305, -15.91334056854248, 38.3219108581543, -16.987844467163086, -32.09724807739258, 10.645455360412598, -23.5710506439209, 7.691153526306152, -17.434438705444336, -24.95379638671875, -14.95767593383789, -36.87055969238281, 12.141437530517578, 35.84382247924805, -4.6027703285217285, 14.628016471862793, 41.059242248535156, -29.088821411132812, 22.542856216430664, 6.5376458168029785, 27.467527389526367, 25.22661590576172, -33.7064094543457, 33.95758819580078, 61.205997467041016, -20.3825626373291, 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-4.822878360748291, 7.919955730438232, 35.98277282714844, -30.89478302001953, -32.40855026245117, 31.27412223815918, -45.20038986206055, 20.97939109802246, -38.077110290527344, 32.18363571166992, -11.242378234863281, -23.64359474182129, -9.223494529724121, 12.907135009765625, -54.31597900390625, -74.0955810546875, 22.661630630493164, 25.90481948852539, 16.636436462402344, -21.157875061035156, -14.36279010772705}; diff --git a/software/tests/fft-32b/script/fft_1024_4.json b/software/tests/fft-32b/script/fft_1024_4.json new file mode 100644 index 0000000..224cc29 --- /dev/null +++ b/software/tests/fft-32b/script/fft_1024_4.json @@ -0,0 +1,5 @@ +{ + npoints: 1024, + ncores: 4, + prec: 32 +} diff --git a/software/tests/idotp-32b/main.c b/software/tests/idotp-32b/main.c index bbd21ce..e26378c 100644 --- a/software/tests/idotp-32b/main.c +++ b/software/tests/idotp-32b/main.c @@ -143,7 +143,7 @@ int main() { if (cid == 0) { if (result[0] != dotp_result_golden*measure_iter) { - printf("Check Failed!\n"); + printf("Check Failed!, got %d, expected %d\n", result[0], dotp_result_golden*measure_iter); } #ifdef DEBUG printf("gold results:%d\n", dotp_result_golden); diff --git a/software/tests/mcs-lock/main.c b/software/tests/mcs-lock/main.c index b273d81..863eeb7 100644 --- a/software/tests/mcs-lock/main.c +++ b/software/tests/mcs-lock/main.c @@ -188,12 +188,14 @@ int main(void) { spin_unlock(&test_spin_lock, 0); #endif - if(core_id != 0) { - while(1){} - } - // Wait for all cores to finish snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception + // (Previously non-zero cores spun in while(1) here and the second + // barrier below then dead-locked core 0 — it waited for cores 1+ to + // reach the barrier, but they were trapped in the infinite loop. + // Just let every core return; the runtime's _snrt_exit triggers + // set_eoc only on core 0 anyway, and the other cores halt cleanly.) + return 0; } diff --git a/software/tests/minimal-tile0-repro/main.c b/software/tests/minimal-tile0-repro/main.c new file mode 100644 index 0000000..6a3dc69 --- /dev/null +++ b/software/tests/minimal-tile0-repro/main.c @@ -0,0 +1,39 @@ +// Minimal multi-tile bug repro -- absolutely no printf, no library. +// +// Only core 0 does anything: write 16 words to a single cache line in +// DRAM, then read them back, count mismatches. Communicate the error +// count via the return value -- it gets shifted into the tohost EOC +// value by the runtime, so a non-zero retval == sim retval != 0. + +#include +#include +#include + +#define LINE_BYTES 64U +#define WORDS_PER_LINE (LINE_BYTES / 4) +#define L1LineWidth 64 + +static uint32_t line_buf[WORDS_PER_LINE] __attribute__((section(".dram"))) + __attribute__((aligned(LINE_BYTES))) = { 0 }; + +int main() { + const uint32_t cid = snrt_cluster_core_idx(); + + if (cid != 0) return 0; + + l1d_flush(); + uint32_t offset = 31 - __builtin_clz(L1LineWidth); + l1d_xbar_config(offset); + + volatile uint32_t *buf = line_buf; + + for (uint32_t w = 0; w < WORDS_PER_LINE; ++w) + buf[w] = 0xA5A50000u | w; + + uint32_t errs = 0; + for (uint32_t w = 0; w < WORDS_PER_LINE; ++w) { + if (buf[w] != (0xA5A50000u | w)) ++errs; + } + + return (int)errs; +} diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/llist.h b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/llist.h index 08044d1..62d4bcb 100644 --- a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/llist.h +++ b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/llist.h @@ -38,6 +38,12 @@ static inline void spin_lock(spinlock_t *lock, int cycle) { } static inline void spin_unlock(volatile int *lock, int cycle) { + // Release fence: with commit-accurate write responses (cache Option A), + // `fence` drains all prior stores to COMMIT (lsu_empty) before the unlock + // store becomes visible, so a later core that acquires the lock sees the + // critical-section data. (Snitch ignores the .rl AMO bit, hence an explicit + // fence rather than amoswap.w.rl.) + asm volatile ("fence rw, rw" ::: "memory"); asm volatile ( "amoswap.w zero, zero, %0" : "+A" (*lock) diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/mm.c b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/mm.c index 523f4a2..c130491 100644 --- a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/mm.c +++ b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/mm.c @@ -34,6 +34,9 @@ static inline void mm_lock_acquire(volatile int *lock) { } static inline void mm_lock_release(volatile int *lock) { + // Release fence (cache Option A): drain prior stores to COMMIT before the + // unlock store is visible (see spin_unlock in llist.h). + asm volatile ("fence rw, rw" ::: "memory"); asm volatile ( "amoswap.w zero, zero, %0" : "+A" (*lock) diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/printf_lock.c b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/printf_lock.c index a285bd1..6b552d0 100644 --- a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/printf_lock.c +++ b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/printf_lock.c @@ -28,6 +28,9 @@ static inline void printf_lock_acquire(volatile int *lock) { } static inline void printf_lock_release(volatile int *lock) { + // Release fence (cache Option A): drain prior stores to COMMIT before the + // unlock store is visible (see spin_unlock in llist.h). + asm volatile ("fence rw, rw" ::: "memory"); asm volatile ( "amoswap.w zero, zero, %0" : "+A" (*lock) diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.c b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.c index dad7f18..f3a8890 100644 --- a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.c +++ b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.c @@ -242,17 +242,16 @@ static void consumer(const unsigned int core_id) { // scalar_memcpy32_32bit_unrolled(node->tgt, node->data, node->data_size); // vector_memcpy32_m8_m4_general_opt(node->tgt, node->data, node->data_size); // vector_memcpy32_1360B_opt(node->tgt, node->data); - vector_memcpy32_1360B_opt_with_header(node->tgt, node->data, rlc_ctx.vtNext); + // Atomically allocate a unique RLC sequence number for this PDU and + // use it as the header. fetch_add returns the pre-increment value, + // so each consumer gets a distinct SN (safe for multiple consumers). + uint32_t sn = atomic_fetch_add_explicit(&rlc_ctx.vtNext, 1, memory_order_relaxed); + vector_memcpy32_1360B_opt_with_header(node->tgt, node->data, sn); // timer_mv_1 = benchmark_get_cycle(); - // Update the RLC struct variables - // atomic_fetch_add_explicit(&rlc_ctx.pduWithoutPoll, 1, memory_order_relaxed); - // atomic_fetch_add_explicit(&rlc_ctx.byteWithoutPoll, node->data_size, memory_order_relaxed); - rlc_ctx.pduWithoutPoll += 1; - rlc_ctx.byteWithoutPoll += node->data_size; - // Increment the next available RLC sequence number - rlc_ctx.vtNext += 1; - // atomic_fetch_add_explicit(&rlc_ctx.vtNext, 1, memory_order_relaxed); + // Update the RLC stats atomically (shared across multiple consumers). + atomic_fetch_add_explicit(&rlc_ctx.pduWithoutPoll, 1, memory_order_relaxed); + atomic_fetch_add_explicit(&rlc_ctx.byteWithoutPoll, node->data_size, memory_order_relaxed); // DEBUG_PRINTF_LOCK_ACQUIRE(&printf_lock); @@ -395,14 +394,11 @@ void cluster_entry(const unsigned int core_id) { start_kernel(); } - if (core_id >= 2) { + if (core_id < 2) { consumer(core_id); - } else /*if (core_id == 0)*/ { + } else { producer(core_id); - }/* else { - while (1) {} - }*/ - // consumer(core_id); + } snrt_cluster_hw_barrier(); // this can trigger Misaligned Load exception diff --git a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.h b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.h index 62f259a..4894d23 100644 --- a/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.h +++ b/software/tests/multi_producer_single_consumer_double_linked_list/kernel/rlc.h @@ -66,8 +66,8 @@ typedef struct { unsigned int cellId __attribute__((aligned(4))); /* Indicates the cell to which the RLC entity belongs.*/ _Atomic unsigned int pollPdu __attribute__((aligned(4))); _Atomic unsigned int pollByte __attribute__((aligned(4))); - unsigned int pduWithoutPoll __attribute__((aligned(4))); /* Indicates the total number of PDUs that are not polled. */ - unsigned int byteWithoutPoll __attribute__((aligned(4))); /* Indicates the total bytes of PDUs that are not polled. */ + _Atomic unsigned int pduWithoutPoll __attribute__((aligned(4))); /* Indicates the total number of PDUs that are not polled. */ + _Atomic unsigned int byteWithoutPoll __attribute__((aligned(4))); /* Indicates the total bytes of PDUs that are not polled. */ // unsigned int sduNum; /* Number of sdus to be sent */ // unsigned int sduBytes; /* Number of sdus bytes to be sent */ @@ -77,7 +77,7 @@ typedef struct { char Reserve1[CACHE_LINE_SIZE-6-sizeof(LinkedList)] __attribute__((aligned(4))); /* Reserved for future use, pieced into a cacheline */ _Atomic unsigned int vtNextAck __attribute__((aligned(4))); /* First SN to be confirmed */ - unsigned int vtNext __attribute__((aligned(4))); /* Next Available RLCSN */ + _Atomic unsigned int vtNext __attribute__((aligned(4))); /* Next Available RLCSN */ // unsigned int sendPduNum; /* Number of pdus to be confirmed */ // unsigned int sendPduBytes; /* Number of pdus to be confirmed */ // void *waitAckLinkHdr; /* First SDU to be confirmed */ diff --git a/util/lint/script/lint.tcl b/util/lint/script/lint.tcl index 843fb66..d415579 100644 --- a/util/lint/script/lint.tcl +++ b/util/lint/script/lint.tcl @@ -60,7 +60,6 @@ waive -rule "FlopEConst" waive -rule "W416" # Assert not synthesizable waive -rule "SYNTH_5064" - # Set lint_rtl goal and run current_goal lint/lint_rtl run_goal