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DMA status check The ASPEED I3C controller reuses the PIO FIFO in DMA mode. When transfer errors or aborts occur, the interrupt may be raised before the DMA engine completes the transfer, leading to potential data corruption if the FIFO is reset immediately. Add aspeed_pio_fifo_reset() function that: - Polls WDMA_DBG_LO and RDMA_DBG_LO registers for I3C_DMA_DBG_LO_BUSY bit - Uses readl_poll_timeout_atomic() with 100ms timeout for reliable polling - Only resets PIO FIFOs after confirming DMA engines are idle - Replaces direct FIFO reset calls on transfer aborts Also add DMA debug register definitions and status bit masks to vendor_aspeed.h to support the polling mechanism. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
for ASPEED The ASPEED I3C controller reuses PIO FIFO in DMA mode, but transfer errors were not clearing the FIFO properly. This causes data corruption issues when sending consecutive Regular Data Transfer Commands. When the first transfer gets NACKed, its data remains in the PIO FIFO. Without clearing the FIFO, subsequent transfers will: - Read shifted/stale data from the previous failed transfer - Reuse corrupted data leading to incorrect transfer results Add aspeed_pio_fifo_reset() call on INTR_TRANSFER_ERR to ensure the PIO FIFO is properly cleared before the controller is resumed. This prevents data contamination between transfers and ensures data integrity for subsequent operations. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
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aspeed fixes to reset the DMA FIFO buffers in case of errors.