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Pull requests: OpenXiangShan/GEM5
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arch-riscv: Add an assert for vector splitting.
rvv
#840
opened Apr 22, 2026 by
jueshiwenli
Collaborator
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arch-riscv,cpu-o3,mem-cache: add memblock PMU stats
#831
opened Apr 15, 2026 by
Ergou-ren
Collaborator
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[codex] Enable MBTB VC16 and approximate dense-block interflush
#826
opened Apr 13, 2026 by
jensen-yan
Collaborator
•
Draft
Refs/heads/tage size align repeat index fill align
#824
opened Apr 13, 2026 by
CJ362ff
Contributor
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Tracking legacy resolve train feature performance
do not merge
perf
#823
opened Apr 10, 2026 by
Yakkhini
Collaborator
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cpu,arch-riscv,cpu-o3,bpu: align control-PC semantics, fetch coverage, and owner migration
perf
#805
opened Mar 22, 2026 by
Lingrui98
Contributor
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configs: reduce UARTLite console PIO latency for Xiangshan bare-metal runs
#789
opened Mar 12, 2026 by
jensen-yan
Collaborator
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mem: remove duplicated trainning req of prefetcher
perf
#777
opened Mar 9, 2026 by
happy-lx
Contributor
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cpu-o3: Add replayed load completion counter
#765
opened Feb 27, 2026 by
happy-lx
Contributor
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