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Rename SimMemAccess to SimDataAccess - #28

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kristinas merged 3 commits into
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kristina-halted-case
Nov 7, 2026
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kristinas merged 3 commits into
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kristina-halted-case

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The simulator's memory stage holds only data accesses, so SimMemAccess read like a counterpart of Core.Pipeline.MemAccess, which includes fetches. SimNoAccess was also easy to confuse with the observation NoAccess, which means the bus shows nothing.

kristinas and others added 3 commits November 7, 2026 14:36
The simulator's memory stage holds only data accesses, so SimMemAccess
read like a counterpart of Core.Pipeline.MemAccess, which includes
fetches. SimNoAccess was also easy to confuse with the observation
NoAccess, which means the bus shows nothing.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The Boolean in SimCachedSys says whether the simulator is ready to
receive an input. Describing it as "the cache answered in the previous
cycle" needed a made-up justification for its initial value True,
since nothing has answered before the start. The field is now
simCachedReady, and the comments on the type, its initial state and
its step describe it as readiness.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…mments

The invariant and driver of link 2's leakage half still described the
flag as "the last cycle brought an answer". They now call it readiness
to receive an input, as the simulator itself does.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@kristinas
kristinas merged commit 254f24b into main Nov 7, 2026
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