Merge to tag jdk-28+22

.gitignore

@@ -17,8 +17,10 @@ NashornProfile.txt
 **/JTwork/**
 /src/utils/LogCompilation/target/
 /src/utils/LogCompilation/logc.jar
-/.project/
-/.settings/
+**/.classpath
+**/.factorypath
+**/.project
+**/.settings/
 /compile_commands.json
 /.cache
 /.gdbinit

make/hotspot/lib/CompileJvm.gmk

@@ -207,6 +207,7 @@ $(eval $(call SetupJdkLibrary, BUILD_LIBJVM, \
     DISABLED_WARNINGS_gcc_jvmFlag.cpp := unused-const-variable, \
     DISABLED_WARNINGS_gcc_jvmtiTagMap.cpp := stringop-overflow, \
     DISABLED_WARNINGS_gcc_macroAssembler_ppc_sha.cpp := unused-const-variable, \
+    DISABLED_WARNINGS_gcc_mountUnmountDisabler.cpp := stringop-overflow, \
     DISABLED_WARNINGS_gcc_postaloc.cpp := address, \
     DISABLED_WARNINGS_gcc_safepointMechanism.cpp := stringop-overflow, \
     DISABLED_WARNINGS_gcc_shenandoahGenerationalHeap.cpp := stringop-overflow, \

make/hotspot/lib/JvmFeatures.gmk

@@ -121,10 +121,7 @@ ifneq ($(call check-jvm-feature, cds), true)
   JVM_CFLAGS_FEATURES += -DINCLUDE_CDS=0
   JVM_EXCLUDE_FILES += \
       aotCodeCache.cpp \
-      classLoaderDataShared.cpp \
-      classLoaderExt.cpp \
       aotCompileBroker.cpp \
-      systemDictionaryShared.cpp \
       trainingData.cpp
   JVM_EXCLUDE_PATTERNS += cds/
 endif

make/jdk/src/classes/build/tools/intpoly/FieldGen.java

@@ -88,24 +88,6 @@ private static List<CarryReduce> P256CrSequence() {
         return result;
     }
 
-    static FieldParams P384 = new FieldParams(
-            "IntegerPolynomialP384", 28, 14, 2, 384,
-            Arrays.asList(
-                    new Term(128, -1),
-                    new Term(96, -1),
-                    new Term(32, 1),
-                    new Term(0, -1)
-            ),
-            P384CrSequence(), simpleSmallCrSequence(14)
-    );
-
-    private static List<CarryReduce> P384CrSequence() {
-        List<CarryReduce> result = new ArrayList<CarryReduce>();
-        result.addAll(fullReduce(14));
-        result.addAll(simpleSmallCrSequence(14));
-        return result;
-    }
-
     static FieldParams P521 = new FieldParams(
             "IntegerPolynomialP521", 28, 19, 2, 521,
             Arrays.asList(
@@ -194,7 +176,7 @@ private static List<CarryReduce> orderFieldSmallCrSequence(int numLimbs) {
     }
 
     static final FieldParams[] ALL_FIELDS = {
-            Curve448, P256, P384, P521, O256, O384, O521, O25519, O448
+            Curve448, P256, P521, O256, O384, O521, O25519, O448
     };
 
     public static class Term {

src/hotspot/cpu/aarch64/aarch64.ad

@@ -1701,6 +1701,34 @@ int MachCallRuntimeNode::ret_addr_offset() const {
 
 //=============================================================================
 
+void MachUncommonTrapNode::emit_impl(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
+  address entry_point = OptoRuntime::uncommon_trap_blob()->entry_point();
+  address runtime_call = __ trampoline_call(Address(entry_point, relocInfo::runtime_call_type));
+  if (runtime_call == nullptr) {
+    ciEnv::current()->record_failure("Failed to emit uncommon trap trampoline call");
+    return;
+  }
+
+  __ emit_int32(trap_request());
+}
+
+uint MachUncommonTrapNode::size_impl(PhaseRegAlloc* ra_) const {
+  // BL followed by 32-bit integer constant.
+  //
+  // If target address cannot be directly encoded into the BL,
+  // a trampoline in the stub code will be emitted and used to reach
+  // the uncommon trap blob, similarly to trampolines for static calls
+  // into compiled Java methods. The size of the trampoline is
+  // accounted for separately.
+  return NativeInstruction::instruction_size + sizeof(int32_t);
+}
+
+int MachUncommonTrapNode::ret_addr_offset_impl() const {
+  return NativeInstruction::instruction_size;
+}
+
+//=============================================================================
+
 #ifndef PRODUCT
 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
   st->print("BREAKPOINT");
@@ -3657,10 +3685,16 @@ encode %{
       }
     }
 
-    __ post_call_nop();
+    int trap_request;
+    bool is_trap = is_uncommon_trap(&trap_request);
+    if (is_trap) {
+      __ emit_int32(trap_request);
+    } else {
+      __ post_call_nop();
+    }
 
     // Only non uncommon_trap calls need to reinitialize ptrue.
-    if (Compile::current()->max_vector_size() > 0 && uncommon_trap_request() == 0) {
+    if (Compile::current()->max_vector_size() > 0 && !is_trap) {
       __ reinitialize_ptrue();
     }
   %}
@@ -9315,21 +9349,6 @@ instruct subI_reg_reg(iRegINoSp dst, iRegIorL2I src1, iRegIorL2I src2) %{
   ins_pipe(ialu_reg_reg);
 %}
 
-// Immediate Subtraction
-instruct subI_reg_imm(iRegINoSp dst, iRegIorL2I src1, immIAddSub src2) %{
-  match(Set dst (SubI src1 src2));
-
-  ins_cost(INSN_COST);
-  format %{ "subw $dst, $src1, $src2" %}
-
-  // use opcode to indicate that this is a sub not an add
-  opcode(0x1);
-
-  ins_encode(aarch64_enc_addsubw_imm(dst, src1, src2));
-
-  ins_pipe(ialu_reg_imm);
-%}
-
 // Long Subtraction
 instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
 
@@ -9347,21 +9366,6 @@ instruct subL_reg_reg(iRegLNoSp dst, iRegL src1, iRegL src2) %{
   ins_pipe(ialu_reg_reg);
 %}
 
-// No constant pool entries requiredLong Immediate Subtraction.
-instruct subL_reg_imm(iRegLNoSp dst, iRegL src1, immLAddSub src2) %{
-  match(Set dst (SubL src1 src2));
-
-  ins_cost(INSN_COST);
-  format %{ "sub$dst, $src1, $src2" %}
-
-  // use opcode to indicate that this is a sub not an add
-  opcode(0x1);
-
-  ins_encode( aarch64_enc_addsub_imm(dst, src1, src2) );
-
-  ins_pipe(ialu_reg_imm);
-%}
-
 // Integer Negation (special case for sub)
 
 instruct negI_reg(iRegINoSp dst, iRegIorL2I src, immI0 zero, rFlagsReg cr) %{

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp

@@ -498,6 +498,7 @@ void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
       Label not_null;
       __ cbnz(r0, not_null);
       // Returned value is null, zero all return registers because they may belong to oop fields
+      __ mov(j_rarg0, zr);
       __ mov(j_rarg1, zr);
       __ mov(j_rarg2, zr);
       __ mov(j_rarg3, zr);
@@ -2415,7 +2416,7 @@ void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
   }
 
   // if we don't know anything, just go through the generic arraycopy
-  if (default_type == nullptr // || basic_type == T_OBJECT
+  if (default_type == nullptr || !default_type->is_loaded() // || basic_type == T_OBJECT
       ) {
     Label done;
     assert(src == r1 && src_pos == r2, "mismatch in calling convention");

src/hotspot/cpu/aarch64/c1_LIRGenerator_aarch64.cpp

@@ -1173,7 +1173,8 @@ void LIRGenerator::do_NewObjectArray(NewObjectArray* x) {
   // in case of patching (i.e., object class is not yet loaded), we need to reexecute the instruction
   // and therefore provide the state before the parameters have been consumed
   CodeEmitInfo* patching_info = nullptr;
-  if (!x->klass()->is_loaded() || PatchALot) {
+  ciKlass* obj = ciObjArrayKlass::make(x->klass());
+  if (!x->klass()->is_loaded() || !obj->is_loaded() || PatchALot) {
     patching_info =  state_for(x, x->state_before());
   }
 
@@ -1189,15 +1190,13 @@ void LIRGenerator::do_NewObjectArray(NewObjectArray* x) {
   length.load_item_force(FrameMap::r19_opr);
   LIR_Opr len = length.result();
 
-  ciKlass* obj = ciObjArrayKlass::make(x->klass());
-
   // TODO 8265122 Implement a fast path for this
   bool is_flat = obj->is_loaded() && obj->is_flat_array_klass();
   bool is_null_free = obj->is_loaded() && obj->as_array_klass()->is_elem_null_free();
 
   CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info, is_null_free);
-  if (obj == ciEnv::unloaded_ciobjarrayklass()) {
-    BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
+  if (x->klass()->is_loaded() && !obj->is_loaded()) {
+    BAILOUT("encountered unloaded ciobjarrayklass due to out of memory error");
   }
 
   klass2reg_with_patching(klass_reg, obj, patching_info);

src/hotspot/cpu/aarch64/frame_aarch64.cpp

@@ -106,6 +106,13 @@ bool frame::safe_for_sender(JavaThread *thread) {
       if (_cb->is_nmethod() || _cb->is_adapter_blob() || _cb->is_runtime_stub()) {
         return false;
       }
+
+      if (_cb->is_uncommon_trap_stub() &&
+          !(thread->has_last_Java_frame() && thread->frame_anchor()->walkable())) {
+        // The frame might not be safe to walk when the frame anchor is missing.
+        // For example, RegisterSaver adjusts the stack pointer as it spills the registers.
+        return false;
+      }
     }
 
     // Could just be some random pointer within the codeBlob

src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.ad

@@ -633,33 +633,6 @@ instruct g1CompareAndSwapNAcq(iRegINoSp res, indirect mem, iRegN newval, iRegPNo
   ins_pipe(pipe_slow);
 %}
 
-// This pattern is generated automatically from g1_aarch64.m4.
-// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-instruct g1GetAndSetP(indirect mem, iRegP newval, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp preval, rFlagsReg cr)
-%{
-  predicate(UseG1GC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() != 0);
-  match(Set preval (GetAndSetP mem newval));
-  effect(TEMP preval, TEMP tmp1, TEMP tmp2, KILL cr);
-  ins_cost(2 * VOLATILE_REF_COST);
-  format %{ "atomic_xchg  $preval, $newval, [$mem]" %}
-  ins_encode %{
-    assert_different_registers($mem$$Register, $newval$$Register);
-    write_barrier_pre(masm, this,
-                      $mem$$Register /* obj */,
-                      $preval$$Register /* pre_val (as a temporary register) */,
-                      $tmp1$$Register /* tmp1 */,
-                      $tmp2$$Register /* tmp2 */,
-                      RegSet::of($mem$$Register, $preval$$Register, $newval$$Register) /* preserve */);
-    __ atomic_xchg($preval$$Register, $newval$$Register, $mem$$Register);
-    write_barrier_post(masm, this,
-                       $mem$$Register /* store_addr */,
-                       $newval$$Register /* new_val */,
-                       $tmp1$$Register /* tmp1 */,
-                       $tmp2$$Register /* tmp2 */);
-  %}
-  ins_pipe(pipe_serial);
-%}
-
 // This pattern is generated automatically from g1_aarch64.m4.
 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
 instruct g1GetAndSetPAcq(indirect mem, iRegP newval, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp preval, rFlagsReg cr)
@@ -687,34 +660,6 @@ instruct g1GetAndSetPAcq(indirect mem, iRegP newval, iRegPNoSp tmp1, iRegPNoSp t
   ins_pipe(pipe_serial);
 %}
 
-// This pattern is generated automatically from g1_aarch64.m4.
-// DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
-instruct g1GetAndSetN(indirect mem, iRegN newval, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegNNoSp preval, rFlagsReg cr)
-%{
-  predicate(UseG1GC && !needs_acquiring_load_exclusive(n) && n->as_LoadStore()->barrier_data() != 0);
-  match(Set preval (GetAndSetN mem newval));
-  effect(TEMP preval, TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
-  ins_cost(2 * VOLATILE_REF_COST);
-  format %{ "atomic_xchgw $preval, $newval, [$mem]" %}
-  ins_encode %{
-    assert_different_registers($mem$$Register, $newval$$Register);
-    write_barrier_pre(masm, this,
-                      $mem$$Register /* obj */,
-                      $tmp1$$Register /* pre_val */,
-                      $tmp2$$Register /* tmp1 */,
-                      $tmp3$$Register /* tmp2 */,
-                      RegSet::of($mem$$Register, $preval$$Register, $newval$$Register) /* preserve */);
-    __ atomic_xchgw($preval$$Register, $newval$$Register, $mem$$Register);
-    __ decode_heap_oop($tmp1$$Register, $newval$$Register);
-    write_barrier_post(masm, this,
-                       $mem$$Register /* store_addr */,
-                       $tmp1$$Register /* new_val */,
-                       $tmp2$$Register /* tmp1 */,
-                       $tmp3$$Register /* tmp2 */);
-  %}
-  ins_pipe(pipe_serial);
-%}
-
 // This pattern is generated automatically from g1_aarch64.m4.
 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
 instruct g1GetAndSetNAcq(indirect mem, iRegN newval, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegNNoSp preval, rFlagsReg cr)

src/hotspot/cpu/aarch64/gc/g1/g1_aarch64.m4

@@ -1,4 +1,4 @@
-dnl Copyright (c) 2024, Oracle and/or its affiliates. All rights reserved.
+dnl Copyright (c) 2024, 2026, Oracle and/or its affiliates. All rights reserved.
 dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 dnl
 dnl This code is free software; you can redistribute it and/or modify it
@@ -299,7 +299,6 @@ instruct g1GetAndSetP$1(indirect mem, iRegP newval, iRegPNoSp tmp1, iRegPNoSp tm
   %}
   ins_pipe(pipe_serial);
 %}')dnl
-XCHGP_INSN(,,atomic_xchg)
 XCHGP_INSN(Acq,_acq,atomic_xchgal)
 dnl
 define(`XCHGN_INSN',
@@ -331,7 +330,6 @@ instruct g1GetAndSetN$1(indirect mem, iRegN newval, iRegPNoSp tmp1, iRegPNoSp tm
   %}
   ins_pipe(pipe_serial);
 %}')dnl
-XCHGN_INSN(,atomic_xchgw,atomic_xchgw)
 XCHGN_INSN(Acq,atomic_xchgw_acq,atomic_xchgalw)
 
 // This pattern is generated automatically from g1_aarch64.m4.