All other than GPU

.gitignore

@@ -11,6 +11,10 @@
 # Normal rules (sorted alphabetically)
 #
 .*
+# The leading-dot rule above would otherwise hide the CI configuration,
+# which needs to be tracked for the workflow to run.
+!.github/
+!.github/workflows/
 *.a
 *.asn1.[ch]
 *.bc

Documentation/clk/mediatek-mt6589-unused-gates.rst

@@ -0,0 +1,140 @@
+=================================
+MediaTek MT6589 unreferenced clocks
+=================================
+
+The MT6589 clock drivers in ``drivers/clk/mediatek/clk-mt6589-*.c`` define
+188 clocks.  88 of them are referenced by a Device Tree node; the rest are
+either internal graph nodes (which correctly have no consumer) or leaf gates
+for blocks this board does not drive.
+
+This file records what the unreferenced leaf gates belong to, so that a later
+reader does not mistake them for an oversight and add a consumer for a block
+that has no driver.  A wrong clock consumer is worse than a missing one: it
+programs a gate register for a block that is not there.
+
+Internal graph nodes (not gates)
+================================
+
+Most of the unreferenced clocks are not gates at all but the mux and divider
+outputs that form the internal clock graph.  They must not be given DT
+consumers; they are reached through the gates below them.
+
+* ``CLK_TOP_MUX_*`` - ``axi_sel``, ``mem_sel``, ``smi_sel``, ``audintbus_sel``,
+  ``audio_sel``, ``cam_sel``, ``camtg_sel``, ``dpilvds_sel``, ``fd_sel``,
+  ``fix_sel``, ``hyd_sel``, ``irda_sel``, ``jpg_sel``, ``pmicspi_sel``,
+  ``uart_sel``, ``usb20_sel``.
+* PLL post-dividers - ``CLK_TOP_SYSPLL_D*``, ``CLK_TOP_UNIVPLL_D*``,
+  ``CLK_TOP_UNIVPLL1_D*``, ``CLK_TOP_UNIVPLL2_D*``, ``CLK_TOP_MMPLL_D4``,
+  ``CLK_TOP_MMPLL_D6``, ``CLK_TOP_LVDSPLL*``, ``CLK_TOP_MEMPLL_MCK_D4``.
+* Miscellaneous - ``CLK_TOP_CLK_NULL``, ``CLK_TOP_CLKPH_MCK``,
+  ``CLK_TOP_CPUM_TCK_IN``.
+
+Display
+=======
+
+The following gates are not referenced by any node.
+
+* ``CLK_DISP0_SCL`` (``disp0_scl``) - the display scaler.  MT6589 drives its
+  panel through the MIPI DSI path, and nothing in this tree uses a scaler
+  block.
+* ``CLK_DISP0_CMDQ_ENGINE`` / ``CLK_DISP0_CMDQ_SMI`` - the display command
+  queue.
+* ``CLK_DISP0_GAMMA_ENGINE`` / ``CLK_DISP0_GAMMA_PIXEL`` - the gamma
+  correction block.
+* ``CLK_DISP0_ROT_ENGINE`` / ``CLK_DISP0_ROT_SMI`` - the hardware rotator.
+  The MT6589 has no rotator in use here.
+* ``CLK_DISP1_LCD``, ``CLK_DISP1_SLCD``, ``CLK_DISP1_DPI0``, ``CLK_DISP1_DPI1``,
+  ``CLK_DISP1_DBI_ENGINE``, ``CLK_DISP1_DBI_OUTPUT``, ``CLK_DISP1_DBI_SMI`` -
+  the parallel LCD output paths (SLCD, DPI, DBI).  The Lenovo Blade drives
+  MIPI DSI and has no parallel LCD interface wired.
+
+Infrastructure
+==============
+
+Defined in ``clk-mt6589-infracfg.c``, unreferenced by any node.
+
+* ``CLK_INFRA_MD1MCUAXI``, ``CLK_INFRA_MD1HWMIXAXI``, ``CLK_INFRA_MD1AHB``,
+  ``CLK_INFRA_MD2MCUAXI``, ``CLK_INFRA_MD2HWMIXAXI``, ``CLK_INFRA_MD2AHB`` -
+  the two Cortex-M4 MCU subsystems (MD1, MD2).  There is no MCU driver in
+  this tree, so no consumer can exist.
+* ``CLK_INFRA_CPUM`` (``infra_cpum``) - the M4U-side CPU clock, same reason.
+* ``CLK_INFRA_AUDIO``, ``CLK_INFRA_SPI0``, ``CLK_INFRA_DBGCLK``,
+  ``CLK_INFRA_SMI``, ``CLK_INFRA_MFGAXI``, ``CLK_INFRA_CCIF0``,
+  ``CLK_INFRA_CCIF1``.
+
+.. note::
+
+   The gate array in ``clk-mt6589-infracfg.c`` does not line up with
+   ``include/dt-bindings/clock/mediatek,mt6589-clk.h``: ``CLK_INFRA_M4U`` is
+   ID 7 in the header but is shifted to 8 in the driver, and the gates run to
+   shift 23 while the header stops at 19 plus ``CLK_INFRA_ARMDIV1`` (20).
+   Several entries also still carry the original author's ``/* maybe */`` and
+   ``/* mt8135 */`` comments.  That misalignment is a separate bug and has
+   deliberately not been changed here, because correcting it would renumber
+   live gate registers.
+
+Peripheral
+==========
+
+Defined in ``clk-mt6589-pericfg.c``, unreferenced by any node.
+
+* ``CLK_PERI0_USB1`` (``peri_usb1``) - this board uses the internal HSIC PHY,
+  not the USB1 controller clock path.
+* ``CLK_PERI0_APHIF``, ``CLK_PERI0_MDHIF`` - the audio and multimedia PD/HIF
+  controllers.  No MT6589 driver in this tree claims them.
+* ``CLK_PERI0_IRDA``, ``CLK_PERI0_NLI`` - IrDA and the nativeland interface,
+  neither wired on this board.
+* ``CLK_PERI1_FHCTL`` (``peri_fhctl``) - the frequency-hopping controller.
+  ``clk-fhctl.c`` exists in this tree but no MT6589 node consumes the hop
+  clock.
+
+Image
+=====
+
+Defined in ``clk-mt6589-img.c``, unreferenced by any node.  The MT6589 camera
+capture path has no driver in this tree - the camera dtsi files are GPIO pin
+definitions only - so none of these can have a consumer yet.
+
+* ``CLK_IMAGE_CAM_CAM``, ``CLK_IMAGE_CAM_SMI``, ``CLK_IMAGE_COMMON_SMI``,
+  ``CLK_IMAGE_SEN_CAM``, ``CLK_IMAGE_SEN_TG``.
+
+GPU
+===
+
+* ``CLK_MFG_HYD`` (``mfg_hyd``) - defined in ``clk-mt6589-mfg.c``, unreferenced.
+  No GPU driver in this tree drives this clock.
+
+Top-level PMIC SPI
+==================
+
+* ``CLK_TOPCK_PMICSPI`` (``topck_pmicspi``) - a top-level PMIC SPI clock,
+  distinct from ``CLK_INFRA_PMICSPI``.  The ``pwrap`` node takes the
+  infracfg one (mt6589.dtsi).
+
+CPU intermediate clock
+======================
+
+``CLK_INFRA_ARMDIV1`` (``armdiv1``) is defined in
+``clk-mt6589-infracfg.c`` as a divider on the CPU mux, with
+``CLK_SET_RATE_PARENT`` set.  Until the Device Tree was corrected it had no
+consumer at all, because the CPU nodes named ``clk26m`` as their
+"intermediate" clock.
+
+That is not a cosmetic error.  ``mediatek-cpufreq.c`` reads the clock by that
+name and reparents the CPU onto it while ARMPLL is being reprogrammed, then
+looks up an OPP matching the intermediate rate to derive a safe intermediate
+voltage.  Pointing it at an unrelated always-on oscillator made both the
+reparent target and that voltage lookup meaningless.
+
+The CPU nodes now name ``CLK_INFRA_ARMDIV1``, which divides the mux output
+through ``TOP_CKDIV1.clkdiv1_sel`` (bits [4:0], datasheet pp. 435-437).
+
+.. warning::
+
+   ``mt6589_armdiv_determine_rate()`` selects the ratio *nearest* the request
+   rather than refusing a rate it cannot hit exactly
+   (``mt6589_armdiv_find_rate()``, ``clk-mt6589-infracfg.c``).  A mis-specified
+   target frequency therefore yields a silently wrong - but valid - rate
+   instead of an error.  This is left as-is deliberately: changing it alters
+   runtime clock semantics beyond the scope of this correction.  It is called
+   out here so the behaviour is not mistaken for exact division.

Documentation/devicetree/bindings/clock/mediatek,mt6589-mempll.yaml

@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6589-mempll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek MT6589 MEMPLL (DRAM PLL)
+
+maintainers:
+  - Akari Tsuyukusa <akkun11.open@gmail.com>
+
+description: |
+  The MT6589 MEMPLL is the PLL that clocks the DRAM controller.  Its
+  registers are not in the apmixedsys window: MEMPLL0..MEMPLL12 and
+  MEMPLL_DIVIDER live in the ddrphy_conf module at 0x1001_1600..0x1001_1640,
+  and the power-on debounce registers MPLLPON0..3 at 0x1001_15C0, per the
+  MT6589 datasheet section 13.4.3 ("DDRPHY Registers").  The node therefore
+  lives in the ddrphy_conf window rather than under apmixedsys.
+
+  The binding exposes the MEMPLL as a single read-only clock output.  The
+  rate is declared by the board with "clock-frequency" rather than decoded
+  from the registers, because the register set does not determine it
+  unambiguously: MEMPLL0's feedback divider field is not the divider for
+  PLL1, the reference can be either the crystal or the APLL plus a divider
+  (MEMPLL1[12:11]), and the downstream frequency tables map several
+  different DRAM rates onto the same DDS value.
+
+  The MEMPLL selection for the DRAM clock is still made in topckgen, not
+  here; the clock output of this node is what topckgen's "clkph_mck" is
+  parented to.
+
+properties:
+  compatible:
+    const: mediatek,mt6589-mempll
+
+  reg:
+    maxItems: 1
+    description: |
+      The ddrphy_conf window, at minimum covering the MEMPLL registers,
+      i.e. 0x600 through 0x640 of that block.
+
+  clock-frequency:
+    description: |
+      Frequency of the MEMPLL output in Hz, as configured by the bootloader
+      for the DRAM rate this board runs at.  Defaults to 266500000, the
+      figure the datasheet states for this clock ("MEMPLL_MCK 266.5MHz").
+    minimum: 1
+
+  "#clock-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+
+allOf:
+  - $ref: /schemas/clock/clock.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mediatek,mt6589-clk.h>
+
+    ddrphy: syscon@10011000 {
+        compatible = "mediatek,mt6589-mempll";
+        reg = <0x10011000 0x1000>;
+        #clock-cells = <0>;
+    };

Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml

@@ -17,6 +17,7 @@ description: |
 properties:
   compatible:
     enum:
+      - mediatek,mt6589-fhctl
       - mediatek,mt6795-fhctl
       - mediatek,mt8173-fhctl
       - mediatek,mt8186-fhctl
@@ -40,6 +41,20 @@ properties:
       minimum: 0
       maximum: 8
 
+  mediatek,fhctl-hopping-enabled:
+    description:
+      Whether a rate change on the corresponding PLL is driven through the
+      FHCTL hardware, one cell per entry in "clocks". This is separate from
+      mediatek,hopping-ssc-percent, which is the spread-spectrum modulation
+      depth and says nothing about whether the FHCTL path is used at all.
+      A PLL can hop without spreading, and conversely a spread-spectrum
+      percentage does not by itself make the hop work.
+    minItems: 0
+    maxItems: 30
+    items:
+      enum: [0, 1]
+      default: 0
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml

@@ -24,6 +24,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-color
+          - mediatek,mt6589-disp-color
           - mediatek,mt8167-disp-color
           - mediatek,mt8173-disp-color
           - mediatek,mt8195-mdp3-color

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml

@@ -18,12 +18,30 @@ description: |
 
 allOf:
   - $ref: /schemas/display/dsi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt6589-dsi
+    then:
+      properties:
+        clocks:
+          minItems: 4
+        clock-names:
+          minItems: 4
+    else:
+      properties:
+        clocks:
+          maxItems: 3
+        clock-names:
+          maxItems: 3
 
 properties:
   compatible:
     oneOf:
       - enum:
           - mediatek,mt2701-dsi
+          - mediatek,mt6589-dsi
           - mediatek,mt7623-dsi
           - mediatek,mt8167-dsi
           - mediatek,mt8173-dsi
@@ -50,16 +68,22 @@ properties:
     maxItems: 1
 
   clocks:
+    minItems: 3
+    maxItems: 4
     items:
       - description: Engine Clock
       - description: Digital Clock
       - description: HS Clock
+      - description: Digital Lane Clock (MT6589 only)
 
   clock-names:
+    minItems: 3
+    maxItems: 4
     items:
       - const: engine
       - const: digital
       - const: hs
+      - const: lane
 
   resets:
     maxItems: 1

Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml

@@ -23,6 +23,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-ovl
+          - mediatek,mt6589-disp-ovl
           - mediatek,mt8167-disp-ovl
           - mediatek,mt8173-disp-ovl
           - mediatek,mt8183-disp-ovl

Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml

@@ -25,6 +25,7 @@ properties:
     oneOf:
       - enum:
           - mediatek,mt2701-disp-rdma
+          - mediatek,mt6589-disp-rdma
           - mediatek,mt8173-disp-rdma
           - mediatek,mt8183-disp-rdma
           - mediatek,mt8195-disp-rdma

Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml

@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Two-Dimension Sharpness Processor (TDSHP)
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  The MediaTek TDSHP is a two-dimension sharpness processor found in
+  various MediaTek SoCs. On MT6589 the block sits between the COLOR
+  processor and BLS in the display pipeline and is used in relay mode.
+
+properties:
+  compatible:
+    const: mediatek,mt6589-disp-tdshp
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mediatek,mt6589-clk.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        tdshp@1400b000 {
+            compatible = "mediatek,mt6589-disp-tdshp";
+            reg = <0x1400b000 0x1000>;
+            interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
+            clocks = <&dispsys CLK_DISP0_2DSHP>;
+        };
+    };