Pipeline V1 by TheDeepestSpace · Pull Request #159 · UTOSS/risc-v

TheDeepestSpace · 2026-01-24T18:23:59Z

PR for tracking pipeline-related changes

Todos

…ames

This reverts commit e0b4bc5.

Decode Pipeline Stage Implementation

i think we incorrectly named the signals at the start of the pipeline; need to revisit the naming

TheDeepestSpace · 2026-04-07T17:40:29Z

+  assign imem__address = pc_cur;
+  assign IF_to_ID.instruction = imem__data;
+  assign IF_to_ID.pc_cur = pc_prev;
+  assign IF_to_ID.pc_plus_4 = pc_prev + 32'h4; // TODO: revisit


Would be interesting to see the trade off between two +4 circuits and a single +4 and a 32-bit reg.

github-actions · 2026-04-10T05:55:32Z

🔧 DE1-SoC Synthesis Report Summary Diff

📊 Fitter Summary (.fit.summary)

@@ -1,16 +1,16 @@
-Fitter Status : Successful - Fri Apr 10 06:00:53 2026
+Fitter Status : Successful - Fri Apr 10 05:54:55 2026
 Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
 Revision Name : utoss-risc-v
 Top-level Entity Name : top
 Family : Cyclone V
 Device : 5CSEMA5F31C6
 Timing Models : Final
-Logic utilization (in ALMs) : 1,427 / 32,070 ( 4 % )
-Total registers : 1262
+Logic utilization (in ALMs) : 1,513 / 32,070 ( 5 % )
+Total registers : 1535
 Total pins : 15 / 457 ( 3 % )
 Total virtual pins : 0
-Total block memory bits : 16,384 / 4,065,280 ( < 1 % )
-Total RAM Blocks : 4 / 397 ( 1 % )
+Total block memory bits : 32,768 / 4,065,280 ( < 1 % )
+Total RAM Blocks : 8 / 397 ( 2 % )
 Total DSP Blocks : 0 / 87 ( 0 % )
 Total HSSI RX PCSs : 0
 Total HSSI PMA RX Deserializers : 0

🔢 Fitter Resource Utilization by Entity

@@ -1,19 +1,33 @@
-Compilation Hierarchy Node                     ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                    Entity Name         Library Name
-|top                                           1427.0 (0.5)          1586.5 (0.5)                      177.0 (0.0)                                        17.5 (0.0)                        0.0 (0.0)             1747 (1)             1262 (0)                   0 (0)          16384              4      0           15    0             |top                                                                                   top                 work
-   |memory_map:memory_map|                     37.8 (37.8)           41.8 (41.8)                       4.3 (4.3)                                          0.3 (0.3)                         0.0 (0.0)             67 (67)              12 (12)                    0 (0)          16384              4      0           0     0             |top|memory_map:memory_map                                                             memory_map          work
-      |altsyncram:M0_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                         altsyncram          work
-         |altsyncram_9hp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated          altsyncram_9hp1     work
-      |altsyncram:M1_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                         altsyncram          work
-         |altsyncram_ahp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated          altsyncram_ahp1     work
-      |altsyncram:M2_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                         altsyncram          work
-         |altsyncram_bhp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated          altsyncram_bhp1     work
-      |altsyncram:M3_rtl_0|                    0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                         altsyncram          work
-         |altsyncram_chp1:auto_generated|      0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated          altsyncram_chp1     work
-   |utoss_riscv:core|                          1388.6 (131.9)        1544.2 (143.3)                    172.7 (15.3)                                       17.2 (4.0)                        0.0 (0.0)             1679 (163)           1250 (177)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                  utoss_riscv         work
-      |ALU:alu|                                372.3 (372.3)         386.2 (386.2)                     19.8 (19.8)                                        5.9 (5.9)                         0.0 (0.0)             521 (521)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ALU:alu                                                          ALU                 work
-      |ControlFSM:control_fsm|                 31.8 (31.8)           32.2 (32.2)                       0.5 (0.5)                                          0.1 (0.1)                         0.0 (0.0)             49 (49)              17 (17)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|ControlFSM:control_fsm                                           ControlFSM          work
-      |Instruction_Decode:instruction_decode|  57.0 (48.8)           57.0 (48.7)                       0.2 (0.0)                                          0.1 (0.1)                         0.0 (0.0)             108 (96)             0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode                            Instruction_Decode  work
-         |ALUdecoder:instanceALUDec|           7.2 (7.2)             8.3 (8.3)                         1.2 (1.2)                                          0.0 (0.0)                         0.0 (0.0)             12 (12)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
-      |MemoryLoader:MemLoad|                   30.1 (30.1)           28.3 (28.3)                       0.1 (0.1)                                          2.0 (2.0)                         0.0 (0.0)             64 (64)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|MemoryLoader:MemLoad                                             MemoryLoader        work
-      |fetch:fetch|                            72.8 (72.8)           72.8 (72.8)                       0.5 (0.5)                                          0.5 (0.5)                         0.0 (0.0)             95 (95)              64 (64)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch:fetch                                                      fetch               work
-      |registerFile:RegFile|                   692.7 (692.7)         824.5 (824.5)                     136.3 (136.3)                                      4.6 (4.6)                         0.0 (0.0)             679 (679)            992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|registerFile:RegFile                                             registerFile        work
+Compilation Hierarchy Node                        ALMs needed [=A-B+C]  [A] ALMs used in final placement  [B] Estimate of ALMs recoverable by dense packing  [C] Estimate of ALMs unavailable  ALMs used for memory  Combinational ALUTs  Dedicated Logic Registers  I/O Registers  Block Memory Bits  M10Ks  DSP Blocks  Pins  Virtual Pins  Full Hierarchy Name                                                                                  Entity Name         Library Name
+|top                                              1513.0 (0.5)          1645.5 (0.5)                      167.0 (0.0)                                        34.5 (0.0)                        0.0 (0.0)             1796 (1)             1535 (0)                   0 (0)          32768              8      0           15    0             |top                                                                                                 top                 work
+   |memory_map:memory_map|                        13.6 (13.6)           13.7 (13.7)                       0.3 (0.3)                                          0.1 (0.1)                         0.0 (0.0)             13 (13)              11 (11)                    0 (0)          32768              8      0           0     0             |top|memory_map:memory_map                                                                           memory_map          work
+      |altsyncram:M0_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0                                                       altsyncram          work
+         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_0|altsyncram_9hp1:auto_generated                        altsyncram_9hp1     work
+      |altsyncram:M0_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1                                                       altsyncram          work
+         |altsyncram_9hp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M0_rtl_1|altsyncram_9hp1:auto_generated                        altsyncram_9hp1     work
+      |altsyncram:M1_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0                                                       altsyncram          work
+         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_0|altsyncram_ahp1:auto_generated                        altsyncram_ahp1     work
+      |altsyncram:M1_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1                                                       altsyncram          work
+         |altsyncram_ahp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M1_rtl_1|altsyncram_ahp1:auto_generated                        altsyncram_ahp1     work
+      |altsyncram:M2_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0                                                       altsyncram          work
+         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_0|altsyncram_bhp1:auto_generated                        altsyncram_bhp1     work
+      |altsyncram:M2_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1                                                       altsyncram          work
+         |altsyncram_bhp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M2_rtl_1|altsyncram_bhp1:auto_generated                        altsyncram_bhp1     work
+      |altsyncram:M3_rtl_0|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0                                                       altsyncram          work
+         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_0|altsyncram_chp1:auto_generated                        altsyncram_chp1     work
+      |altsyncram:M3_rtl_1|                       0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1                                                       altsyncram          work
+         |altsyncram_chp1:auto_generated|         0.0 (0.0)             0.0 (0.0)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             0 (0)                0 (0)                      0 (0)          4096               1      0           0     0             |top|memory_map:memory_map|altsyncram:M3_rtl_1|altsyncram_chp1:auto_generated                        altsyncram_chp1     work
+   |utoss_riscv:core|                             1499.0 (605.2)        1631.3 (634.2)                    166.7 (40.9)                                       34.4 (11.8)                       0.0 (0.0)             1782 (737)           1524 (468)                 0 (0)          0                  0      0           0     0             |top|utoss_riscv:core                                                                                utoss_riscv         work
+      |Decode:decode|                             302.9 (3.0)           377.6 (3.0)                       77.5 (0.0)                                         2.8 (0.0)                         0.0 (0.0)             90 (8)               992 (0)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Decode:decode                                                                  Decode              work
+         |Instruction_Decode:instruction_decode|  9.5 (6.7)             10.3 (7.3)                        0.8 (0.6)                                          0.0 (0.0)                         0.0 (0.0)             32 (23)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Decode:decode|Instruction_Decode:instruction_decode                            Instruction_Decode  work
+            |ALUdecoder:instanceALUDec|           2.8 (2.8)             3.1 (3.1)                         0.2 (0.2)                                          0.0 (0.0)                         0.0 (0.0)             9 (9)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Decode:decode|Instruction_Decode:instruction_decode|ALUdecoder:instanceALUDec  ALUdecoder          work
+         |control_fsm:u_ctrl|                     3.8 (3.8)             3.8 (3.8)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             10 (10)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Decode:decode|control_fsm:u_ctrl                                               control_fsm         work
+         |registerFile:RegFile|                   286.4 (286.4)         360.4 (360.4)                     76.8 (76.8)                                        2.8 (2.8)                         0.0 (0.0)             40 (40)              992 (992)                  0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Decode:decode|registerFile:RegFile                                             registerFile        work
+      |Execute:execute|                           441.5 (90.6)          462.4 (99.2)                      37.5 (9.3)                                         16.6 (0.7)                        0.0 (0.0)             657 (167)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Execute:execute                                                                Execute             work
+         |ALU:alu|                                351.0 (351.0)         363.3 (363.3)                     28.3 (28.3)                                        16.0 (16.0)                       0.0 (0.0)             490 (490)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|Execute:execute|ALU:alu                                                        ALU                 work
+      |fetch_stage:u_fetch_stage|                 70.9 (70.9)           76.0 (76.0)                       7.5 (7.5)                                          2.4 (2.4)                         0.0 (0.0)             123 (123)            64 (64)                    0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|fetch_stage:u_fetch_stage                                                      fetch_stage         work
+      |hazard_unit:u_hazard_unit|                 9.4 (9.4)             10.6 (10.6)                       1.3 (1.3)                                          0.1 (0.1)                         0.0 (0.0)             18 (18)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|hazard_unit:u_hazard_unit                                                      hazard_unit         work
+      |mem_stage:memory_stage|                    9.3 (0.0)             9.0 (0.0)                         0.0 (0.0)                                          0.3 (0.0)                         0.0 (0.0)             24 (0)               0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|mem_stage:memory_stage                                                         mem_stage           work
+         |MemoryLoader:memory_loader|             9.3 (9.3)             9.0 (9.0)                         0.0 (0.0)                                          0.3 (0.3)                         0.0 (0.0)             24 (24)              0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|mem_stage:memory_stage|MemoryLoader:memory_loader                              MemoryLoader        work
+      |write_back:wb|                             59.5 (58.1)           61.5 (60.3)                       2.4 (2.6)                                          0.4 (0.4)                         0.0 (0.0)             133 (130)            0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back:wb                                                                  write_back          work
+         |MemoryLoader:memory_loader|             1.2 (1.2)             1.2 (1.2)                         0.0 (0.0)                                          0.0 (0.0)                         0.0 (0.0)             3 (3)                0 (0)                      0 (0)          0                  0      0           0     0             |top|utoss_riscv:core|write_back:wb|MemoryLoader:memory_loader                                       MemoryLoader        work

⏱️ Timing Analysis Summary (.sta.summary)

@@ -3,51 +3,51 @@
 ------------------------------------------------------------
 
 Type  : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 4.839
+Slack : 2.984
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.375
+Slack : 0.310
 TNS   : 0.000
 
 Type  : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.876
+Slack : 8.868
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 5.002
+Slack : 3.242
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.388
+Slack : 0.263
 TNS   : 0.000
 
 Type  : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.830
+Slack : 8.822
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : 10.876
+Slack : 9.647
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.181
+Slack : 0.191
 TNS   : 0.000
 
 Type  : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.786
+Slack : 8.787
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : 11.803
+Slack : 10.704
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.171
+Slack : 0.149
 TNS   : 0.000
 
 Type  : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : 8.778
+Slack : 8.780
 TNS   : 0.000
 
 ------------------------------------------------------------

Comparing synthesis results from main branch vs. this PR

marwannismail and others added 30 commits November 30, 2025 12:55

Organized directory structure for pipelined implementation

9013538

Modified testbench files to include new header directory

12980be

Progress on Decode.sv implementation and IF creation

3f12c15

IF to ID interface and IF register in Decode.sv

b0875eb

Added newlines at the end of modules

21138a0

Verilator set up for Makefile and changes to the jal_tb and jalr_tb n…

cdd5a66

…ames

Merge remote-tracking branch 'origin/main' into mi_pipeline_decode_impl

22361dd

Params file name change

7caa25b

Fixed inclusion of params header and new top module

308f29a

Renamed uut from top to utoss_riscv

e0b4bc5

Revert "Renamed uut from top to utoss_riscv"

b147150

This reverts commit e0b4bc5.

Adjusted Makefile to include envs directory

af2b713

Removed duplicate params.svh file

a6c4221

Added Verilator installation process to CI

f1056eb

Fixed fetch_tb.sv and Verilator CI tool installation

761adb9

SVLint fixes

4ad4c4b

SVLint fixes

c48702f

Removing duplicate .v files

610ac51

Modified De1-SoC Makefile to use Verilator

20b2466

Merge remote-tracking branch 'origin/main' into mi_pipeline_decode_impl

ef9db3f

Merge pull request #133 from UTOSS/mi_pipeline_decode_impl

c74d82e

Decode Pipeline Stage Implementation

Merge branch 'main' into pipeline-v1

e23e501

set up write back stage

870d281

start adding mem stage

b79877e

create mem_stage module

b534e97

Fix linting and move mem_stage to stages

d1eb2a5

Move mem_stage to stages

5829d4a

Change include path

4ddb376

Fix lint again

773cad1

Fix lint again

1cf4cf5

TheDeepestSpace added 5 commits April 3, 2026 15:29

dut debugging

50b2264

add pc_target_kind selector

e9fef3c

fix cfsm jal bug

f8b2326

use pc_cur instead of pc_plus_4 in wb

11765e1

i think we incorrectly named the signals at the start of the pipeline; need to revisit the naming

run riscof, but let fail

9041011

TheDeepestSpace force-pushed the pipeline-v1 branch from d743b8f to 9041011 Compare April 3, 2026 15:39

Invisipac and others added 8 commits April 3, 2026 16:56

merge fix-loads

eb5b4b6

get rid of some warnings

c261be3

fix svlint infraction

4c51a3e

require riscof to pass

86b3938

remove ex pkg

e8e0d1d

move forwarding hazard enums outside pkg

7e33500

fix and document pc_cur/prev/next arrangement

8aef48b

use always_ff

7f5c24e

TheDeepestSpace commented Apr 7, 2026

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TheDeepestSpace added 14 commits April 10, 2026 04:12

remove old tops

538698d

migrate new tops

e064eb1

remove build_pipelined

d494b00

reinstate build_and_test and skip test part for now

e14f9a4

get de1-soc's top to be verilatable

8aaef6c

remove multi-cycle cfsm

98a271d

migrate cfsm

d8b12eb

arrange pipelined impl files for quartus

3675819

make alu control type safe

4209aba

fix syntax

b1627c4

deal with quartus not supporting inside keyword

2eeea9b

re-enable de1-soc ci job

dc81229

fix riscof dut

7786900

add timescale import to sv files directly

719e333

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Pipeline V1#159

Pipeline V1#159
TheDeepestSpace wants to merge 191 commits intomainfrom
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TheDeepestSpace commented Jan 24, 2026 •

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TheDeepestSpace commented Jan 24, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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github-actions bot commented Apr 10, 2026 • edited Loading Uh oh! There was an error while loading. Please reload this page.

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🔧 DE1-SoC Synthesis Report Summary Diff

📊 Fitter Summary (.fit.summary)

🔢 Fitter Resource Utilization by Entity

⏱️ Timing Analysis Summary (.sta.summary)

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TheDeepestSpace commented Jan 24, 2026 •

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github-actions bot commented Apr 10, 2026 •

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