[ashhart]

What this changes

Corrects the four CUDA documentation entry points against the native registry, loader gates and recorded receipts. Native GLM TP=2/TP=3, Gemma 4 CUDA and family-specific precision are described without promoting an A100 kernel receipt to whole-model qualification. Historical Python tables keep their scope.

• Refs CUDA: Ampere sm_80 in the release fatbins, with the ModelOpt floor named at its refusal #846, nemotron cuda: ModelOpt checkpoints below sm_90, the lane matmul's slices reduced through a per-stream buffer #901, qwen3_5: a modelopt checkpoint refuses below sm_90 in words, not missinglanepart #1470 and GLM-5.3-Flash and full GLM-5.3 on the native CUDA engine (tracker) #593. Documentation audit; no new family or arithmetic change.

Claim changes and evidence

Each item names the changed documentation and the exact source or recorded receipt it rests on. Absence of an sm_80 served-checkpoint receipt follows the qualification record; no new hardware run is claimed.

1. Native CUDA registers more than Nemotron and Flash Next; registration is separate from device and checkpoint qualification.
   Changed text: docs/recipes/cuda.md:11.
   Evidence: zig/src/native/cuda.zig:33, zig/src/native/cuda.zig:199, zig/src/native/cuda.zig:202.

2. Qwen4 is preparation with synthetic device gates and no real-checkpoint qualification; DeepSeek is refused pending gate DeepSeek V4.1: the lane backend — one stream per slot on the lane core #827.
   Changed text: docs/recipes/cuda.md:13, RUNBOOK.md:201.
   Evidence: zig/src/native/cuda.zig:43, CHANGELOG.md:773, zig/src/native/cuda_refusal.zig:5.

3. Native GLM has recorded TP=2 and TP=3 serving, including FP4-Local and XSFP4; the CUDA setup is not limited to two ranks.
   Changed text: docs/recipes/cuda.md:17, RUNBOOK.md:193, README.md:207.
   Evidence: zig/src/native/cuda.zig:33, zig/src/families/glm/cuda_native.zig:128, docs/receipts/glm-fp4local-80517fc3/README.md:27, CHANGELOG.md:517.

4. GLM uses TF_GLM_RANK, TF_GLM_WORLD and NCCL_COMM_ID; other families accept --tp only when their options consume ranks. Super VL has one- and two-GB10 receipts.
   Changed text: docs/recipes/cuda.md:162, RUNBOOK.md:194.
   Evidence: zig/src/families/glm/cuda_native.zig:118, zig/src/families/glm/cuda_native.zig:180, zig/src/native/cuda_options.zig:12, zig/src/native/cuda_refusal.zig:55, docs/recipes/nemotron-3.5-super-vl.md:4.

5. EXL3 loading and DFlash2 drafting are native capabilities for particular families and formats, not Python-only features.
   Changed text: docs/recipes/cuda.md:18.
   Evidence: zig/src/families/glm/cuda_exl3.zig:27, zig/src/families/glm/cuda_native.zig:291, zig/src/families/qwen3_5/cuda_native.zig:34, CHANGELOG.md:553.

6. The Nemotron MLX 4-bit serving record names GB10, RTX 3090 and RTX PRO 6000; an RTX 3090 receipt does not measure every sm_86 card.
   Changed text: docs/recipes/cuda.md:20, docs/recipes/README.md:34, RUNBOOK.md:190.
   Evidence: zig/src/native/cuda.zig:33, zig/src/families/nemotron/cuda_native.zig:31, CHANGELOG.md:1662, CHANGELOG.md:1623, CHANGELOG.md:1538.

7. Release targets are sm_80, sm_86, sm_120 and sm_121. The A100 has recorded kernel checks but no served checkpoint on record, so it is not model-qualified.
   Changed text: docs/recipes/cuda.md:22, docs/recipes/README.md:35, RUNBOOK.md:197, README.md:164.
   Evidence: zig/build/cuda.zig:542, CHANGELOG.md:1322.

8. Nemotron and dense Qwen have NVFP4/FP8 non-cluster fallback implementations for sm_80 to sm_89; no such model run on sm_80 is recorded.
   Changed text: docs/recipes/cuda.md:24, docs/recipes/README.md:41, RUNBOOK.md:199, README.md:166, README.md:179.
   Evidence: zig/src/families/nemotron/cuda_kernels.zig:193, zig/src/families/qwen3_5/cuda_modelopt.zig:216, zig/src/cuda/qmmf.zig:153, CHANGELOG.md:1237, CHANGELOG.md:577.

9. Flash Next MLX 4-bit has a GB10 serving receipt; the ModelOpt/two-local-rank path is experimental, with tensor-rank drafting requiring the prompt cache off. There is no blanket all-SM qualification.
   Changed text: docs/recipes/README.md:42.
   Evidence: zig/src/native/cuda.zig:33, zig/src/families/flashnext/cuda_lanes.zig:29, zig/src/native/cuda_refusal.zig:57, CHANGELOG.md:1221.

10. Gemma 4 12B and 31B MLX checkpoints, including assistant/DFlash drafting, have native CUDA GB10 receipts; pre-M5 Metal has a row path, while its assistant and DFlash drafters require tensor units.
    Changed text: RUNBOOK.md:195, README.md:194, README.md:195.
    Evidence: zig/src/native/cuda.zig:33, zig/src/families/gemma4/cuda_native.zig:21, CHANGELOG.md:881, zig/src/families/gemma4/model.zig:93, zig/src/families/gemma4/weights.zig:234, zig/src/families/gemma4/assistant.zig:95, zig/src/families/gemma4/dflash.zig:89, CHANGELOG.md:849.

11. Native --precision is family-specific: Super VL checkpoint math requires Blackwell and dense Qwen accepts full only. The two --prefill-fp8 flags remain Python-only.
    Changed text: docs/recipes/cuda.md:8, docs/recipes/cuda.md:209.
    Evidence: zig/src/server/cli.zig:137, zig/src/server/cli.zig:138, zig/src/server/cli.zig:139, zig/src/server/cli.zig:303, zig/src/families/nemotron/cuda_latent_ck.zig:13, zig/src/families/nemotron/cuda_kernels.zig:190, zig/src/families/qwen3_5/cuda_native.zig:55.

12. The legacy checkpoint/precision/transport/serialization tables and Apple memory scopes are explicitly Python 0.6.6 history, not current native limits.
    Changed text: docs/recipes/cuda.md:70, docs/recipes/cuda.md:167, docs/recipes/cuda.md:222, docs/recipes/cuda.md:329, docs/recipes/README.md:44.
    Evidence: CONTRIBUTING.md:4, zig/src/native/cuda.zig:131, CHANGELOG.md:795.

13. The segmented tensorfold run description applies to Nemotron; it is not a promise that every registered family takes four segments.
    Changed text: docs/recipes/cuda.md:106.
    Evidence: zig/src/cli/cuda_main.zig:228, zig/src/families/qwen3_5/cuda_native.zig:31.

14. The P2P report describes native ranked implementation; its DeepSeek references do not imply the release serves that family.
    Changed text: docs/recipes/cuda.md:356.
    Evidence: zig/src/native/cuda.zig:53, zig/src/families/glm/cuda_native.zig:230, zig/src/native/cuda_refusal.zig:5.

15. The Qwen3.6 MLX row records a CUDA run without describing native Metal as absent: Metal also registers qwen3_5_moe, while the linked recipe retains Python Metal commands.
    Changed text: README.md:192.
    Evidence: zig/src/native/metal.zig:48, zig/src/native/metal.zig:179, CHANGELOG.md:1228, docs/recipes/qwen3.6-moe.md:3.

Checks on this head

• Lean checker: not run; all source, tests, build files and the pinned baseline are byte-identical to main.
• Checks run: all 143 local links and their local Markdown anchors pass; the 15 claim groups map to the cited lines; section headings are unchanged; prose spacing and git diff --check pass. Exactly four Markdown files change, with the other 9,855 tracked files unchanged.
• Not run: builds, unit tests, lean, GPU kernels, models and servers. Documentation only. External URL availability is unchecked.

Receipt

n/a: this changes documentation only. No timing, throughput, fidelity or hardware qualification measurement was added. Existing historical measurements keep their historical scope.

Checklist

• Title, description and claim list match the one documentation commit.
• No code, tests, lean baseline or new sections.
• Changed claims cite source or recorded receipts; unmeasured hardware is labelled.
• Local links, whitespace and prose spacing checked.
• Outgoing tree and metadata inspected.

[ashhart]

Updated after a read against the code. The docs now name the startup refusals someone buying hardware needs: MiniMax-M3.1-Flash on CUDA is sm_121 only, DeepSeek needs sm_90 and stays refused by the release, Nemotron's checkpoint math needs Blackwell, GLM refuses some projection shapes without split-K partial storage on cards before sm_90, and the CUDA learner is sm_121 only. "No NVFP4/FP8 model run" now covers sm_80 to sm_89. The RUNBOOK gives the rank limits: GLM refuses above 16, --tp offers 1, 2, 4 or 8, and the largest recorded run is three GB10s. Nemotron on the RTX PRO 6000 stays "checked", as there's no serving receipt to link.