[ashhart]

Spark 2.5 on CUDA loaded gate and up as two weights and decoded them with two launches. They now load as one stacked weight and every CUDA chip decodes both in one launch. The bits stay the same: both members keep n=10240, so split-K stays 2; codes are addressed independently of npad, and scales and biases use npad as their stride; the seam is 128-aligned, so no tile crosses into the other member. On GB10 the same grouped kernels run. On other chips the segmented kernel replaces the split kernel at 16 rows or fewer, with the same gemv_split<64,64,4> body (split-K 2) and its own work and ticket areas; at 17-32 rows each member keeps its own launch. Only 4-bit checkpoints take this path.

Tests: test-spark25-host 13, test-cuda-family-groups-host 5 and test-qwen35-verify-host 8 pass; the new test records main's per-member launches and fails on main ("expected 1, found 0"). compile-cuda-tests passes for aarch64 and x86_64 Linux.

Device check pending (needs a Spark 2.5 MLX 4-bit checkpoint): on a GB10 and a non-GB10 sm_120 card, a served A/B against main with token hashes equal at T=0 and sampled with the same seed, over 1, 2, 8 and 16-row decode, 17-32-row verify windows on sm_120, the prompt, and solo versus concurrent streams; decode tok/s reported.