Add risc-v test configuration

[keiravillekode]

Context:

• forum thread

• hello-world prototype

The aspiration is for the risc-v track to be 32 bit. I don't have the 32 bit tooling working yet, but "How hard can it be?"

cc @ErikSchierboom

[ErikSchierboom]

@keiravillekode am I correct ik seeing that the risc track hasn't been launched yet (of is nearing completion)?

[keiravillekode]

http://github.com/exercism/risc-v has not been created yet. But it and http://github.com/exercism/risc-v-test-runner would be very similar to the arm64 track, it is mostly just the example solutions that need to be reimplemented. And often the example solutions can be easily ported from mips, as the instruction sets are similar.

I also need to request a logo.

Assuming I get the 32 bit tooling working (or give up and go with the 64 bit tooling currently used in https://github.com/keiravillekode/prototype-risc-v/) then the track could be created and launched with 20 exercises exceedingly quickly.

(Or we could take a slower approach and aim for 60+ exercises before launch, to reduce cross-track-reviewer workload after launch.)

[ErikSchierboom]

I'd still like to only merge this once the track is nearly completed.

[IsaacG]

Closing this out as there's no imminent Risc V launch.

[keiravillekode]

The test runner has been implemented, the track has 77 exercises, and a logo has been requested.

[IsaacG]

@keiravillekode Please rebase