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[pwrmgr, dv] Power manager vendoring#553

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csabakiss-semify wants to merge 2 commits into
lowRISC:mainfrom
csabakiss-semify:csk_pwrmgr_dv_port
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[pwrmgr, dv] Power manager vendoring#553
csabakiss-semify wants to merge 2 commits into
lowRISC:mainfrom
csabakiss-semify:csk_pwrmgr_dv_port

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@csabakiss-semify csabakiss-semify commented May 14, 2026

This is a PR about the power manager block level DV vendoring.

Linked to issue #431

@martin-velay martin-velay changed the title Power manager vendoring [pwrmgr, dv] Power manager vendoring May 19, 2026
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I have few comments so far but I'd prefer to not have that much commit to review as most of these changes I think are because of the OpenTitan hash update. Would it be possible to squash commits which come from the OT hash update? And if you have other automated code generated, it's best to have them in one commit, then I know I can just skip them from my review and focus only on your edits.

Comment thread hw/vendor/lowrisc_ip/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl Outdated
Comment thread hw/vendor/lowrisc_ip/ip_templates/pwrmgr/dv/pwrmgr_sim_cfg.hjson.tpl Outdated
@csabakiss-semify csabakiss-semify force-pushed the csk_pwrmgr_dv_port branch 2 times, most recently from bc35e3d to 1ed4c06 Compare May 22, 2026 11:59
@martin-velay
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@csabakiss-semify could you pull the latest main and rebase please?

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I just checked against OT results when we run with Xcelium and we are getting similar results.

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 3.000s 22.671us 50 50 100.00 %
V1 csr_hw_reset pwrmgr_csr_hw_reset 2.000s 24.097us 5 5 100.00 %
V1 csr_rw pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V1 csr_bit_bash pwrmgr_csr_bit_bash 5.000s 1222.642us 5 5 100.00 %
V1 csr_aliasing pwrmgr_csr_aliasing 3.000s 74.892us 5 5 100.00 %
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 3.000s 52.385us 20 20 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_aliasing 3.000s 74.892us 5 5 100.00 %
V1 TOTAL 105 105 100.00 %
V2 wakeup pwrmgr_wakeup 3.000s 156.159us 49 50 98.00 %
V2 control_clks pwrmgr_wakeup 3.000s 156.159us 49 50 98.00 %
V2 aborted_low_power pwrmgr_aborted_low_power 3.000s 86.369us 50 50 100.00 %
V2 aborted_low_power pwrmgr_lowpower_invalid 2.000s 44.751us 49 50 98.00 %
V2 reset pwrmgr_reset 3.000s 41.477us 33 50 66.00 %
V2 reset pwrmgr_reset_invalid 3.000s 126.320us 50 50 100.00 %
V2 main_power_glitch_reset pwrmgr_reset 3.000s 41.477us 33 50 66.00 %
V2 reset_wakeup_race pwrmgr_wakeup_reset 3.000s 174.732us 8 50 16.00 %
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 4.000s 297.502us 50 50 100.00 %
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 3.000s 155.929us 50 50 100.00 %
V2 stress_all pwrmgr_stress_all 16.000s 2471.006us 14 50 28.00 %
V2 intr_test pwrmgr_intr_test 2.000s 21.240us 50 50 100.00 %
V2 tl_d_oob_addr_access pwrmgr_tl_errors 5.000s 427.516us 20 20 100.00 %
V2 tl_d_illegal_access pwrmgr_tl_errors 5.000s 427.516us 20 20 100.00 %
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 2.000s 24.097us 5 5 100.00 %
V2 tl_d_outstanding_access pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V2 tl_d_outstanding_access pwrmgr_csr_aliasing 3.000s 74.892us 5 5 100.00 %
V2 tl_d_outstanding_access pwrmgr_same_csr_outstanding 3.000s 28.634us 20 20 100.00 %
V2 tl_d_partial_access pwrmgr_csr_hw_reset 2.000s 24.097us 5 5 100.00 %
V2 tl_d_partial_access pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V2 tl_d_partial_access pwrmgr_csr_aliasing 3.000s 74.892us 5 5 100.00 %
V2 tl_d_partial_access pwrmgr_same_csr_outstanding 3.000s 28.634us 20 20 100.00 %
V2 TOTAL 473 570 82.98 %
V2S tl_intg_err pwrmgr_tl_intg_err 3.000s 519.054us 20 20 100.00 %
V2S tl_intg_err pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S prim_count_check pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S prim_fsm_check pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 3.000s 519.054us 20 20 100.00 %
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.000s 255.075us 0 50 0.00 %
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_wakeup_reset 3.000s 174.732us 8 50 16.00 %
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 3.000s 47.729us 50 50 100.00 %
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 3.000s 32.895us 50 50 100.00 %
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 3.000s 968.786us 5 5 100.00 %
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 2.000s 48.399us 50 50 100.00 %
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 2.000s 35.252us 50 50 100.00 %
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 4.000s 266.673us 50 50 100.00 %
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 3.000s 21.037us 20 20 100.00 %
V2S TOTAL 303 395 76.71 %
V3 escalation_timeout pwrmgr_escalation_timeout 3.000s 107.314us 48 50 96.00 %
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 17.000s 1606.330us 2 50 4.00 %
V3 TOTAL 50 100 50.00 %
TOTAL 873 1070 81.59 %

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A few initial comments from my end.

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Did you skip number 3?

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Yes, good catch. I had that during the development but then became useless so I removed and forgot to renumber. I’ll renumber the patches to make them cleaner.

'''
stage: V2S
- tests: ["pwrmgr_wakeup_reset", "pwrmgr_repeat_wakeup_reset"]
+ tests: ["pwrmgr_wakeup_reset"]
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What is wrong with the repeat wakeup reset test?

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Nothing. The pwrmgr_repeat_wakeup_reset_vseq still exists, and it is used by the pwrmgr_sec_cm_lc_ctrl_intersig_mubi test. It was only that the testplan which listed pwrmgr_repeat_wakeup_reset as a test, but there is no test with that name. This patch is only to remove the stale testplan entry, not the sequence.

Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
Signed-off-by: Csaba Kiss <csaba.kiss@semify-eda.com>
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3 participants