Rebase/cache refactoring onto main

Bender.lock

@@ -71,7 +71,7 @@ packages:
     - common_verification
     - register_interface
   insitu-cache:
-    revision: fa761ddebc946f9b46509d84945bf41ee1a9ec49
+    revision: fbabd6a06fd801c960078517ad47f7994130b944
     version: null
     source:
       Git: https://github.com/pulp-platform/Insitu-Cache.git

Bender.yml

@@ -14,7 +14,7 @@ dependencies:
   register_interface:  { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.8                }
   riscv-dbg:           { git: "https://github.com/pulp-platform/riscv-dbg.git",          version: 0.7.0                }
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11               }
-  Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/cachepool_dev  }
+  Insitu-Cache:        { git: "https://github.com/pulp-platform/Insitu-Cache.git",       rev:     zexin/sync-flush-fixes }
   spatz:               { git: "https://github.com/pulp-platform/spatz.git",              rev:     cachepool-32b        }
   dram_rtl_sim:        { git: "https://github.com/pulp-platform/dram_rtl_sim.git",       rev:     cachepool            }
 
@@ -49,6 +49,10 @@ sources:
   - hardware/src/cachepool_cluster.sv
   # Level 4
   - hardware/tb/cachepool_cluster_wrapper.sv
+  # sim-only verification IP (bind-attached; excluded from synth/lint)
+  - target: simulation
+    files:
+    - hardware/src/verif/cachepool_tile_tcdm_checker.sv
   # testbench
   - target: cachepool_test
     files:

Makefile

@@ -251,6 +251,12 @@ VLOG_DEFS += -DL1D_TILE_SIZE=$(l1d_tile_size)
 VLOG_DEFS += -DL1D_TAG_DATA_WIDTH=$(l1d_tag_data_width)
 VLOG_DEFS += -DL1D_NUM_BANKS=$(l1d_num_banks)
 VLOG_DEFS += -DL1D_DEPTH=$(l1d_depth)
+# L1 data-bank micro-architecture knobs (1=on/0=off). Production = folded(1) +
+# hash-way(1) + fwd-buffer(1). Unfolded conventional = folded(0)+hash(0)+fwd(0).
+VLOG_DEFS += -DL1D_USE_FOLDED=$(l1d_use_folded)
+VLOG_DEFS += -DL1D_FOLD_WAY_GROUP=$(l1d_fold_way_group)
+VLOG_DEFS += -DL1D_USE_HASH_WAY=$(l1d_use_hash_way)
+VLOG_DEFS += -DL1D_USE_FWD_BUF=$(l1d_use_fwd_buf)
 
 # CachePool CC / core cluster
 VLOG_DEFS += -DSPATZ_FPU_EN=$(spatz_fpu_en)
@@ -277,6 +283,8 @@ VLOG_DEFS += -DPERIPH_START_ADDR=$(periph_start_addr)
 VLOG_DEFS += -DBOOT_ADDR=$(boot_addr)
 VLOG_DEFS += -DUART_ADDR=$(uart_addr)
 
+VLOG_DEFS += -DENABLE_SPATZ_REQ_SCOREBOARD
+
 ENABLE_CACHEPOOL_TESTS ?= 1
 
 # Bender targets

config/cachepool_2t_fpu_512.mk

@@ -0,0 +1,101 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# 2-tile / 8-core FPU variant of cachepool_fpu_512.
+# Bisect point between 1t/4c (works) and 4t/16c (broken) to isolate
+# whether the bug is in the inter-tile (group-level) xbar at all, or
+# only at 4t.
+
+#########################
+##  CachePool Cluster  ##
+#########################
+
+# Number of tiles
+num_tiles ?= 2
+
+# Number of cores
+num_cores ?= 8
+
+# Core datawidth
+data_width ?= 32
+
+# Core addrwidth
+addr_width ?= 32
+
+num_remote_ports_per_tile ?= 1
+
+
+######################
+##  CachePool Tile  ##
+######################
+
+# Number of cores per CachePool tile
+num_cores_per_tile ?= 4
+
+# Refill interconnection data width
+refill_data_width ?= 128
+
+##### L1 Data Cache #####
+
+# L1 data cacheline width (in Bit)
+l1d_cacheline_width ?= 512
+
+# L1 data cache size (in KiB)
+l1d_size ?= 256
+
+# L1 data cache banking factor (how many banks per core?)
+l1d_bank_factor ?= 1
+
+# L1 coalecsing window
+l1d_coal_window ?= 2
+
+# L1 data cache number of ways per
+l1d_num_way ?= 4
+
+# L1 data cache size per tile (KiB)
+l1d_tile_size ?= 256
+
+# L1 data cache tag width (TODO: should be calcualted)
+l1d_tag_data_width ?= 92
+
+####################
+##  CachePool CC  ##
+####################
+# Spatz fpu support?
+spatz_fpu_en ?= 1
+
+# Spatz number of FPU
+spatz_num_fpu ?= 4
+
+# Spatz number of IPU
+spatz_num_ipu ?= 4
+
+# Spatz max outstanding transactions
+spatz_max_trans ?= 32
+
+# Snitch/FPU max outstanding transactions
+snitch_max_trans ?= 16
+
+
+#####################
+##  L2 Main Memory ##
+#####################
+# L2 number of channels
+l2_channel ?= 4
+
+# L2 bank width (DRAM width, change with care)
+l2_bank_width ?= 512
+
+# L2 interleaving factor (in order of bank_width)
+l2_interleave ?= 16
+
+
+##################
+##  Peripherals ##
+##################
+# Hardware stack size (in Byte)
+stack_hw_size ?= 1024
+
+# Stack size (total, including share and private, 32'h800)
+stack_tot_size ?= 2048

config/cachepool_512.mk

@@ -9,10 +9,10 @@
 #########################
 
 # Number of tiles
-num_tiles ?= 4
+num_tiles ?= 1
 
 # Number of cores
-num_cores ?= 16
+num_cores ?= 4
 
 # Core datawidth
 data_width ?= 32
@@ -54,6 +54,18 @@ l1d_tile_size ?= 256
 # L1 data cache tag width (TODO: should be calcualted)
 l1d_tag_data_width ?= 92
 
+# L1 data-bank micro-architecture (1=on, 0=off).
+# Production cache  = folded(1) + hash-way(1) + fwd-buffer(1).
+# Unfolded "conventional" cache = folded(0) + hash-way(0) + fwd-buffer(0).
+# Constraints (enforced by RTL elaboration asserts):
+#   - folded (l1d_use_folded=1) REQUIRES l1d_use_hash_way=1
+#   - fwd-buffer (l1d_use_fwd_buf=1) REQUIRES l1d_use_hash_way=1
+# l1d_fold_way_group=0 => auto (min(4, ways)).
+l1d_use_folded     ?= 1
+l1d_fold_way_group ?= 0
+l1d_use_hash_way   ?= 1
+l1d_use_fwd_buf    ?= 1
+
 ####################
 ##  CachePool CC  ##
 ####################

config/cachepool_fpu_512.mk

@@ -56,6 +56,18 @@ l1d_tile_size ?= 256
 # L1 data cache tag width (TODO: should be calcualted)
 l1d_tag_data_width ?= 92
 
+# L1 data-bank micro-architecture (1=on, 0=off).
+# Production cache  = folded(1) + hash-way(1) + fwd-buffer(1).
+# Unfolded "conventional" cache = folded(0) + hash-way(0) + fwd-buffer(0).
+# Constraints (enforced by RTL elaboration asserts):
+#   - folded (l1d_use_folded=1) REQUIRES l1d_use_hash_way=1
+#   - fwd-buffer (l1d_use_fwd_buf=1) REQUIRES l1d_use_hash_way=1
+# l1d_fold_way_group=0 => auto (min(4, ways)).
+l1d_use_folded     ?= 1
+l1d_fold_way_group ?= 0
+l1d_use_hash_way   ?= 1
+l1d_use_fwd_buf    ?= 1
+
 ####################
 ##  CachePool CC  ##
 ####################

config/config.mk

@@ -105,14 +105,57 @@ snitch_max_trans ?= 16
 ##  AXI configuration  ##
 #########################
 
+# axi_user_width sets the AXI 'user' field that carries refill_user_t over the
+# cache->L2 AXI.  Hard requirement: axi_user_width >= $bits(refill_user_t).
+# This floor is now enforced in RTL by ASSERT_INIT(CheckAxiUserFitsRefillUser)
+# in cachepool_cluster.sv, and the cluster zero-extends refill_user_t onto the
+# (wider) AXI user port at the reqrsp_to_axi call site.
+#
+#   refill_user_t = bank_id(BankIDWidth) + tile_id(TileIDWidth)
+#                 + cache_info_t + burst_req_t
+#   cache_info_t  = {for_write_pend, depth, way}   -- NOTE: NO tile_id inside.
+#
+# So refill_user_t carries TileIDWidth exactly ONCE.  The values below are
+# deliberately conservative headroom, not an exact fit: the per-tile adjustment
+# adds 2*(idx_width(NumTiles)-1) bits, and cachepool_pkg.sv:163 then adds a
+# further clog2(NumTiles) (SpatzAxiUserWidth = AXI_USER_WIDTH + clog2(NumTiles)),
+# so the tile term ends up over-provisioned.  This is harmless: no RTL reads any
+# AXI user bit above $bits(refill_user_t)-1.
+# (An earlier version of this comment claimed cache_info_t held a second
+#  TileIDWidth copy and therefore doubled idx_width(NumTiles) -- it does not;
+#  the 2x factor is just slack, kept as-is for headroom.)
+#
+# Do NOT let axi_user_width drop below $bits(refill_user_t): the MSB of bank_id
+# (or higher tile_id) would be truncated on the AXI loopback and refill
+# responses would route back to the wrong slv port (e.g. bank_id=4 aliases to
+# bank_id=0, sending cb=3's refill response to the icache bypass slot, making
+# cb=3 hang).  The ASSERT_INIT above catches this at elaboration.
+
+ifeq ($(num_tiles),1)
+  axi_user_tile_adj := 0
+else ifeq ($(num_tiles),2)
+  axi_user_tile_adj := 0
+else ifeq ($(num_tiles),4)
+  axi_user_tile_adj := 2
+else ifeq ($(num_tiles),8)
+  axi_user_tile_adj := 4
+else ifeq ($(num_tiles),16)
+  axi_user_tile_adj := 6
+else
+  $(error num_tiles=$(num_tiles) not handled by axi_user_width formula; add a case in config.mk)
+endif
+
+# Base widths for NumTiles=1 (= reference values, verified working).
 ifeq ($(l1d_cacheline_width),512)
-  axi_user_width := 17
+  axi_user_base := 18
 else ifeq ($(l1d_cacheline_width),256)
-  axi_user_width := 18
+  axi_user_base := 19
 else ifeq ($(l1d_cacheline_width),128)
-  axi_user_width := 21
+  axi_user_base := 22
 endif
 
+axi_user_width := $(shell echo $$(( $(axi_user_base) + $(axi_user_tile_adj) )))
+
 #####################
 ##  L2 Main Memory ##
 #####################