Updates on pulp-runtime

bin/slm_hyper.py

@@ -1,7 +1,6 @@
 #!/usr/bin/python3
 
 #Written by ABA to update the format of the slm file to be compliant with hyperflash model used in testbench
-import numpy as np
 import os
 import os.path
 import argparse
@@ -24,7 +23,10 @@
 with open(args.input_file, "rU") as fi:
     data = list(map(lambda x:x.split(delimiter), fi.read().strip().split("\n")))
 fo=open(args.output_file, "w")
-A=np.array(data)
+
+# Write the header
 fo.write('@000000\n')
-for i in range(0, A.shape[0],2):
-    fo.write('%s%s\n' %(A[i+1][1],A[i][1]))
+
+# Iterate over rows in pairs
+for i in range(0, len(data)-1, 2):  # subtract 1 to avoid IndexError if odd number of rows
+    fo.write(f'{data[i+1][1]}{data[i][1]}\n')

drivers/host_uart.c

@@ -0,0 +1,49 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+// Adapted from Cheshire
+
+#include "host_uart.h"
+
+static inline volatile uint8_t *reg8(void *base, int offs) {
+    return (volatile uint8_t *)(base + offs);
+}
+
+static inline void fence() {
+    asm volatile("fence" ::: "memory");
+}
+
+int uart_read_ready(void *uart_base) {
+    return *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_DATA_READY_BIT);
+}
+
+static inline int __uart_write_ready(void *uart_base) {
+    return *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_THR_EMPTY_BIT);
+}
+
+static inline int __uart_write_idle(void *uart_base) {
+    return __uart_write_ready(uart_base) &&
+           *reg8(uart_base, UART_LINE_STATUS_REG_OFFSET) & (1 << UART_LINE_STATUS_TMIT_EMPTY_BIT);
+}
+
+void uart_write(void *uart_base, uint8_t byte) {
+    while (!__uart_write_ready(uart_base))
+        ;
+    *reg8(uart_base, UART_THR_REG_OFFSET) = byte;
+}
+
+void uart_write_flush(void *uart_base) {
+    fence();
+    while (!__uart_write_idle(uart_base))
+        ;
+}
+
+uint8_t uart_read(void *uart_base) {
+    while (!uart_read_ready(uart_base))
+        ;
+    return *reg8(uart_base, UART_RBR_REG_OFFSET);
+}

drivers/include/host_uart.h

@@ -0,0 +1,42 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+// Adapted from Cheshire
+
+#pragma once
+
+#include <stdint.h>
+
+// Register offsets
+#define UART_RBR_REG_OFFSET 0
+#define UART_THR_REG_OFFSET 0
+#define UART_INTR_ENABLE_REG_OFFSET 4
+#define UART_INTR_IDENT_REG_OFFSET 8
+#define UART_FIFO_CONTROL_REG_OFFSET 8
+#define UART_LINE_CONTROL_REG_OFFSET 12
+#define UART_MODEM_CONTROL_REG_OFFSET 16
+#define UART_LINE_STATUS_REG_OFFSET 20
+#define UART_MODEM_STATUS_REG_OFFSET 24
+#define UART_DLAB_LSB_REG_OFFSET 0
+#define UART_DLAB_MSB_REG_OFFSET 4
+
+// Register fields
+#define UART_LINE_STATUS_DATA_READY_BIT 0
+#define UART_LINE_STATUS_THR_EMPTY_BIT 5
+#define UART_LINE_STATUS_TMIT_EMPTY_BIT 6
+
+int uart_read_ready(void *uart_base);
+
+void uart_write(void *uart_base, uint8_t byte);
+
+void uart_write_str(void *uart_base, void *src, uint64_t len);
+
+void uart_write_flush(void *uart_base);
+
+uint8_t uart_read(void *uart_base);
+
+void uart_read_str(void *uart_base, void *dst, uint64_t len);

include/archi/chips/astral-cluster/memory_map.h

@@ -60,6 +60,7 @@
 #define ARCHI_FC_ITC_ADDR            ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_ITC_OFFSET )
 #define ARCHI_FC_TIMER_ADDR          ( ARCHI_SOC_PERIPHERALS_ADDR + ARCHI_FC_TIMER_OFFSET )
 #define ARCHI_STDOUT_ADDR            0x03002000
+#define ARCHI_HOST_UART_ADDR         0x03002000
 
 #define ARCHI_FLL_AREA_SIZE          0x00000010
 

include/archi/chips/carfield-cluster/memory_map.h

@@ -100,6 +100,7 @@
 #define ARCHI_MCHAN_EXT_OFFSET           0x00001800
 #define ARCHI_HMR_OFFSET                 0x00002000
 #define ARCHI_TCDM_SCRUBBER_OFFSET       0x00002400
+#define ARCHI_HWPE_HCI_ECC_OFFSET        0x00002800
 
 #define ARCHI_CLUSTER_PERIPHERALS_ADDR             ( ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
 #define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) ( ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET )
@@ -111,6 +112,7 @@
 #define ARCHI_MCHAN_EXT_ADDR                       ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_MCHAN_EXT_OFFSET )
 #define ARCHI_HMR_ADDR                             ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HMR_OFFSET )
 #define ARCHI_TCDM_SCRUBBER_ADDR                   ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_TCDM_SCRUBBER_OFFSET )
+#define ARCHI_HWPE_HCI_ECC_ADDR                    ( ARCHI_CLUSTER_PERIPHERALS_ADDR + ARCHI_HWPE_HCI_ECC_OFFSET )
 
 #define ARCHI_CLUSTER_CTRL_GLOBAL_ADDR(cid)        ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_CTRL_OFFSET )
 #define ARCHI_ICACHE_CTRL_GLOBAL_ADDR(cid)         ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_ICACHE_CTRL_OFFSET )
@@ -120,6 +122,7 @@
 #define ARCHI_IDMA_EXT_GLOBAL_ADDR(cid)            ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_IDMA_EXT_OFFSET )
 #define ARCHI_HMR_GLOBAL_ADDR(cid)                 ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HMR_OFFSET )
 #define ARCHI_TCDM_SCRUBBER_GLOBAL_ADDR(cid)       ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_TCDM_SCRUBBER_OFFSET )
+#define ARCHI_HWPE_HCI_ECC_GLOBAL_ADDR(cid)        ( ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid) + ARCHI_HWPE_HCI_ECC_OFFSET )
 
 
 /*

include/archi/chips/carfield-cluster/properties.h

@@ -89,7 +89,7 @@
 #define ARCHI_HAS_CLUSTER   1
 #define ARCHI_L1_TAS_BIT    20
 #ifndef ARCHI_CLUSTER_NB_PE
-#define ARCHI_CLUSTER_NB_PE 12
+#define ARCHI_CLUSTER_NB_PE 8
 #endif
 #define ARCHI_NB_CLUSTER    1
 

include/archi/chips/carfield-cluster/pulp.h

@@ -47,5 +47,6 @@
 #include "archi/udma/udma_v3.h"
 #include "archi/hmr/hmr_v1.h"
 #include "archi/tcdm_scrubber/tcdm_scrubber.h"
+#include "archi/hwpe_hci_ecc/hwpe_hci_ecc.h"
 
 #endif

include/archi/chips/pulp_cluster/properties.h

@@ -18,6 +18,8 @@
 #ifndef __ARCHI_CHIPS_PULP_PROPERTIES_H__
 #define __ARCHI_CHIPS_PULP_PROPERTIES_H__
 
+#define ARCHI_HAS_DMA_DEMUX 1
+
 /*
  * FPGA
  */

include/archi/dma/idma_v2.h

@@ -301,4 +301,4 @@ extern "C" {
 }  // extern "C"
 #endif
 #endif  // _IDMA_REG32_3D_REG_DEFS_
-// End generated register defines for idma_reg32_3d
+// End generated register defines for idma_reg32_3d

include/hal/chips/carfield-cluster/pulp.h

@@ -43,5 +43,6 @@
 #include "hal/udma/uart/udma_uart_v1.h"
 #include "hal/hmr/hmr_v1.h"
 #include "hal/tcdm_scrubber/tcdm_scrubber.h"
+#include "hal/hwpe_hci_ecc/hwpe_hci_ecc.h"
 
 #endif

include/hal/chips/pulp_cluster/pulp.h

@@ -26,14 +26,14 @@
 #endif // __ibex__
 #include "hal/eu/eu_v3.h"
 #include "hal/itc/itc_v1.h"
+#include "hal/cluster_ctrl/cluster_ctrl_v2.h"
 #ifndef USE_IDMA
 #include "hal/dma/mchan_v7.h"
 #else
 #include "hal/dma/idma_v2.h"
 #endif
 #include "hal/timer/timer_v2.h"
 #include "hal/soc_eu/soc_eu_v2.h"
-#include "hal/cluster_ctrl/cluster_ctrl_v2.h"
 #include "hal/icache/icache_ctrl_v2.h"
 #include "hal/apb_soc/apb_soc_v3.h"
 #include "hal/fll/fll_v1.h"

include/hal/cluster_ctrl/cluster_ctrl_v2.h

@@ -71,4 +71,12 @@ static inline void hal_cluster_ctrl_return_set_remote(int cid, int value){
   pulp_write32(ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)+ARCHI_CLUSTER_CTRL_OFFSET+ARCHI_CLUSTER_CTRL_RETURN, value | 1 << ARCHI_CLUSTER_CTRL_RETURN_SHIFT_BITS);
 }
 
+static inline void plp_ctrl_cluster_cfg_set(unsigned int mask) {
+  pulp_write32(ARCHI_CLUSTER_CTRL_ADDR + ARCHI_CLUSTER_CTRL_CLUSTER_CFG, mask);
+}
+
+static inline int plp_ctrl_cluster_cfg_get() {
+  return pulp_read32(ARCHI_CLUSTER_CTRL_ADDR + ARCHI_CLUSTER_CTRL_CLUSTER_CFG);
+}
+
 #endif

include/hal/dma/idma_v2.h

@@ -266,7 +266,7 @@ static inline int pulp_cl_idma_L2ToL1_2d(unsigned int src, unsigned int dst, uns
   */
 
 static inline int pulp_idma_L1ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps);
-static inline int pulp_idma_cl_L1ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps);
+static inline int pulp_cl_idma_L1ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps);
 
 
 
@@ -341,6 +341,7 @@ static inline int pulp_cl_idma_zeromem(unsigned int dst, unsigned short size, id
 
 /** DMA barrier.
  * This blocks the core until no transfer is on-going in the DMA.
+ * Careful: these only wait for transfers towards L2
  */
 static inline void plp_dma_barrier();
 static inline void plp_cl_dma_barrier();
@@ -476,6 +477,19 @@ static inline unsigned int plp_cl_dma_status_toL1();
 static inline unsigned int plp_dma_status_toL2();
 static inline unsigned int plp_cl_dma_status_toL2();
 
+/* CLOCK GATING PROCEDURE FOR iDMA */
+/*  Three modes are supported:
+    - No clock: the whole iDMA is unresponsive
+    - Frontend-only clock: only the iDMA frontend is clocked. This way power consumption
+      is kept to a minimum while still being responsive to incoming transfer requests.
+    - Fully clocked: both the frontend and datapath of iDMA are clocked. Notice that
+      clock gating for the dapath is fully managed in rtl.
+*/
+
+// Enables the frontend clock
+static inline void plp_idma_enable_clk();
+// Disables the frontend clock
+static inline void plp_idma_disable_clk();
 
 //!@}
 
@@ -510,6 +524,22 @@ static inline unsigned int plp_cl_dma_status_toL2();
 #define DMA_CL_READ(offset) DMA_READ(value, offset)
 #endif
 
+//
+// CLOCK GATING CONTROL
+//
+
+static inline void plp_idma_enable_clk() {
+  uint32_t cluster_ctrl_cfg_reg;
+  cluster_ctrl_cfg_reg = plp_ctrl_cluster_cfg_get();
+  plp_ctrl_cluster_cfg_set(cluster_ctrl_cfg_reg | (1 << 17));
+}
+
+static inline void plp_idma_disable_clk() {
+  uint32_t cluster_ctrl_cfg_reg;
+  cluster_ctrl_cfg_reg = plp_ctrl_cluster_cfg_get();
+  plp_ctrl_cluster_cfg_set(cluster_ctrl_cfg_reg & (0 << 17));
+}
+
 static inline int plp_dma_memcpy(dma_ext_t ext, unsigned int loc, unsigned short size, int ext2loc) {
   if (ext2loc)
     return pulp_idma_L2ToL1(ext, loc, size);
@@ -782,7 +812,6 @@ static inline int pulp_cl_idma_L2ToL1(unsigned int src, unsigned int dst, unsign
   asm volatile("" : : : "memory");
   // Launch TX
   dma_tx_id = DMA_CL_READ(IDMA_REG32_3D_NEXT_ID_1_REG_OFFSET);
-
   return dma_tx_id;
 }
 
@@ -900,6 +929,7 @@ static inline int pulp_idma_L2ToL1_2d(unsigned int src, unsigned int dst, unsign
   dma_tx_id = DMA_READ(IDMA_REG32_3D_NEXT_ID_1_REG_OFFSET);
   return dma_tx_id;
 }
+
 static inline int pulp_cl_idma_L2ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps) {
   unsigned int dma_tx_id;
   unsigned int cfg = IDMA_DEFAULT_CONFIG_L2TOL1_2D;
@@ -916,7 +946,6 @@ static inline int pulp_cl_idma_L2ToL1_2d(unsigned int src, unsigned int dst, uns
   return dma_tx_id;
 }
 
-
 static inline int pulp_idma_L1ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps) {
   unsigned int dma_tx_id;
   unsigned int cfg = IDMA_DEFAULT_CONFIG_L1TOL1_2D;
@@ -932,6 +961,7 @@ static inline int pulp_idma_L1ToL1_2d(unsigned int src, unsigned int dst, unsign
   dma_tx_id = DMA_READ(IDMA_REG32_3D_NEXT_ID_1_REG_OFFSET);
   return dma_tx_id;
 }
+
 static inline int pulp_cl_idma_L1ToL1_2d(unsigned int src, unsigned int dst, unsigned short size, unsigned int src_stride, unsigned int dst_stride, unsigned int num_reps) {
   unsigned int dma_tx_id;
   unsigned int cfg = IDMA_DEFAULT_CONFIG_L1TOL1_2D;
@@ -1076,6 +1106,7 @@ static inline int pulp_idma_zeromem(unsigned int dst, unsigned short size, idma_
   asm volatile("" : : : "memory");
   return dma_tx_id;
 }
+
 static inline int pulp_cl_idma_zeromem(unsigned int dst, unsigned short size, idma_prot_t dst_prot) {
   unsigned int dma_tx_id;
   unsigned int cfg = IDMA_DEFAULT_CONFIG;
@@ -1091,6 +1122,10 @@ static inline int pulp_cl_idma_zeromem(unsigned int dst, unsigned short size, id
   return dma_tx_id;
 }
 
+//
+// BARRIERS
+//
+
 
 static inline void plp_dma_barrier() {
   while(plp_dma_status()) {
@@ -1125,4 +1160,4 @@ static inline void plp_cl_dma_barrier_toL2() {
   }
 }
 
-#endif // __HAL_IDMA_V2_H__
+#endif // __HAL_IDMA_V2_H__