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hw: fix double bw vlsu#100

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Navaneeth-KunhiPurayil wants to merge 9 commits into
mainfrom
fix/vle
Open

hw: fix double bw vlsu#100
Navaneeth-KunhiPurayil wants to merge 9 commits into
mainfrom
fix/vle

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@Navaneeth-KunhiPurayil
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Fixed

  1. Simpler synchronization for both double-bandwidth interfaces. Both interfaces now always commit together. If interface1 conflicts at the VRF, it is buffered. Interface1 is always the one that sends the response to the controller to retire the instruction.
  2. Fix address generation for strided loads in double bandwidth vlsu

Added

  1. Instruction test for strided loads vlse

@Navaneeth-KunhiPurayil Navaneeth-KunhiPurayil self-assigned this Jun 1, 2026
@Navaneeth-KunhiPurayil Navaneeth-KunhiPurayil marked this pull request as draft June 1, 2026 07:19
@Navaneeth-KunhiPurayil Navaneeth-KunhiPurayil marked this pull request as ready for review June 1, 2026 08:50
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@DiyouS DiyouS left a comment

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Hi Navaneeth, in general looks good to me. But there are some small details can be improved.

if (sb_enable_o[port]) begin
// VFU and VSLDU: intID derived from vl_cnt progress, vl_cnt updated every successful write
if (port inside {SB_VFU_VD_WD, SB_VSLDU_VD_WD}) begin
automatic logic intID = (vl_cnt_q[sb_id_i[port]] < vl_max_d[sb_id_i[port]]) ? 0 : 1;
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Might be better to avoid using automatic for debugging purposes


#include "vector_macros.h"

int8_t mask[1] = {0xAA};
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will this data be stored on address 0x0? Might be better to add attribute here. I saw these issues in cache-version, and cause illegal visits to DRAMSys

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2 participants