feat(riscv): i64 Phase 2 — mul, shifts, rotates, compares, clz/ctz/popcnt, sign-extends

[avrabe]

Summary

Phase 2 of RV32IMAC i64 support, building on Phase 1 (v0.3.1, #119). 16 new i64 ops, all lowering to RV32IMAC base-ISA instruction sequences via the typed VstackVal register-pair model.

Implemented (16 ops)

• I64Mul — low-64 product. lo = mul(al,bl); hi = mulhu(al,bl) + mul(al,bh) + mul(ah,bl).
• I64Shl / I64ShrS / I64ShrU — runtime-amount shifts with a data-dependent bne on bit 5 of shamt & 63. Cross-half carry uses a two-step (lo>>1)>>(31-s) so it stays well-defined at s==0 (avoids RV's >>32 == >>0 masking).
• I64Rotl / I64Rotr — composed from two cross-word shifts ORed half-by-half.
• I64Clz / I64Ctz / I64Popcnt — base-ISA software (no Zbb). clz branches hi-vs-lo; clz_word is an unrolled branchless binary search. ctz via 31 - clz(x & -x). popcnt is SWAR per half.
• I64{Lt,Le,Gt,Ge}{S,U} — hi-then-lo comparison ladder; Le/Gt/Ge derived from Lt by operand swap + invert.
• I64Extend8S/16S/32S — (x << (32-w)) >>s (32-w) then srai lo,31 to broadcast the sign.

Deferred to Phase 3

I64DivS/DivU/RemS/RemU — RV32 has no 64-bit divide; an inline __divdi3-style long division would balloon the selector and there's no runtime-call path yet. They fall through to the existing SelectorError::Unsupported arm (a test pins this).

Tests

+23 tests (125 → 148 passing, 1 pre-existing ignored). One+ per op; both shift cross-word cases pinned (i64_shl_big_case_zeroes_low_half, i64_shl_small_case_uses_register_shifts_and_carry_or), the clz hi-vs-lo branch pinned, signed + unsigned compares both covered.

Note on the diff

git diff --stat reports 2312 insertions / 699 deletions, but no functions or tests were removed — verified: all 108 functions from main are present in the branch (now 145, +37). The "deletions" are blank-line reflow artifacts from cargo fmt interleaving with the large additions. Function-name set diff main → branch is empty for removals.

Validation

• cargo test --package synth-backend-riscv — 148 pass, 0 fail, 1 ignored.
• cargo clippy --package synth-backend-riscv --all-targets -- -D warnings — clean.
• cargo fmt --check — clean.

Follow-ups

• i64 div/rem (Phase 3) — needs a __divdi3-style runtime or a runtime-call path.
• Sub-word i64 loads (i64.load8_s etc.) still unimplemented — noted in the module doc.

🤖 Generated with Claude Code

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.

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