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OSFG is toggled from _PTS/_WAK via MPTS/MWAK and therefore runs for all supported sleep states. Update the suspend/resume comments to match the unguarded behavior. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I613efd68ed2770798c2754a1c59f802f47986795 Reviewed-on: https://review.coreboot.org/c/coreboot/+/91439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The m920q and m720q are the same board, so rename the m920q to reflect that Change-Id: Ieef22530207ad4c35ac3cb4255d2ad65e62b65bf Signed-off-by: Tom Hiller <thrilleratplay@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90374 Reviewed-by: Evie (Ivi) Ballou <iviballou@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Linux btintel driver requires DSM function 3 (DSM_SET_RESET_METHOD) to be supported before it will use the ACPI _PRR/_RST reset path. Without it, the driver falls back to GPIO or USB reset. Add set_reset_method callback that returns success. coreboot only supports WDISABLE2 (GPIO); the _RST method already implements the toggle. Update the capability buffer (0x03 -> 0x0b) to advertise function 3 support. Change RDLY default from 105 to 160 ms to match the Linux driver. Change-Id: I6a7c9289dcffbbbd769ab3fb4e59765d2fef7598 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91445 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a weak devtree_update() hook and invoke it early in ramstage at BS_PRE_DEVICE. Mainboards can override devtree_update() to enable/disable devices at runtime based on CMOS/NVRAM settings. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic84ddb25e1da050543c230ea457042b8a8a3061f Reviewed-on: https://review.coreboot.org/c/coreboot/+/91250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
devtree_update() is invoked automatically at BS_PRE_DEVICE. Remove the per-board init_mainboard() calls and associated includes. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifb44080dc2e785a8554f5404902540daa9e872d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90990 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a common implementation of soc_fill_soundwire_controller() to reduce code duplication across multiple Intel SoC platforms. This implementation consolidates identical SoundWire link configuration code from Alder Lake, Meteor Lake, Panther Lake, and Tiger Lake platforms. The common driver uses platform-specific Kconfig options: - SOC_SOUNDWIRE_ACPI_ADDRESS: ACPI address for the controller (default 0x40000000) - SOC_SOUNDWIRE_MASTER_COUNT: Number of SoundWire master links (default 4) Platforms can override these defaults in their Kconfig if needed. This change enables consolidation of nearly identical soundwire.c files across four platforms, reducing duplication by approximately 210 lines. Change-Id: I5e188b0b60da91a33cf0325caefbbcabef0ebcba Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91276 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common SoundWire driver implementation from the Intel common feature code. This change eliminates platform- specific code by leveraging the shared soundwire.c driver. This commit: - Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig - Removes src/soc/intel/alderlake/soundwire.c - Updates Makefile to remove soundwire.c compilation Alder Lake uses the default values (4 SoundWire master links with ACPI address 0x40000000). Change-Id: Idf21d32d0cab9e3c6ca35e2b9f20c42c0455b5bb Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Meteor Lake to use the common SoundWire driver implementation from the Intel common feature code. This change eliminates platform- specific code by leveraging the shared soundwire.c driver. This commit: - Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig - Removes src/soc/intel/meteorlake/soundwire.c - Updates Makefile to remove soundwire.c compilation Meteor Lake uses the default values (4 SoundWire master links with ACPI address 0x40000000). Change-Id: Ib6d412b22cce78caf56ca2d09fcf74e57f54d09c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91278 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Panther Lake to use the common SoundWire driver implementation from the Intel common feature code. This change eliminates platform- specific code by leveraging the shared soundwire.c driver. This commit: - Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig - Removes src/soc/intel/pantherlake/soundwire.c - Updates Makefile to remove soundwire.c compilation Panther Lake uses the default values (4 SoundWire master links with ACPI address 0x40000000). TEST=Build and boot to the OS on a Fatcat device Change-Id: Iaebb27ddc44da536c8e6a6aece1dfee3a4ac7bac Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Tiger Lake to use the common SoundWire driver implementation from the Intel common feature code. This change eliminates platform- specific code by leveraging the shared soundwire.c driver. This commit: - Selects SOC_INTEL_COMMON_FEATURE_SOUNDWIRE Kconfig - Removes src/soc/intel/tigerlake/soundwire.c - Updates Makefile to remove soundwire.c compilation Tiger Lake uses the default values (4 SoundWire master links with ACPI address 0x40000000). Change-Id: Ife743d28c8760d9de3f593f7d8caafd7a73efe3a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
This introduces a common implementation for eSPI/LPC initialization that handles generic IO decode range configuration and standard interrupt setup. This code is nearly identical across multiple Intel client platforms. The implementation includes: - soc_get_gen_io_dec_range(): Configures generic IO decode ranges from devicetree (gen1_dec through gen4_dec) - lpc_soc_init(): Performs legacy ISA/DMA initialization, enables CLKRUN for power gating, configures Serial IRQ mode, and sets up the interrupt controllers (IOAPIC, PIRQ, i8259) Platform-specific configuration is handled through the config_t typedef that each platform defines via its soc_chip.h header, eliminating the need for preprocessor conditionals. The common driver is enabled via the SOC_INTEL_COMMON_FEATURE_ESPI Kconfig option and works across bootblock, romstage, and ramstage. Platforms that will use this common implementation: - Alder Lake - Meteor Lake - Panther Lake - Tiger Lake - Jasper Lake - Elkhart Lake Change-Id: Idbdecff1cef44dae90afb35ff6e2afca011ea5b4 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91216 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/alderlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. Change-Id: Ifacdd480a9cfd59d9e54faebad82e1cc2db8a8ed Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91217 Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/meteorlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. Change-Id: Ifb198964c5eda1fceaec6111cd7fba374bacf1b6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/pantherlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. TEST=Build and boot to the OS on a Fatcat device Change-Id: If5f2de9faa209ff30f986f34b1816ffa6d5fc683 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91219 Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/tigerlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. Change-Id: I65f8af8f5abccff25ec0dead4f7def7ce16d3081 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91220 Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/jasperlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. Change-Id: Ied29a5f2dabdebe0afedd1d69e4a817d6606a82d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
Replace platform-specific espi.c with the common eSPI/LPC initialization driver. Changes: - Remove src/soc/intel/elkhartlake/espi.c - Enable SOC_INTEL_COMMON_FEATURE_ESPI in Kconfig - Update Makefile.mk to remove espi.c from build The eSPI/LPC initialization was nearly identical across platforms, differing only in minor header inclusions and ENV_RAMSTAGE wrapper usage. The common implementation uses the config_t typedef that each platform defines, providing clean abstraction without preprocessor conditionals. Change-Id: I59d9cb1b37bca2c682e2bf87fc3f5b24c34fb920 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
This adds a common PM utility driver for modern Intel platforms that share consistent PM register layouts. The driver consolidates power management utility functions that were previously duplicated across multiple Intel SoC platforms. This includes functions for: - SMI/TCO/GPE status bit decoding - PMC MMIO base address access - RTC failure detection - Sleep state management - Power state structure population - After-G3 power state configuration - GPE configuration retrieval using generic config_t The GPE configuration function (soc_get_gpi_gpe_configs) uses the generic config_t typedef that each platform defines, allowing complete code reuse without platform-specific shims. This common driver is controlled by the Kconfig option SOC_INTEL_COMMON_FEATURE_PMUTIL and is built for all boot stages. Change-Id: I45b829b7c18ee66474457df5523069f930806b35 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Alder Lake to use the common PMC utility driver instead of maintaining platform-specific pmutil.c code. This change: - Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig - Removes platform-specific pmutil.c - Removes pmutil.c from Makefile.mk The common driver provides all necessary functionality through the generic config_t interface, eliminating ~290 lines of duplicated code. Change-Id: Ieb62ffac95550a0ae8607a3a9ae76e0f6ff0ac35 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Panther Lake to use the common PMC utility driver instead of maintaining platform-specific pmutil.c code. This change: - Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig - Removes platform-specific pmutil.c - Removes pmutil.c from Makefile.mk The common driver provides all necessary functionality through the generic config_t interface, eliminating ~290 lines of duplicated code. TEST=Build and boot to the OS on a Fatcat device Change-Id: I3ee9630a6b15d7b02776ff633a3cff0766a8915b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91239 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Meteor Lake to use the common PMC utility driver instead of maintaining platform-specific pmutil.c code. This change: - Enables SOC_INTEL_COMMON_FEATURE_PMUTIL in Kconfig - Removes platform-specific pmutil.c - Removes pmutil.c from Makefile.mk The common driver provides all necessary functionality through the generic config_t interface, eliminating ~290 lines of duplicated code. Change-Id: I1c46a517420c8ea7410c4ed7e8e7b761d4399cf9 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Add a common implementation of SMI handler code for PCH client platforms to reduce code duplication across Alder Lake, Meteor Lake, Panther Lake, and Tiger Lake platforms. This implementation consolidates: - smihandler_soc_disable_busmaster(): Skip disabling PMC bus master - southbridge_smi array: Standard SMI handler mappings The common driver uses a platform-specific macro that must be defined in each platform's soc/pci_devs.h header: - SOC_PMC_DEV: PMC PCI device identifier This change enables consolidation of nearly identical smihandler.c files across four platforms, reducing duplication by approximately 100+ lines. Change-Id: I9ecb65b7ea4feafb8acbaf5798bbeaeb80b7c24a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91293 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Alder Lake to use the common PCH client SMI handler implementation from the Intel common feature code. This change eliminates platform-specific code by leveraging the shared smihandler.c driver. This commit: - Adds SOC_PMC_DEV macro definition to soc/pci_devs.h - Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig - Removes src/soc/intel/alderlake/smihandler.c - Updates Makefile to remove smihandler.c compilation Alder Lake uses PCH_DEV_PMC as the PMC device identifier. Change-Id: Icbbc7af25e73e952c9b5f811cf0bbe01efe3ae94 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Migrate Meteor Lake to use the common PCH client SMI handler implementation from the Intel common feature code. This change eliminates platform-specific code by leveraging the shared smihandler.c driver. This commit: - Adds SOC_PMC_DEV macro definition to soc/pci_devs.h - Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig - Removes src/soc/intel/meteorlake/smihandler.c - Updates Makefile to remove smihandler.c compilation Meteor Lake uses PCI_DEV_PMC as the PMC device identifier. Change-Id: Ia21a6ee0c6fbee6d4ffcfce5fdbe9b3bdf5fcece Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91295 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Panther Lake to use the common PCH client SMI handler implementation from the Intel common feature code. This change eliminates platform-specific code by leveraging the shared smihandler.c driver. This commit: - Adds SOC_PMC_DEV macro definition to soc/pci_devs.h - Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig - Removes src/soc/intel/pantherlake/smihandler.c - Updates Makefile to remove smihandler.c compilation Panther Lake uses PCI_DEV_PMC as the PMC device identifier. TEST=Build and boot to the OS on a Fatcat device Change-Id: I32bf4b678e7edda598319086acccc4983edcbe3e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91296 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Migrate Tiger Lake to use the common PCH client SMI handler implementation from the Intel common feature code. This change eliminates platform-specific code by leveraging the shared smihandler.c driver. This commit: - Adds SOC_PMC_DEV macro definition to soc/pci_devs.h - Selects SOC_INTEL_COMMON_FEATURE_SMIHANDLER Kconfig - Removes src/soc/intel/tigerlake/smihandler.c - Updates Makefile to remove smihandler.c compilation Tiger Lake uses PCH_DEV_PMC as the PMC device identifier. Change-Id: Ibe06e4d100b2715aeccfe0ff85dc944ab6cd80fc Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91297 Reviewed-by: Huang, Cliff <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the SOC_I2C_DEVFN(n) macro definitions that were duplicated in a separate "for common code" section at the end of multiple platform pci_devs.h files. Platforms affected: - Alder Lake - Cannon Lake - Elkhart Lake - Jasper Lake - Skylake - Tiger Lake Change-Id: Ie3b3e6a25b0dba1beeadad1ab9acf59cafdbcf4a Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Guvendik, Bora <bora.guvendik@intel.com>
As the card reader isn't on a dedicated USB interface for all variants for the StarLite, default to disable to ensure that an unused USB port isn't enabled. Change-Id: I2176fd6556797e468012c98f7e482b9573b5e3f7 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Set the default power profile to Performance, regardless of whether there is a fan present. Change-Id: Id1d624355f9f08b5abb154e26026e70675322ddb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Enable the card reader USB port, along with ACPI driver info and the CFR option to control it. Change-Id: I30dd26438f0a7b355061a45b9ffb7f447c89a751 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Updating from commit id a5b3d0e056ad: 2025-12-22 09:38:25 +0800 - (Renaming directory back to "IoT" to fix the corrupted path) to commit id 81399b3b6147: 2026-02-24 08:49:28 +0800 - (ECG BTL-S 12P PV (6311_62) FSP) This brings in 13 new commits: 81399b3b6147 ECG BTL-S 12P PV (6311_62) FSP 53b5040674c2 Edge Platforms ARL -UH IPU 2026.2 (5385_51) FSP 635793898797 TWL IPU26.2 v6491_51 3aebe88923ec ASL IPU26.2 v6491_51 45e148caeda5 ADL-N IPU26.2 v6491_51 6749aee0aae0 ADL-N IPU26.2 6491_51 a230e1e778d1 FSP Integration Guide 77d47e8d6f64 FSP Integration Guide 23cf258760b0 Update README.md d7ab4a17f30d Update README.md 57141c9f85f9 TWL MR2 IPU26.1 v6457_50 faea68792e93 ASL MR5 IPU26.1 v6457_50 309053b4ae5a Create AmstonLake folder Change-Id: I52cb07feec06ee456b3aca40fbc049715da650cf Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Updating from commit id f910b0a225d6: 2025-11-10 16:26:35 -0600 - (microcode-20251111 Release) to commit id 250941fb6706: 2026-02-27 10:50:11 -0600 - (microcode-20260227 Release) This brings in 3 new commits: 250941fb6706 microcode-20260227 Release 439ddde999b0 microcode-20260210-rev1 Release b24397c3611f microcode-20260210 Release Change-Id: I9eb7a1e70f3c58e1964bd9ffe963f059c97a583e Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91714 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add fw_config_probe_mainboard_override() hook that allows mainboards to selectively override specific fw_config probes. The hook returns whether the function handed the probe or not. If set to true, the hook's 'result' parameter is returned; otherwise, standard fw_config logic is used automatically. This enables mainboards to override probes based on runtime conditions (e.g., CFR options) without reimplementing standard fw_config logic. The change is backward compatible as the default hook doesn't handle any probes. TEST=tested with subsequent patch Change-Id: I6b9207eb9097ef5296fb5c41d8d1acbfde68b445 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for selecting NVMe or eMMC storage via CFR option on taeko and taniks variants. Override fw_config_probe() to check the CFR "storage_device" option and enable/disable the appropriate PCIe root port based on user selection. This allows runtime configuration of storage devices while ensuring only the selected device is initialized, since initializing both causes neither to be detected. TEST=build/boot taeko, verify both eMMC and NVMe M.2 storage modules functional when correct type selected from setup menu. Change-Id: Ic555f93763736adb5837534b8011aa9c123fea08 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The colour components are in RGB order in the structure returned by the ACPI `_PLD` method, so use the same order in the C struct as well. This has no impact since nobody currently specifies port colours with this. Change-Id: I11b486faaf73f5da37b973180f23e8b3f19f3f5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91389 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop send_psp_command_smm() and let the generic send_psp_command() method handle SMM as special case. This allows to use the same method in regular code and SMM. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I5dad79e80b97e9d4dfbcd0d84d49eb23ea3f83cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/91702 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Glinda is an alias for Strix. This only changes the SoC name in amdfwtool; SoC folder will be renamed later once all remaining patches have been upstreamed, since renaming the SoC folder right now, would just make the upstreaming more difficult. Change-Id: I10cb9c4a97dd2689fe02329262772b05d24a5896 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Faegan is an alias for Krackan2e. This only changes the SoC name in amdfwtool; the Faegan SoC variant name in the glinda folder will be renamed later once all remaining patches have been upstreamed, to not make the upstreaming more difficult than necessary. Change-Id: I051e163170d4363594dcff4b505d01cabfb3a190 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Add the OPAL packet builder and unlock logic used by the SMM resume path. Uses the TCG storage encoder and NVMe Security Send/Receive helpers to perform the Admin1/User1 Set Global Range unlock sequence. TEST=tested with rest of patch train Change-Id: I4cdb16e13c1aeb89648db49672b77598a8b42fac Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Produced by running: util/vboot_list/vboot_list.sh Change-Id: I2c59e921e1160c4df739ad827161ee0af40fec39 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91729 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
These are the preliminary release notes. They'll need to be updated with any changes done this week. We'll need another patch after the tag to capture the final statistics. The notes will be changed from "Upcoming release" after the tag is done. Change-Id: Id24c2d43c53db7976c98f5936d9d8866a7392ad2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91731 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This adds the release notes template for the upcoming June 2026 release of coreboot. Change-Id: I4a436ba1b649ce1091c6e496768ef7dc41776668 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91730 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Martin L Roth <gaumless@gmail.com>
The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume on S3 with the error `TPM_RC_VALUE`. Per TPM2 spec, handle the failure by performing a TPM Restart. > The startup behavior defined by this specification is different than > TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter > Failure Mode if no state is available when the TPM receives > Startup(STATE). This is not the case in this specification. It is up > to the CRTM to take corrective action if it the TPM returns > TPM_RC_VALUE in response to Startup(STATE). Fixes the following error from being repeatedly logged in Linux: > kernel: tpm tpm0: A TPM error (256) occurred attempting get random Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59 Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b Signed-off-by: Tim Crawford <tcrawford@system76.com>
Previously, only _PR0 was specified, which allowed devices to enter D0. Add _PR3 to allow the same devices to enter D3Cold, enabling proper runtime power management for devices that support it. Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15 Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Ic30bec272e82535f6f606033c3ba512662cb2c8b Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
These values were taken from alderlake. Change-Id: Ib790c7d52748156b25bad423ed082c1b51a33550 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This config is not available in coreboot FSP headers, but is required for USB3 to work correctly. Change-Id: I9f69935123b8d3e2a7f93318ea39667d8a9efe0d Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The driver provides ACPI support for dynamically powering on and off the GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU power in romstage. References: - DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide - DG-09954-001: NVIDIA GN20/QN20 Software Design Guide Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
System76 EC supports a lock bit on Clevo-based boards (`ME_WE`) that prevents writing its flash when enabled. Extend this lock to system flash by protecting regions when the `SECURITY` feature is present and enabled. Change-Id: Ifd5f77e8516bfd538409a079022f444a571d4e72 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has been updated with a Thunderbolt 5 controller (Barlow Ridge). Identified chip changes from the schematics: - JHL8540_MP -> JHL9580_QS - TPS65994BF -> TPS65994BH - IT5570E-128 -> IT5570E-256 Change-Id: I784e489cdd034febeaaac0182ab5b4fe672381ec Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Meerkat 9 is an Intel Meteor Lake-H based small form factor desktop computer based on the Asus NUC-155H R2. Change-Id: I37a0b808cf383379b8e284831644c824c0d4817e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Ibc3401463084173483ef2c98e4241af6557607ce Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I35b792e0298700f41fc8469fcf9c75a1bae3d4d4 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3 resume, causing the units to not power on in the EC code. Switch them to S0ix as a workaround. Enable CSME in CMOS options by default so that S0ix will work. Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I1b2ec2ec95f5d29e71e4d99a76a0d186679fd101 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Update from the 25.03 tag to the 26.03 tag. Current branch is preserved as
system76-25.03.Commits not upstreamed
Reference for commits not upstreamed. I try to push them to gerrit and keep them in sync, but some have been squashed or modified to handle dependencies with other uncommitted changes.
TODO
gpio.cfromsystem76-25.03if necessary