Sorting deeds done down the chip
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Updated
Aug 15, 2023 - Julia
Sorting deeds done down the chip
A join pipeline inspired by the 2025 sigmod programming contest
Matrix package with cache-aware lock-free tiling optimization in Go
A high-performance ANN library which targets cache-aware design
Contains source code to carry out tests & analyse the results of various branch predictors against each other. Additionally, demonstrates the benefits of cache-oblivious algorithms. Done as part of VL-803 Processor Architecture course at IIIT-B (Spring 2020).
A deterministic, ultra-low latency C++20 execution engine for hardware-constrained environments, eliminating allocation, locking, and syscall overhead to achieve sub-200ns processing through cache-aware, lock-free design and explicit memory ordering.
A high-performance ANN library which targets cache-aware design
A C++ concurrency learning repository with implementations of various synchronization primitives and concurrent data structures.
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